ide: remove ->INB, ->OUTB and ->OUTBSYNC methods
* Remove no longer needed ->INB, ->OUTB and ->OUTBSYNC methods. Then: * Remove no longer used default_hwif_[mm]iops() and ide_[mm_]outbsync(). * Cleanup SuperIO handling in ns87415.c. There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
parent
1823649b5a
commit
761052e676
14 changed files with 15 additions and 115 deletions
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@ -469,8 +469,6 @@ icside_register_v5(struct icside_state *state, struct expansion_card *ec)
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if (!hwif)
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return -ENODEV;
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default_hwif_mmiops(hwif);
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state->hwif[0] = hwif;
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ecard_set_drvdata(ec, state);
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@ -547,14 +545,11 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec)
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return -ENODEV;
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hwif->chipset = ide_acorn;
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default_hwif_mmiops(hwif);
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idx[0] = hwif->index;
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mate = ide_find_port();
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if (mate) {
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default_hwif_mmiops(mate);
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hws[1] = &hw[1];
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idx[1] = mate->index;
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}
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@ -399,8 +399,6 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
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i = hwif->index;
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default_hwif_mmiops(hwif);
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idx[0] = i;
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ide_device_add(idx, &palm_bk3710_port_info, hws);
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@ -59,8 +59,6 @@ rapide_probe(struct expansion_card *ec, const struct ecard_id *id)
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goto release;
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}
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default_hwif_mmiops(hwif);
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idx[0] = hwif->index;
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ide_device_add(idx, &rapide_port_info, hws);
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@ -171,8 +171,6 @@ static inline void hw_setup(hw_regs_t *hw)
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static inline void hwif_setup(ide_hwif_t *hwif)
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{
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default_hwif_iops(hwif);
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hwif->tf_load = h8300_tf_load;
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hwif->tf_read = h8300_tf_read;
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@ -42,18 +42,6 @@ static void ide_outb (u8 val, unsigned long port)
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outb(val, port);
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}
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static void ide_outbsync(ide_hwif_t *hwif, u8 addr, unsigned long port)
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{
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outb(addr, port);
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}
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void default_hwif_iops (ide_hwif_t *hwif)
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{
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hwif->OUTB = ide_outb;
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hwif->OUTBSYNC = ide_outbsync;
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hwif->INB = ide_inb;
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}
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/*
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* MMIO operations, typically used for SATA controllers
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*/
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@ -68,22 +56,6 @@ static void ide_mm_outb (u8 value, unsigned long port)
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writeb(value, (void __iomem *) port);
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}
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static void ide_mm_outbsync(ide_hwif_t *hwif, u8 value, unsigned long port)
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{
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writeb(value, (void __iomem *) port);
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}
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void default_hwif_mmiops (ide_hwif_t *hwif)
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{
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hwif->OUTB = ide_mm_outb;
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/* Most systems will need to override OUTBSYNC, alas however
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this one is controller specific! */
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hwif->OUTBSYNC = ide_mm_outbsync;
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hwif->INB = ide_mm_inb;
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}
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EXPORT_SYMBOL(default_hwif_mmiops);
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void SELECT_DRIVE (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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@ -101,7 +101,6 @@ void ide_init_port_data(ide_hwif_t *hwif, unsigned int index)
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init_completion(&hwif->gendev_rel_comp);
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default_hwif_iops(hwif);
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default_hwif_transport(hwif);
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ide_port_init_devices_data(hwif);
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@ -103,10 +103,8 @@ static int __devinit plat_ide_probe(struct platform_device *pdev)
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plat_ide_setup_ports(&hw, base, alt_base, pdata, res_irq->start);
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hw.dev = &pdev->dev;
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if (mmio) {
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if (mmio)
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d.host_flags |= IDE_HFLAG_MMIO;
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default_hwif_mmiops(hwif);
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}
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idx[0] = hwif->index;
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@ -120,9 +120,6 @@ static int __devinit swarm_ide_probe(struct device *dev)
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if (hwif == NULL)
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goto err;
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/* Setup MMIO ops. */
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default_hwif_mmiops(hwif);
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idx[0] = hwif->index;
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ide_device_add(idx, &swarm_port_info, hws);
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@ -28,10 +28,6 @@
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*/
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#include <asm/superio.h>
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static unsigned long superio_ide_status[2];
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static unsigned long superio_ide_select[2];
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static unsigned long superio_ide_dma_status[2];
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#define SUPERIO_IDE_MAX_RETRIES 25
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/* Because of a defect in Super I/O, all reads of the PCI DMA status
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@ -40,27 +36,18 @@ static unsigned long superio_ide_dma_status[2];
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*/
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static u8 superio_ide_inb (unsigned long port)
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{
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if (port == superio_ide_status[0] ||
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port == superio_ide_status[1] ||
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port == superio_ide_select[0] ||
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port == superio_ide_select[1] ||
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port == superio_ide_dma_status[0] ||
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port == superio_ide_dma_status[1]) {
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u8 tmp;
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int retries = SUPERIO_IDE_MAX_RETRIES;
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u8 tmp;
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int retries = SUPERIO_IDE_MAX_RETRIES;
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/* printk(" [ reading port 0x%x with retry ] ", port); */
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/* printk(" [ reading port 0x%x with retry ] ", port); */
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do {
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tmp = inb(port);
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if (tmp == 0)
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udelay(50);
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} while (tmp == 0 && retries-- > 0);
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do {
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tmp = inb(port);
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if (tmp == 0)
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udelay(50);
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} while (tmp == 0 && retries-- > 0);
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return tmp;
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}
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return inb(port);
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return tmp;
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}
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static u8 superio_read_status(ide_hwif_t *hwif)
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@ -120,27 +107,20 @@ static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
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static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
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{
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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u32 base, dmabase;
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u32 dma_stat;
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u8 port = hwif->channel, tmp;
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base = pci_resource_start(pdev, port * 2) & ~3;
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dmabase = pci_resource_start(pdev, 4) & ~3;
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superio_ide_status[port] = base + 7;
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superio_ide_select[port] = base + 6;
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superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
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dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
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/* Clear error/interrupt, enable dma */
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tmp = superio_ide_inb(superio_ide_dma_status[port]);
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outb(tmp | 0x66, superio_ide_dma_status[port]);
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tmp = superio_ide_inb(dma_stat);
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outb(tmp | 0x66, dma_stat);
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hwif->read_status = superio_read_status;
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hwif->read_sff_dma_status = superio_read_sff_dma_status;
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hwif->tf_read = superio_tf_read;
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/* We need to override inb to workaround a SuperIO errata */
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hwif->INB = superio_ide_inb;
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}
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static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
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@ -188,14 +188,6 @@ static void scc_ide_outb(u8 addr, unsigned long port)
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out_be32((void*)port, addr);
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}
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static void scc_ide_outbsync(ide_hwif_t *hwif, u8 addr, unsigned long port)
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{
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out_be32((void*)port, addr);
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eieio();
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in_be32((void*)(hwif->dma_base + 0x01c));
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eieio();
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}
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static void
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scc_ide_outsw(unsigned long port, void *addr, u32 count)
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{
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hwif->input_data = scc_input_data;
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hwif->output_data = scc_output_data;
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hwif->INB = scc_ide_inb;
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hwif->OUTB = scc_ide_outb;
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hwif->OUTBSYNC = scc_ide_outbsync;
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hwif->dma_base = dma_base;
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hwif->config_data = ports->ctl;
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}
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@ -623,9 +623,6 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
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if (hwif == NULL)
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goto err;
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/* The IOC4 uses MMIO rather than Port IO. */
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default_hwif_mmiops(hwif);
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/* Initializing chipset IRQ Registers */
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writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
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@ -601,7 +601,7 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
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* Fill in the basic hwif bits
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*/
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hwif->host_flags |= IDE_HFLAG_MMIO;
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default_hwif_mmiops(hwif);
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hwif->hwif_data = addr;
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/*
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@ -486,15 +486,6 @@ pmac_ide_do_update_timings(ide_drive_t *drive)
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pmac_ide_selectproc(drive);
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}
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static void pmac_outbsync(ide_hwif_t *hwif, u8 value, unsigned long port)
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{
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u32 tmp;
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writeb(value, (void __iomem *) port);
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tmp = readl((void __iomem *)(hwif->io_ports.data_addr
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+ IDE_TIMING_CONFIG));
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}
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static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
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{
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writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
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hwif->exec_command = pmac_exec_command;
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hwif->set_irq = pmac_set_irq;
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/* Setup MMIO ops */
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default_hwif_mmiops(hwif);
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hwif->OUTBSYNC = pmac_outbsync;
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idx[0] = hwif->index;
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ide_device_add(idx, &d, hws);
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@ -504,11 +504,6 @@ typedef struct hwif_s {
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void (*ide_dma_clear_irq)(ide_drive_t *drive);
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void (*OUTB)(u8 addr, unsigned long port);
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void (*OUTBSYNC)(struct hwif_s *hwif, u8 addr, unsigned long port);
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u8 (*INB)(unsigned long port);
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/* dma physical region descriptor table (cpu view) */
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unsigned int *dmatable_cpu;
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/* dma physical region descriptor table (dma view) */
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}
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#endif
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extern void default_hwif_iops(ide_hwif_t *);
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extern void default_hwif_mmiops(ide_hwif_t *);
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extern void default_hwif_transport(ide_hwif_t *);
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typedef struct ide_pci_enablebit_s {
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