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[POWERPC] 8xx: Work around CPU15 erratum.

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The CPU15 erratum on MPC8xx chips can cause incorrect code execution
under certain circumstances, where there is a conditional or indirect
branch in the last word of a page, with a target in the last cache line
of the next page.  This patch implements one of the suggested
workarounds, by forcing a TLB miss whenever execution crosses a page
boundary.  This is done by invalidating the pages before and after the
one being loaded into the TLB in the ITLB miss handler.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Scott Wood 2007-06-25 14:50:41 -05:00 committed by Kumar Gala
parent 663edbd264
commit 7401685242
2 changed files with 22 additions and 0 deletions
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6
arch/powerpc/kernel/head_8xx.S
View file

@ -298,6 +298,12 @@ InstructionTLBMiss:
stw r10, 0(r0)
stw r11, 4(r0)
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
#ifdef CONFIG_8xx_CPU15
addi r11, r10, 0x1000
tlbie r11
addi r11, r10, -0x1000
tlbie r11
#endif
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */

16
arch/powerpc/platforms/8xx/Kconfig
View file

@ -100,6 +100,22 @@ config 8xx_CPU6
If in doubt, say N here.
config 8xx_CPU15
bool "CPU15 Silicon Errata"
default y
help
This enables a workaround for erratum CPU15 on MPC8xx chips.
This bug can cause incorrect code execution under certain
circumstances. This workaround adds some overhead (a TLB miss
every time execution crosses a page boundary), and you may wish
to disable it if you have worked around the bug in the compiler
(by not placing conditional branches or branches to LR or CTR
in the last word of a page, with a target of the last cache
line in the next page), or if you have used some other
workaround.
If in doubt, say Y here.
choice
prompt "Microcode patch selection"
default NO_UCODE_PATCH