sh: intc - rework core code
This patch reworks the intc core, implementing the following features: - Support dual priority registers - one set and one clear register - All 8/16/32 bit register combinations are now supported - Both single mask and single enable bitmap register are supported - Add code to set interrupt priority - Speedup sense and priority configuration code - Allocate data using bootmem, allows intc data structures to be __initdata - Save memory - allocated memory footprint is smaller than intc structures Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
6ef5fb2cfc
commit
73505b445d
3 changed files with 345 additions and 229 deletions
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@ -50,7 +50,7 @@ static struct intc_vect vectors[] = {
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};
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static struct intc_mask_reg mask_registers[] = {
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{ VOYAGER_INT_MASK, 1, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
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{ VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
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{ UP, G54, G53, G52, G51, G50, G49, G48,
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I2C, PW, 0, DMA, PCI, I2S, AC, US,
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0, 0, U1, U0, CV, MC, S1, S0,
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@ -20,176 +20,227 @@
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/bootmem.h>
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#define _INTC_MK(fn, idx, bit, value) \
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((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
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#define _INTC_FN(h) (h >> 24)
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#define _INTC_VALUE(h) ((h >> 16) & 0xff)
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#define _INTC_IDX(h) ((h >> 8) & 0xff)
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#define _INTC_BIT(h) (h & 0xff)
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#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
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((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
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((addr_e) << 16) | ((addr_d << 24)))
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#define _INTC_PTR(desc, member, data) \
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(desc->member + _INTC_IDX(data))
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#define _INTC_SHIFT(h) (h & 0x1f)
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#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
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#define _INTC_FN(h) ((h >> 9) & 0xf)
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#define _INTC_MODE(h) ((h >> 13) & 0x7)
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#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
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#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
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static inline struct intc_desc *get_intc_desc(unsigned int irq)
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struct intc_handle_int {
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unsigned int irq;
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unsigned long handle;
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};
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struct intc_desc_int {
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unsigned long *reg;
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unsigned int nr_reg;
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struct intc_handle_int *prio;
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unsigned int nr_prio;
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struct intc_handle_int *sense;
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unsigned int nr_sense;
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struct irq_chip chip;
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};
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static unsigned int intc_prio_level[NR_IRQS]; /* for now */
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static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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return (void *)((char *)chip - offsetof(struct intc_desc, chip));
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return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
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}
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static inline unsigned int set_field(unsigned int value,
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unsigned int field_value,
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unsigned int width,
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unsigned int shift)
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unsigned int handle)
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{
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unsigned int width = _INTC_WIDTH(handle);
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unsigned int shift = _INTC_SHIFT(handle);
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value &= ~(((1 << width) - 1) << shift);
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value |= field_value << shift;
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return value;
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}
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static inline unsigned int set_prio_field(struct intc_desc *desc,
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unsigned int value,
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unsigned int priority,
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unsigned int data)
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static void write_8(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
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return set_field(value, priority, width, _INTC_BIT(data));
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ctrl_outb(set_field(0, data, h), addr);
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}
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static void disable_prio_16(struct intc_desc *desc, unsigned int data)
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static void write_16(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
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ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
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ctrl_outw(set_field(0, data, h), addr);
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}
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static void enable_prio_16(struct intc_desc *desc, unsigned int data)
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static void write_32(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
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unsigned int prio = _INTC_VALUE(data);
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ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
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ctrl_outl(set_field(0, data, h), addr);
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}
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static void disable_prio_32(struct intc_desc *desc, unsigned int data)
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static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
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ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
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ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
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}
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static void enable_prio_32(struct intc_desc *desc, unsigned int data)
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static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
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unsigned int prio = _INTC_VALUE(data);
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ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
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ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
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}
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static void write_set_reg_8(struct intc_desc *desc, unsigned int data)
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static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
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{
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ctrl_outb(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->set_reg);
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ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
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}
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static void write_clr_reg_8(struct intc_desc *desc, unsigned int data)
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{
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ctrl_outb(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->clr_reg);
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}
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enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
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static void write_set_reg_32(struct intc_desc *desc, unsigned int data)
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{
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ctrl_outl(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->set_reg);
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}
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static void write_clr_reg_32(struct intc_desc *desc, unsigned int data)
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{
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ctrl_outl(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->clr_reg);
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}
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static void or_set_reg_16(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
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ctrl_outw(ctrl_inw(addr) | 1 << _INTC_BIT(data), addr);
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}
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static void and_set_reg_16(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
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ctrl_outw(ctrl_inw(addr) & ~(1 << _INTC_BIT(data)), addr);
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}
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static void or_set_reg_32(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
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ctrl_outl(ctrl_inl(addr) | 1 << _INTC_BIT(data), addr);
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}
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static void and_set_reg_32(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
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ctrl_outl(ctrl_inl(addr) & ~(1 << _INTC_BIT(data)), addr);
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}
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enum { REG_FN_ERROR=0,
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REG_FN_DUAL_8, REG_FN_DUAL_32,
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REG_FN_ENA_16, REG_FN_ENA_32,
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REG_FN_PRIO_16, REG_FN_PRIO_32 };
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static struct {
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void (*enable)(struct intc_desc *, unsigned int);
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void (*disable)(struct intc_desc *, unsigned int);
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} intc_reg_fns[] = {
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[REG_FN_DUAL_8] = { write_clr_reg_8, write_set_reg_8 },
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[REG_FN_DUAL_32] = { write_clr_reg_32, write_set_reg_32 },
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[REG_FN_ENA_16] = { or_set_reg_16, and_set_reg_16 },
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[REG_FN_ENA_32] = { or_set_reg_32, and_set_reg_32 },
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[REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
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[REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
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static void (*intc_reg_fns[])(unsigned long addr,
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unsigned long h,
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unsigned long data) = {
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[REG_FN_WRITE_BASE + 0] = write_8,
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[REG_FN_WRITE_BASE + 1] = write_16,
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[REG_FN_WRITE_BASE + 3] = write_32,
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[REG_FN_MODIFY_BASE + 0] = modify_8,
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[REG_FN_MODIFY_BASE + 1] = modify_16,
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[REG_FN_MODIFY_BASE + 3] = modify_32,
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};
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enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
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MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
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MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
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MODE_PRIO_REG, /* Priority value written to enable interrupt */
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MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
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};
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static void intc_mode_field(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
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}
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static void intc_mode_zero(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, 0);
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}
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static void intc_mode_prio(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, intc_prio_level[irq]);
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}
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static void (*intc_enable_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_field,
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[MODE_MASK_REG] = intc_mode_zero,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_prio,
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[MODE_PCLR_REG] = intc_mode_prio,
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};
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static void (*intc_disable_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_zero,
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[MODE_MASK_REG] = intc_mode_field,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_zero,
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[MODE_PCLR_REG] = intc_mode_field,
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};
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static inline void _intc_enable(unsigned int irq, unsigned long handle)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long addr = d->reg[_INTC_ADDR_E(handle)];
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intc_enable_fns[_INTC_MODE(handle)](addr, handle,
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intc_reg_fns[_INTC_FN(handle)],
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irq);
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}
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static void intc_enable(unsigned int irq)
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{
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struct intc_desc *desc = get_intc_desc(irq);
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unsigned int data = (unsigned int) get_irq_chip_data(irq);
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intc_reg_fns[_INTC_FN(data)].enable(desc, data);
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_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
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}
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static void intc_disable(unsigned int irq)
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{
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struct intc_desc *desc = get_intc_desc(irq);
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unsigned int data = (unsigned int) get_irq_chip_data(irq);
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struct intc_desc_int *desc = get_intc_desc(irq);
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unsigned long handle = (unsigned long) get_irq_chip_data(irq);
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unsigned long addr = desc->reg[_INTC_ADDR_D(handle)];
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intc_reg_fns[_INTC_FN(data)].disable(desc, data);
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intc_disable_fns[_INTC_MODE(handle)](addr, handle,
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intc_reg_fns[_INTC_FN(handle)],
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irq);
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}
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static void set_sense_16(struct intc_desc *desc, unsigned int data)
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static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
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unsigned int nr_hp,
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unsigned int irq)
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{
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unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
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unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
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unsigned int bit = _INTC_BIT(data);
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unsigned int value = _INTC_VALUE(data);
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int i;
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ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
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for (i = 0; i < nr_hp; i++) {
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if ((hp + i)->irq != irq)
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continue;
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return hp + i;
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}
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return NULL;
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}
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static void set_sense_32(struct intc_desc *desc, unsigned int data)
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int intc_set_priority(unsigned int irq, unsigned int prio)
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{
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unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
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unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
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unsigned int bit = _INTC_BIT(data);
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unsigned int value = _INTC_VALUE(data);
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struct intc_desc_int *d = get_intc_desc(irq);
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struct intc_handle_int *ihp;
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ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
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if (!intc_prio_level[irq] || prio <= 1)
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return -EINVAL;
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ihp = intc_find_irq(d->prio, d->nr_prio, irq);
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if (ihp) {
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if (prio >= ((1 << _INTC_WIDTH(ihp->handle)) - 1))
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return -EINVAL;
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intc_prio_level[irq] = prio;
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/*
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* only set secondary masking method directly
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* primary masking method is using intc_prio_level[irq]
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* priority level will be set during next enable()
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*/
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if (ihp->handle)
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_intc_enable(irq, ihp->handle);
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}
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return 0;
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}
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#define VALID(x) (x | 0x80)
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@ -203,92 +254,38 @@ static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
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static int intc_set_sense(unsigned int irq, unsigned int type)
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{
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struct intc_desc *desc = get_intc_desc(irq);
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
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unsigned int i, j, data, bit;
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intc_enum enum_id = 0;
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struct intc_handle_int *ihp;
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unsigned long addr;
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for (i = 0; i < desc->nr_vectors; i++) {
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struct intc_vect *vect = desc->vectors + i;
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if (evt2irq(vect->vect) != irq)
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continue;
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enum_id = vect->enum_id;
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break;
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}
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if (!enum_id || !value || !desc->sense_regs)
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if (!value)
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return -EINVAL;
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value ^= VALID(0);
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for (i = 0; i < desc->nr_sense_regs; i++) {
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struct intc_sense_reg *sr = desc->sense_regs + i;
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for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
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if (sr->enum_ids[j] != enum_id)
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continue;
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bit = sr->reg_width - ((j + 1) * sr->field_width);
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data = _INTC_MK(0, i, bit, value);
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switch(sr->reg_width) {
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case 16:
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set_sense_16(desc, data);
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break;
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case 32:
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set_sense_32(desc, data);
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break;
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}
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return 0;
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}
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ihp = intc_find_irq(d->sense, d->nr_sense, irq);
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if (ihp) {
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addr = d->reg[_INTC_ADDR_E(ihp->handle)];
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intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
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}
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return -EINVAL;
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return 0;
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}
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static unsigned int __init intc_find_dual_handler(unsigned int width)
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static unsigned int __init intc_get_reg(struct intc_desc_int *d,
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unsigned long address)
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{
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switch (width) {
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case 8:
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return REG_FN_DUAL_8;
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case 32:
|
||||
return REG_FN_DUAL_32;
|
||||
unsigned int k;
|
||||
|
||||
for (k = 0; k < d->nr_reg; k++) {
|
||||
if (d->reg[k] == address)
|
||||
return k;
|
||||
}
|
||||
|
||||
BUG();
|
||||
return REG_FN_ERROR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int __init intc_find_prio_handler(unsigned int width)
|
||||
{
|
||||
switch (width) {
|
||||
case 16:
|
||||
return REG_FN_PRIO_16;
|
||||
case 32:
|
||||
return REG_FN_PRIO_32;
|
||||
}
|
||||
|
||||
BUG();
|
||||
return REG_FN_ERROR;
|
||||
}
|
||||
|
||||
static unsigned int __init intc_find_ena_handler(unsigned int width)
|
||||
{
|
||||
switch (width) {
|
||||
case 16:
|
||||
return REG_FN_ENA_16;
|
||||
case 32:
|
||||
return REG_FN_ENA_32;
|
||||
}
|
||||
|
||||
BUG();
|
||||
return REG_FN_ERROR;
|
||||
}
|
||||
|
||||
static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id)
|
||||
static intc_enum __init intc_grp_id(struct intc_desc *desc,
|
||||
intc_enum enum_id)
|
||||
{
|
||||
struct intc_group *g = desc->groups;
|
||||
unsigned int i, j;
|
||||
|
|
@ -333,10 +330,12 @@ static unsigned int __init intc_prio_value(struct intc_desc *desc,
|
|||
}
|
||||
|
||||
static unsigned int __init intc_mask_data(struct intc_desc *desc,
|
||||
struct intc_desc_int *d,
|
||||
intc_enum enum_id, int do_grps)
|
||||
{
|
||||
struct intc_mask_reg *mr = desc->mask_regs;
|
||||
unsigned int i, j, fn;
|
||||
unsigned int i, j, fn, mode;
|
||||
unsigned long reg_e, reg_d;
|
||||
|
||||
for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
|
||||
mr = desc->mask_regs + i;
|
||||
|
|
@ -345,32 +344,46 @@ static unsigned int __init intc_mask_data(struct intc_desc *desc,
|
|||
if (mr->enum_ids[j] != enum_id)
|
||||
continue;
|
||||
|
||||
switch (mr->clr_reg) {
|
||||
case 1: /* 1 = enabled interrupt - "enable" register */
|
||||
fn = intc_find_ena_handler(mr->reg_width);
|
||||
break;
|
||||
default:
|
||||
fn = intc_find_dual_handler(mr->reg_width);
|
||||
if (mr->set_reg && mr->clr_reg) {
|
||||
fn = REG_FN_WRITE_BASE;
|
||||
mode = MODE_DUAL_REG;
|
||||
reg_e = mr->clr_reg;
|
||||
reg_d = mr->set_reg;
|
||||
} else {
|
||||
fn = REG_FN_MODIFY_BASE;
|
||||
if (mr->set_reg) {
|
||||
mode = MODE_ENABLE_REG;
|
||||
reg_e = mr->set_reg;
|
||||
reg_d = mr->set_reg;
|
||||
} else {
|
||||
mode = MODE_MASK_REG;
|
||||
reg_e = mr->clr_reg;
|
||||
reg_d = mr->clr_reg;
|
||||
}
|
||||
}
|
||||
|
||||
if (fn == REG_FN_ERROR)
|
||||
return 0;
|
||||
|
||||
return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
|
||||
fn += (mr->reg_width >> 3) - 1;
|
||||
return _INTC_MK(fn, mode,
|
||||
intc_get_reg(d, reg_e),
|
||||
intc_get_reg(d, reg_d),
|
||||
1,
|
||||
(mr->reg_width - 1) - j);
|
||||
}
|
||||
}
|
||||
|
||||
if (do_grps)
|
||||
return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0);
|
||||
return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int __init intc_prio_data(struct intc_desc *desc,
|
||||
struct intc_desc_int *d,
|
||||
intc_enum enum_id, int do_grps)
|
||||
{
|
||||
struct intc_prio_reg *pr = desc->prio_regs;
|
||||
unsigned int i, j, fn, bit, prio;
|
||||
unsigned int i, j, fn, mode, bit;
|
||||
unsigned long reg_e, reg_d;
|
||||
|
||||
for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
|
||||
pr = desc->prio_regs + i;
|
||||
|
|
@ -379,26 +392,69 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc,
|
|||
if (pr->enum_ids[j] != enum_id)
|
||||
continue;
|
||||
|
||||
fn = intc_find_prio_handler(pr->reg_width);
|
||||
if (fn == REG_FN_ERROR)
|
||||
return 0;
|
||||
if (pr->set_reg && pr->clr_reg) {
|
||||
fn = REG_FN_WRITE_BASE;
|
||||
mode = MODE_PCLR_REG;
|
||||
reg_e = pr->set_reg;
|
||||
reg_d = pr->clr_reg;
|
||||
} else {
|
||||
fn = REG_FN_MODIFY_BASE;
|
||||
mode = MODE_PRIO_REG;
|
||||
if (!pr->set_reg)
|
||||
BUG();
|
||||
reg_e = pr->set_reg;
|
||||
reg_d = pr->set_reg;
|
||||
}
|
||||
|
||||
prio = intc_prio_value(desc, enum_id, 1);
|
||||
fn += (pr->reg_width >> 3) - 1;
|
||||
bit = pr->reg_width - ((j + 1) * pr->field_width);
|
||||
|
||||
BUG_ON(bit < 0);
|
||||
|
||||
return _INTC_MK(fn, i, bit, prio);
|
||||
return _INTC_MK(fn, mode,
|
||||
intc_get_reg(d, reg_e),
|
||||
intc_get_reg(d, reg_d),
|
||||
pr->field_width, bit);
|
||||
}
|
||||
}
|
||||
|
||||
if (do_grps)
|
||||
return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0);
|
||||
return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
|
||||
static unsigned int __init intc_sense_data(struct intc_desc *desc,
|
||||
struct intc_desc_int *d,
|
||||
intc_enum enum_id)
|
||||
{
|
||||
struct intc_sense_reg *sr = desc->sense_regs;
|
||||
unsigned int i, j, fn, bit;
|
||||
|
||||
for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
|
||||
sr = desc->sense_regs + i;
|
||||
|
||||
for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
|
||||
if (sr->enum_ids[j] != enum_id)
|
||||
continue;
|
||||
|
||||
fn = REG_FN_MODIFY_BASE;
|
||||
fn += (sr->reg_width >> 3) - 1;
|
||||
bit = sr->reg_width - ((j + 1) * sr->field_width);
|
||||
|
||||
BUG_ON(bit < 0);
|
||||
|
||||
return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
|
||||
0, sr->field_width, bit);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init intc_register_irq(struct intc_desc *desc,
|
||||
struct intc_desc_int *d,
|
||||
intc_enum enum_id,
|
||||
unsigned int irq)
|
||||
{
|
||||
unsigned int data[2], primary;
|
||||
|
|
@ -410,15 +466,15 @@ static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
|
|||
* 4. priority, multiple interrupt sources (groups)
|
||||
*/
|
||||
|
||||
data[0] = intc_mask_data(desc, enum_id, 0);
|
||||
data[1] = intc_prio_data(desc, enum_id, 0);
|
||||
data[0] = intc_mask_data(desc, d, enum_id, 0);
|
||||
data[1] = intc_prio_data(desc, d, enum_id, 0);
|
||||
|
||||
primary = 0;
|
||||
if (!data[0] && data[1])
|
||||
primary = 1;
|
||||
|
||||
data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1);
|
||||
data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1);
|
||||
data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
|
||||
data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
|
||||
|
||||
if (!data[primary])
|
||||
primary ^= 1;
|
||||
|
|
@ -426,31 +482,91 @@ static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
|
|||
BUG_ON(!data[primary]); /* must have primary masking method */
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
set_irq_chip_and_handler_name(irq, &desc->chip,
|
||||
set_irq_chip_and_handler_name(irq, &d->chip,
|
||||
handle_level_irq, "level");
|
||||
set_irq_chip_data(irq, (void *)data[primary]);
|
||||
|
||||
/* record the desired priority level */
|
||||
intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);
|
||||
|
||||
/* enable secondary masking method if present */
|
||||
if (data[!primary])
|
||||
intc_reg_fns[_INTC_FN(data[!primary])].enable(desc,
|
||||
data[!primary]);
|
||||
_intc_enable(irq, data[!primary]);
|
||||
|
||||
/* add irq to d->prio list if priority is available */
|
||||
if (data[1]) {
|
||||
(d->prio + d->nr_prio)->irq = irq;
|
||||
if (!primary) /* only secondary priority can access regs */
|
||||
(d->prio + d->nr_prio)->handle = data[1];
|
||||
d->nr_prio++;
|
||||
}
|
||||
|
||||
/* add irq to d->sense list if sense is available */
|
||||
data[0] = intc_sense_data(desc, d, enum_id);
|
||||
if (data[0]) {
|
||||
(d->sense + d->nr_sense)->irq = irq;
|
||||
(d->sense + d->nr_sense)->handle = data[0];
|
||||
d->nr_sense++;
|
||||
}
|
||||
|
||||
/* irq should be disabled by default */
|
||||
desc->chip.mask(irq);
|
||||
d->chip.mask(irq);
|
||||
}
|
||||
|
||||
void __init register_intc_controller(struct intc_desc *desc)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int i, k;
|
||||
struct intc_desc_int *d;
|
||||
|
||||
desc->chip.mask = intc_disable;
|
||||
desc->chip.unmask = intc_enable;
|
||||
desc->chip.mask_ack = intc_disable;
|
||||
desc->chip.set_type = intc_set_sense;
|
||||
d = alloc_bootmem(sizeof(*d));
|
||||
|
||||
d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
|
||||
d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
|
||||
d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
|
||||
|
||||
d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
|
||||
k = 0;
|
||||
|
||||
if (desc->mask_regs) {
|
||||
for (i = 0; i < desc->nr_mask_regs; i++) {
|
||||
if (desc->mask_regs[i].set_reg)
|
||||
d->reg[k++] = desc->mask_regs[i].set_reg;
|
||||
if (desc->mask_regs[i].clr_reg)
|
||||
d->reg[k++] = desc->mask_regs[i].clr_reg;
|
||||
}
|
||||
}
|
||||
|
||||
if (desc->prio_regs) {
|
||||
d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
|
||||
|
||||
for (i = 0; i < desc->nr_prio_regs; i++) {
|
||||
if (desc->prio_regs[i].set_reg)
|
||||
d->reg[k++] = desc->prio_regs[i].set_reg;
|
||||
if (desc->prio_regs[i].clr_reg)
|
||||
d->reg[k++] = desc->prio_regs[i].clr_reg;
|
||||
}
|
||||
}
|
||||
|
||||
if (desc->sense_regs) {
|
||||
d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
|
||||
|
||||
for (i = 0; i < desc->nr_sense_regs; i++) {
|
||||
if (desc->sense_regs[i].reg)
|
||||
d->reg[k++] = desc->sense_regs[i].reg;
|
||||
}
|
||||
}
|
||||
|
||||
BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
|
||||
|
||||
d->chip.name = desc->name;
|
||||
d->chip.mask = intc_disable;
|
||||
d->chip.unmask = intc_enable;
|
||||
d->chip.mask_ack = intc_disable;
|
||||
d->chip.set_type = intc_set_sense;
|
||||
|
||||
for (i = 0; i < desc->nr_vectors; i++) {
|
||||
struct intc_vect *vect = desc->vectors + i;
|
||||
|
||||
intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));
|
||||
intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ struct intc_desc {
|
|||
unsigned int nr_prio_regs;
|
||||
struct intc_sense_reg *sense_regs;
|
||||
unsigned int nr_sense_regs;
|
||||
struct irq_chip chip;
|
||||
char *name;
|
||||
};
|
||||
|
||||
#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
|
||||
|
|
@ -86,7 +86,7 @@ struct intc_desc symbol = { \
|
|||
_INTC_ARRAY(priorities), \
|
||||
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
|
||||
_INTC_ARRAY(sense_regs), \
|
||||
.chip.name = chipname, \
|
||||
chipname, \
|
||||
}
|
||||
|
||||
void __init register_intc_controller(struct intc_desc *desc);
|
||||
|
|
|
|||
Loading…
Reference in a new issue