rtc-ds1302: add some abstraction for new platform support
The current ds1302 driver (or at least the one that lives in /drivers/rtc) seems to be designed for memory mapped devices only. This make it quite hard to add support for GPIO-based implementations (as this is the case for the upcoming Arcom Vulcan). This patch moves the direct register access to inline functions with explicit names. Still not as good as a proper platform driver, but at least neater. Signed-off-by: Marc Zyngier <maz@misterjones.org> Cc: Paul Gortmaker <p_gortmaker@yahoo.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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1 changed files with 67 additions and 18 deletions
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@ -16,7 +16,6 @@
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#include <linux/rtc.h>
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#include <linux/rtc.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/bcd.h>
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#include <linux/bcd.h>
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#include <asm/rtc.h>
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#define DRV_NAME "rtc-ds1302"
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#define DRV_NAME "rtc-ds1302"
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#define DRV_VERSION "0.1.1"
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#define DRV_VERSION "0.1.1"
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@ -34,14 +33,55 @@
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#define RTC_ADDR_MIN 0x01 /* Address of minute register */
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#define RTC_ADDR_MIN 0x01 /* Address of minute register */
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#define RTC_ADDR_SEC 0x00 /* Address of second register */
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#define RTC_ADDR_SEC 0x00 /* Address of second register */
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#ifdef CONFIG_SH_SECUREEDGE5410
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#include <asm/rtc.h>
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#include <mach/snapgear.h>
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#define RTC_RESET 0x1000
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#define RTC_RESET 0x1000
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#define RTC_IODATA 0x0800
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#define RTC_IODATA 0x0800
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#define RTC_SCLK 0x0400
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#define RTC_SCLK 0x0400
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#ifdef CONFIG_SH_SECUREEDGE5410
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#include <mach/snapgear.h>
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#define set_dp(x) SECUREEDGE_WRITE_IOPORT(x, 0x1c00)
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#define set_dp(x) SECUREEDGE_WRITE_IOPORT(x, 0x1c00)
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#define get_dp() SECUREEDGE_READ_IOPORT()
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#define get_dp() SECUREEDGE_READ_IOPORT()
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#define ds1302_set_tx()
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#define ds1302_set_rx()
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static inline int ds1302_hw_init(void)
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{
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return 0;
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}
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static inline void ds1302_reset(void)
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{
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set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
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}
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static inline void ds1302_clock(void)
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{
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set_dp(get_dp() | RTC_SCLK); /* clock high */
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set_dp(get_dp() & ~RTC_SCLK); /* clock low */
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}
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static inline void ds1302_start(void)
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{
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set_dp(get_dp() | RTC_RESET);
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}
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static inline void ds1302_stop(void)
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{
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set_dp(get_dp() & ~RTC_RESET);
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}
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static inline void ds1302_txbit(int bit)
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{
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set_dp((get_dp() & ~RTC_IODATA) | (bit ? RTC_IODATA : 0));
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}
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static inline int ds1302_rxbit(void)
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{
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return !!(get_dp() & RTC_IODATA);
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}
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#else
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#else
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#error "Add support for your platform"
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#error "Add support for your platform"
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#endif
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#endif
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@ -50,11 +90,11 @@ static void ds1302_sendbits(unsigned int val)
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{
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{
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int i;
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int i;
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ds1302_set_tx();
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for (i = 8; (i); i--, val >>= 1) {
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for (i = 8; (i); i--, val >>= 1) {
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set_dp((get_dp() & ~RTC_IODATA) | ((val & 0x1) ?
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ds1302_txbit(val & 0x1);
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RTC_IODATA : 0));
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ds1302_clock();
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set_dp(get_dp() | RTC_SCLK); /* clock high */
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set_dp(get_dp() & ~RTC_SCLK); /* clock low */
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}
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}
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}
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}
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@ -63,10 +103,11 @@ static unsigned int ds1302_recvbits(void)
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unsigned int val;
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unsigned int val;
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int i;
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int i;
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ds1302_set_rx();
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for (i = 0, val = 0; (i < 8); i++) {
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for (i = 0, val = 0; (i < 8); i++) {
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val |= (((get_dp() & RTC_IODATA) ? 1 : 0) << i);
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val |= (ds1302_rxbit() << i);
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set_dp(get_dp() | RTC_SCLK); /* clock high */
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ds1302_clock();
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set_dp(get_dp() & ~RTC_SCLK); /* clock low */
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}
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}
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return val;
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return val;
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@ -76,23 +117,24 @@ static unsigned int ds1302_readbyte(unsigned int addr)
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{
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{
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unsigned int val;
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unsigned int val;
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set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
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ds1302_reset();
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set_dp(get_dp() | RTC_RESET);
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ds1302_start();
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ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_READ);
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ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_READ);
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val = ds1302_recvbits();
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val = ds1302_recvbits();
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set_dp(get_dp() & ~RTC_RESET);
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ds1302_stop();
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return val;
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return val;
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}
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}
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static void ds1302_writebyte(unsigned int addr, unsigned int val)
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static void ds1302_writebyte(unsigned int addr, unsigned int val)
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{
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{
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set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
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ds1302_reset();
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set_dp(get_dp() | RTC_RESET);
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ds1302_start();
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ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_WRITE);
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ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_WRITE);
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ds1302_sendbits(val);
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ds1302_sendbits(val);
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set_dp(get_dp() & ~RTC_RESET);
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ds1302_stop();
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}
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}
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static int ds1302_rtc_read_time(struct device *dev, struct rtc_time *tm)
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static int ds1302_rtc_read_time(struct device *dev, struct rtc_time *tm)
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@ -167,13 +209,20 @@ static int __init ds1302_rtc_probe(struct platform_device *pdev)
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{
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{
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struct rtc_device *rtc;
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struct rtc_device *rtc;
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if (ds1302_hw_init()) {
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dev_err(&pdev->dev, "Failed to init communication channel");
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return -EINVAL;
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}
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/* Reset */
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/* Reset */
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set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
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ds1302_reset();
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/* Write a magic value to the DS1302 RAM, and see if it sticks. */
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/* Write a magic value to the DS1302 RAM, and see if it sticks. */
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ds1302_writebyte(RTC_ADDR_RAM0, 0x42);
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ds1302_writebyte(RTC_ADDR_RAM0, 0x42);
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if (ds1302_readbyte(RTC_ADDR_RAM0) != 0x42)
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if (ds1302_readbyte(RTC_ADDR_RAM0) != 0x42) {
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dev_err(&pdev->dev, "Failed to probe");
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return -ENODEV;
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return -ENODEV;
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}
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rtc = rtc_device_register("ds1302", &pdev->dev,
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rtc = rtc_device_register("ds1302", &pdev->dev,
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&ds1302_rtc_ops, THIS_MODULE);
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&ds1302_rtc_ops, THIS_MODULE);
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