ARM: clps711x: Fix lowlevel debug-macro

CTS signal can not be used for the port and tied to any logic state.
In this case we have an infinite loop waiting for the signal. For fix
this problem, checking CTS removed, waiting for the signal "busy" was
postponed after the byte write to the port.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
This commit is contained in:
Alexander Shiyan 2012-08-21 20:59:34 +04:00 committed by Arnd Bergmann
parent 61ae48c3cb
commit 7255f87a71

View file

@ -28,17 +28,11 @@
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
tst \rd, #1 << 11 @ UBUSYx
bne 1001b
.endm
.macro busyuart,rd,rx
tst \rx, #0x1000 @ UART2 does not have CTS here
bne 1002f
1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
tst \rd, #1 << 8 @ CTS
bne 1001b
1002:
.endm