ARM: clps711x: Fix lowlevel debug-macro
CTS signal can not be used for the port and tied to any logic state. In this case we have an infinite loop waiting for the signal. For fix this problem, checking CTS removed, waiting for the signal "busy" was postponed after the byte write to the port. Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
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1 changed files with 3 additions and 9 deletions
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@ -28,17 +28,11 @@
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.endm
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.macro waituart,rd,rx
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.endm
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.macro busyuart,rd,rx
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1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
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tst \rd, #1 << 11 @ UBUSYx
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bne 1001b
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.endm
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.macro busyuart,rd,rx
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tst \rx, #0x1000 @ UART2 does not have CTS here
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bne 1002f
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1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
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tst \rd, #1 << 8 @ CTS
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bne 1001b
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1002:
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.endm
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