tools/memory-model: Rename litmus tests to comply to norm7
norm7 produces the 'normalized' name of a litmus test, when the test can be generated from a single cycle that passes through each process exactly once. The commit renames such tests in order to comply to the naming scheme implemented by this tool. Signed-off-by: Andrea Parri <andrea.parri@amarulasolutions.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Cc: Akira Yokosawa <akiyks@gmail.com> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: David Howells <dhowells@redhat.com> Cc: Jade Alglave <j.alglave@ucl.ac.uk> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Luc Maranget <luc.maranget@inria.fr> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arch@vger.kernel.org Cc: parri.andrea@gmail.com Link: http://lkml.kernel.org/r/20180716180605.16115-14-paulmck@linux.vnet.ibm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Andrea Parri
Ingo Molnar
parent
0fcff1715b
commit
71b7ff5ebc
11 changed files with 30 additions and 30 deletions
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@ -126,7 +126,7 @@ However, it is not necessarily the case that accesses ordered by
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locking will be seen as ordered by CPUs not holding that lock.
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Consider this example:
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/* See Z6.0+pooncelock+pooncelock+pombonce.litmus. */
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/* See Z6.0+pooncerelease+poacquirerelease+fencembonceonce.litmus. */
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void CPU0(void)
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{
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spin_lock(&mylock);
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@ -292,7 +292,7 @@ and to use smp_load_acquire() instead of smp_rmb(). However, the older
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smp_wmb() and smp_rmb() APIs are still heavily used, so it is important
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to understand their use cases. The general approach is shown below:
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/* See MP+wmbonceonce+rmbonceonce.litmus. */
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/* See MP+fencewmbonceonce+fencermbonceonce.litmus. */
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void CPU0(void)
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{
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WRITE_ONCE(x, 1);
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@ -360,7 +360,7 @@ can be seen in the LB+poonceonces.litmus litmus test.
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One way of avoiding the counter-intuitive outcome is through the use of a
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control dependency paired with a full memory barrier:
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/* See LB+ctrlonceonce+mbonceonce.litmus. */
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/* See LB+fencembonceonce+ctrlonceonce.litmus. */
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void CPU0(void)
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{
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r0 = READ_ONCE(x);
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@ -476,7 +476,7 @@ that one CPU first stores to one variable and then loads from a second,
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while another CPU stores to the second variable and then loads from the
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first. Preserving order requires nothing less than full barriers:
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/* See SB+mbonceonces.litmus. */
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/* See SB+fencembonceonces.litmus. */
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void CPU0(void)
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{
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WRITE_ONCE(x, 1);
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@ -35,13 +35,13 @@ BASIC USAGE: HERD7
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The memory model is used, in conjunction with "herd7", to exhaustively
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explore the state space of small litmus tests.
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For example, to run SB+mbonceonces.litmus against the memory model:
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For example, to run SB+fencembonceonces.litmus against the memory model:
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$ herd7 -conf linux-kernel.cfg litmus-tests/SB+mbonceonces.litmus
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$ herd7 -conf linux-kernel.cfg litmus-tests/SB+fencembonceonces.litmus
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Here is the corresponding output:
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Test SB+mbonceonces Allowed
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Test SB+fencembonceonces Allowed
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States 3
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0:r0=0; 1:r0=1;
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0:r0=1; 1:r0=0;
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@ -50,8 +50,8 @@ Here is the corresponding output:
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Witnesses
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Positive: 0 Negative: 3
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Condition exists (0:r0=0 /\ 1:r0=0)
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Observation SB+mbonceonces Never 0 3
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Time SB+mbonceonces 0.01
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Observation SB+fencembonceonces Never 0 3
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Time SB+fencembonceonces 0.01
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Hash=d66d99523e2cac6b06e66f4c995ebb48
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The "Positive: 0 Negative: 3" and the "Never 0 3" each indicate that
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@ -67,16 +67,16 @@ BASIC USAGE: KLITMUS7
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The "klitmus7" tool converts a litmus test into a Linux kernel module,
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which may then be loaded and run.
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For example, to run SB+mbonceonces.litmus against hardware:
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For example, to run SB+fencembonceonces.litmus against hardware:
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$ mkdir mymodules
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$ klitmus7 -o mymodules litmus-tests/SB+mbonceonces.litmus
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$ klitmus7 -o mymodules litmus-tests/SB+fencembonceonces.litmus
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$ cd mymodules ; make
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$ sudo sh run.sh
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The corresponding output includes:
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Test SB+mbonceonces Allowed
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Test SB+fencembonceonces Allowed
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Histogram (3 states)
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644580 :>0:r0=1; 1:r0=0;
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644328 :>0:r0=0; 1:r0=1;
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@ -86,8 +86,8 @@ The corresponding output includes:
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Positive: 0, Negative: 2000000
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Condition exists (0:r0=0 /\ 1:r0=0) is NOT validated
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Hash=d66d99523e2cac6b06e66f4c995ebb48
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Observation SB+mbonceonces Never 0 2000000
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Time SB+mbonceonces 0.16
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Observation SB+fencembonceonces Never 0 2000000
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Time SB+fencembonceonces 0.16
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The "Positive: 0 Negative: 2000000" and the "Never 0 2000000" indicate
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that during two million trials, the state specified in this litmus
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@ -1,4 +1,4 @@
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C IRIW+mbonceonces+OnceOnce
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C IRIW+fencembonceonces+OnceOnce
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(*
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* Result: Never
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@ -1,4 +1,4 @@
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C LB+ctrlonceonce+mbonceonce
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C LB+fencembonceonce+ctrlonceonce
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(*
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* Result: Never
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@ -1,4 +1,4 @@
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C MP+wmbonceonce+rmbonceonce
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C MP+fencewmbonceonce+fencermbonceonce
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(*
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* Result: Never
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@ -1,4 +1,4 @@
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C R+mbonceonces
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C R+fencembonceonces
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(*
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* Result: Never
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@ -18,7 +18,7 @@ CoWW+poonceonce.litmus
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Test of write-write coherence, that is, whether or not two
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successive writes to the same variable are ordered.
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IRIW+mbonceonces+OnceOnce.litmus
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IRIW+fencembonceonces+OnceOnce.litmus
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Test of independent reads from independent writes with smp_mb()
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between each pairs of reads. In other words, is smp_mb()
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sufficient to cause two different reading processes to agree on
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@ -47,7 +47,7 @@ ISA2+pooncerelease+poacquirerelease+poacquireonce.litmus
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Can a release-acquire chain order a prior store against
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a later load?
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LB+ctrlonceonce+mbonceonce.litmus
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LB+fencembonceonce+ctrlonceonce.litmus
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Does a control dependency and an smp_mb() suffice for the
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load-buffering litmus test, where each process reads from one
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of two variables then writes to the other?
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@ -88,14 +88,14 @@ MP+porevlocks.litmus
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As below, but with the first access of the writer process
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and the second access of reader process protected by a lock.
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MP+wmbonceonce+rmbonceonce.litmus
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MP+fencewmbonceonce+fencermbonceonce.litmus
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Does a smp_wmb() (between the stores) and an smp_rmb() (between
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the loads) suffice for the message-passing litmus test, where one
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process writes data and then a flag, and the other process reads
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the flag and then the data. (This is similar to the ISA2 tests,
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but with two processes instead of three.)
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R+mbonceonces.litmus
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R+fencembonceonces.litmus
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This is the fully ordered (via smp_mb()) version of one of
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the classic counterintuitive litmus tests that illustrates the
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effects of store propagation delays.
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@ -103,7 +103,7 @@ R+mbonceonces.litmus
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R+poonceonces.litmus
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As above, but without the smp_mb() invocations.
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SB+mbonceonces.litmus
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SB+fencembonceonces.litmus
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This is the fully ordered (again, via smp_mb() version of store
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buffering, which forms the core of Dekker's mutual-exclusion
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algorithm.
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@ -123,12 +123,12 @@ SB+rfionceonce-poonceonces.litmus
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S+poonceonces.litmus
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As below, but without the smp_wmb() and acquire load.
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S+wmbonceonce+poacquireonce.litmus
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S+fencewmbonceonce+poacquireonce.litmus
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Can a smp_wmb(), instead of a release, and an acquire order
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a prior store against a subsequent store?
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WRC+poonceonces+Once.litmus
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WRC+pooncerelease+rmbonceonce+Once.litmus
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WRC+pooncerelease+fencermbonceonce+Once.litmus
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These two are members of an extension of the MP litmus-test
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class in which the first write is moved to a separate process.
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The second is forbidden because smp_store_release() is
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@ -143,7 +143,7 @@ Z6.0+pooncelock+poonceLock+pombonce.litmus
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As above, but with smp_mb__after_spinlock() immediately
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following the spin_lock().
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Z6.0+pooncerelease+poacquirerelease+mbonceonce.litmus
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Z6.0+pooncerelease+poacquirerelease+fencembonceonce.litmus
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Is the ordering provided by a release-acquire chain sufficient
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to make ordering apparent to accesses by a process that does
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not participate in that release-acquire chain?
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@ -1,4 +1,4 @@
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C S+wmbonceonce+poacquireonce
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C S+fencewmbonceonce+poacquireonce
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(*
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* Result: Never
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@ -1,4 +1,4 @@
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C SB+mbonceonces
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C SB+fencembonceonces
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(*
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* Result: Never
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@ -1,4 +1,4 @@
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C WRC+pooncerelease+rmbonceonce+Once
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C WRC+pooncerelease+fencermbonceonce+Once
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(*
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* Result: Never
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@ -1,4 +1,4 @@
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C Z6.0+pooncerelease+poacquirerelease+mbonceonce
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C Z6.0+pooncerelease+poacquirerelease+fencembonceonce
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(*
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* Result: Sometimes
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