drm/i915: Invalidate TLB caches on SNB BLT/BSD rings
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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2 changed files with 19 additions and 11 deletions
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@ -174,7 +174,9 @@
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* address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
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*/
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#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
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#define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */
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#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
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#define MI_INVALIDATE_TLB (1<<18)
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#define MI_INVALIDATE_BSD (1<<7)
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#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
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#define MI_BATCH_NON_SECURE (1)
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#define MI_BATCH_NON_SECURE_I965 (1<<8)
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@ -1059,22 +1059,25 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
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}
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static int gen6_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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u32 invalidate, u32 flush)
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{
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uint32_t cmd;
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int ret;
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0)
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return 0;
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ret = intel_ring_begin(ring, 4);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_FLUSH_DW);
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intel_ring_emit(ring, 0);
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cmd = MI_FLUSH_DW;
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if (invalidate & I915_GEM_GPU_DOMAINS)
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cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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return 0;
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}
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@ -1230,22 +1233,25 @@ static int blt_ring_begin(struct intel_ring_buffer *ring,
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}
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static int blt_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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u32 invalidate, u32 flush)
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{
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uint32_t cmd;
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int ret;
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0)
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return 0;
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ret = blt_ring_begin(ring, 4);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_FLUSH_DW);
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intel_ring_emit(ring, 0);
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cmd = MI_FLUSH_DW;
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if (invalidate & I915_GEM_DOMAIN_RENDER)
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cmd |= MI_INVALIDATE_TLB;
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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return 0;
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}
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