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perf vendor events arm64: Enable JSON events for eMAG

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This patch adds the Ampere Computing eMAG file.  This platform follows
the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable.

Signed-off-by: Sean V Kelley <seanvk.dev@oregontracks.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
LPU-Reference: 20180803041811.17065-1-seanvk.dev@oregontracks.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Sean V Kelley 2018-08-02 21:18:11 -07:00 committed by Arnaldo Carvalho de Melo
parent 33d9e1832e
commit 704089e77a
2 changed files with 33 additions and 0 deletions
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32
tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json Normal file
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@ -0,0 +1,32 @@
[
{
"ArchStdEvent": "L1D_CACHE_RD",
},
{
"ArchStdEvent": "L1D_CACHE_WR",
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD",
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR",
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD",
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
"ArchStdEvent": "L1D_TLB_RD",
},
{
"ArchStdEvent": "L1D_TLB_WR",
},
{
"ArchStdEvent": "BUS_ACCESS_RD",
},
{
"ArchStdEvent": "BUS_ACCESS_WR",
}
]

1
tools/perf/pmu-events/arch/arm64/mapfile.csv
View file

@ -16,3 +16,4 @@
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
0x00000000500f0000,v1,ampere/emag,core

1 # Format:
16 0x00000000420f5160,v1,cavium/thunderx2,core
17 0x00000000430f0af0,v1,cavium/thunderx2,core
18 0x00000000480fd010,v1,hisilicon/hip08,core
19 0x00000000500f0000,v1,ampere/emag,core