x86/mm: Use/Fix PCID to optimize user/kernel switches
We can use PCID to retain the TLBs across CR3 switches; including those now part of the user/kernel switch. This increases performance of kernel entry/exit at the cost of more expensive/complicated TLB flushing. Now that we have two address spaces, one for kernel and one for user space, we need two PCIDs per mm. We use the top PCID bit to indicate a user PCID (just like we use the PFN LSB for the PGD). Since we do TLB invalidation from kernel space, the existing code will only invalidate the kernel PCID, we augment that by marking the corresponding user PCID invalid, and upon switching back to userspace, use a flushing CR3 write for the switch. In order to access the user_pcid_flush_mask we use PER_CPU storage, which means the previously established SWAPGS vs CR3 ordering is now mandatory and required. Having to do this memory access does require additional registers, most sites have a functioning stack and we can spill one (RAX), sites without functional stack need to otherwise provide the second scratch register. Note: PCID is generally available on Intel Sandybridge and later CPUs. Note: Up until this point TLB flushing was broken in this series. Based-on-code-from: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: David Laight <David.Laight@aculab.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Eduardo Valentin <eduval@amazon.com> Cc: Greg KH <gregkh@linuxfoundation.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Juergen Gross <jgross@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will.deacon@arm.com> Cc: aliguori@amazon.com Cc: daniel.gruss@iaik.tugraz.at Cc: hughd@google.com Cc: keescook@google.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Peter Zijlstra
Ingo Molnar
parent
48e111982c
commit
6fd166aae7
9 changed files with 162 additions and 33 deletions
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@ -3,6 +3,9 @@
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#include <asm/unwind_hints.h>
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#include <asm/cpufeatures.h>
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#include <asm/page_types.h>
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#include <asm/percpu.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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/*
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@ -191,17 +194,21 @@ For 32-bit we have the following conventions - kernel is built with
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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/* PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two halves: */
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#define PTI_SWITCH_MASK (1<<PAGE_SHIFT)
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/*
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* PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
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* halves:
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*/
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#define PTI_SWITCH_PGTABLES_MASK (1<<PAGE_SHIFT)
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#define PTI_SWITCH_MASK (PTI_SWITCH_PGTABLES_MASK|(1<<X86_CR3_PTI_SWITCH_BIT))
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.macro ADJUST_KERNEL_CR3 reg:req
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/* Clear "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
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andq $(~PTI_SWITCH_MASK), \reg
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.macro SET_NOFLUSH_BIT reg:req
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bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
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.endm
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.macro ADJUST_USER_CR3 reg:req
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/* Move CR3 up a page to the user page tables: */
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orq $(PTI_SWITCH_MASK), \reg
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.macro ADJUST_KERNEL_CR3 reg:req
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ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
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/* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
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andq $(~PTI_SWITCH_MASK), \reg
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.endm
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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@ -212,21 +219,58 @@ For 32-bit we have the following conventions - kernel is built with
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.Lend_\@:
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.endm
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.macro SWITCH_TO_USER_CR3 scratch_reg:req
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#define THIS_CPU_user_pcid_flush_mask \
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PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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mov %cr3, \scratch_reg
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ADJUST_USER_CR3 \scratch_reg
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* Test if the ASID needs a flush.
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*/
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movq \scratch_reg, \scratch_reg2
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andq $(0x7FF), \scratch_reg /* mask ASID */
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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/* Flush needed, clear the bit */
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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movq \scratch_reg2, \scratch_reg
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jmp .Lwrcr3_\@
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.Lnoflush_\@:
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movq \scratch_reg2, \scratch_reg
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SET_NOFLUSH_BIT \scratch_reg
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.Lwrcr3_\@:
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/* Flip the PGD and ASID to the user version */
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orq $(PTI_SWITCH_MASK), \scratch_reg
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mov \scratch_reg, %cr3
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.Lend_\@:
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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pushq %rax
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SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
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popq %rax
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
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movq %cr3, \scratch_reg
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movq \scratch_reg, \save_reg
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/*
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* Is the switch bit zero? This means the address is
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* up in real PAGE_TABLE_ISOLATION patches in a moment.
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* Is the "switch mask" all zero? That means that both of
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* these are zero:
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*
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* 1. The user/kernel PCID bit, and
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* 2. The user/kernel "bit" that points CR3 to the
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* bottom half of the 8k PGD
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*
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* That indicates a kernel CR3 value, not a user CR3.
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*/
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testq $(PTI_SWITCH_MASK), \scratch_reg
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jz .Ldone_\@
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@ -251,7 +295,9 @@ For 32-bit we have the following conventions - kernel is built with
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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.endm
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.macro SWITCH_TO_USER_CR3 scratch_reg:req
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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.endm
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.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
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.endm
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.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
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.endm
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@ -23,7 +23,6 @@
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#include <asm/segment.h>
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#include <asm/cache.h>
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#include <asm/errno.h>
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#include "calling.h"
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#include <asm/asm-offsets.h>
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#include <asm/msr.h>
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#include <asm/unistd.h>
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@ -40,6 +39,8 @@
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#include <asm/frame.h>
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#include <linux/err.h>
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#include "calling.h"
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.code64
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.section .entry.text, "ax"
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@ -406,7 +407,7 @@ syscall_return_via_sysret:
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* We are on the trampoline stack. All regs except RDI are live.
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* We can do future final exit work right here.
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*/
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SWITCH_TO_USER_CR3 scratch_reg=%rdi
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SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
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popq %rdi
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popq %rsp
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@ -744,7 +745,7 @@ GLOBAL(swapgs_restore_regs_and_return_to_usermode)
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* We can do future final exit work right here.
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*/
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SWITCH_TO_USER_CR3 scratch_reg=%rdi
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SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
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/* Restore RDI. */
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popq %rdi
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@ -857,7 +858,7 @@ native_irq_return_ldt:
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*/
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orq PER_CPU_VAR(espfix_stack), %rax
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SWITCH_TO_USER_CR3 scratch_reg=%rdi /* to user CR3 */
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SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
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SWAPGS /* to user GS */
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popq %rdi /* Restore user RDI */
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@ -275,9 +275,9 @@ sysret32_from_system_call:
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* switch until after after the last reference to the process
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* stack.
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*
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* %r8 is zeroed before the sysret, thus safe to clobber.
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* %r8/%r9 are zeroed before the sysret, thus safe to clobber.
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*/
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SWITCH_TO_USER_CR3 scratch_reg=%r8
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SWITCH_TO_USER_CR3_NOSTACK scratch_reg=%r8 scratch_reg2=%r9
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xorq %r8, %r8
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xorq %r9, %r9
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@ -38,6 +38,11 @@
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#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
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#define CR3_PCID_MASK 0xFFFull
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#define CR3_NOFLUSH BIT_ULL(63)
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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# define X86_CR3_PTI_SWITCH_BIT 11
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#endif
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#else
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/*
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* CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
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@ -10,6 +10,8 @@
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#include <asm/special_insns.h>
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#include <asm/smp.h>
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#include <asm/invpcid.h>
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#include <asm/pti.h>
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#include <asm/processor-flags.h>
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static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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{
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@ -24,24 +26,54 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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/* There are 12 bits of space for ASIDS in CR3 */
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#define CR3_HW_ASID_BITS 12
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/*
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* When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
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* user/kernel switches
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*/
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#define PTI_CONSUMED_ASID_BITS 0
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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# define PTI_CONSUMED_PCID_BITS 1
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#else
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# define PTI_CONSUMED_PCID_BITS 0
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#endif
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#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
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#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS - PTI_CONSUMED_ASID_BITS)
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/*
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* ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
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* for them being zero-based. Another -1 is because ASID 0 is reserved for
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* use by non-PCID-aware users.
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*/
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#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_ASID_BITS) - 2)
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#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
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/*
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* 6 because 6 should be plenty and struct tlb_state will fit in two cache
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* lines.
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*/
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#define TLB_NR_DYN_ASIDS 6
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static inline u16 kern_pcid(u16 asid)
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{
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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/*
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* Make sure that the dynamic ASID space does not confict with the
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* bit we are using to switch between user and kernel ASIDs.
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*/
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BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_SWITCH_BIT));
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/*
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* The ASID being passed in here should have respected the
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* MAX_ASID_AVAILABLE and thus never have the switch bit set.
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*/
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VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_SWITCH_BIT));
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#endif
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/*
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* The dynamically-assigned ASIDs that get passed in are small
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* (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
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* so do not bother to clear it.
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*
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* If PCID is on, ASID-aware code paths put the ASID+1 into the
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* PCID bits. This serves two purposes. It prevents a nasty
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* situation in which PCID-unaware code saves CR3, loads some other
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@ -95,12 +127,6 @@ static inline bool tlb_defer_switch_to_init_mm(void)
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return !static_cpu_has(X86_FEATURE_PCID);
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}
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/*
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* 6 because 6 should be plenty and struct tlb_state will fit in
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* two cache lines.
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*/
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#define TLB_NR_DYN_ASIDS 6
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struct tlb_context {
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u64 ctx_id;
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u64 tlb_gen;
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@ -145,6 +171,13 @@ struct tlb_state {
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*/
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bool invalidate_other;
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/*
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* Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
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* the corresponding user PCID needs a flush next time we
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* switch to it; see SWITCH_TO_USER_CR3.
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*/
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unsigned short user_pcid_flush_mask;
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/*
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* Access to this CR4 shadow and to H/W CR4 is protected by
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* disabling interrupts when modifying either one.
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@ -249,15 +282,42 @@ static inline void cr4_set_bits_and_update_boot(unsigned long mask)
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extern void initialize_tlbstate_and_flush(void);
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/*
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* Given an ASID, flush the corresponding user ASID. We can delay this
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* until the next time we switch to it.
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*
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* See SWITCH_TO_USER_CR3.
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*/
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static inline void invalidate_user_asid(u16 asid)
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{
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/* There is no user ASID if address space separation is off */
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if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
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return;
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/*
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* We only have a single ASID if PCID is off and the CR3
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* write will have flushed it.
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*/
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if (!cpu_feature_enabled(X86_FEATURE_PCID))
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return;
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if (!static_cpu_has(X86_FEATURE_PTI))
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return;
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__set_bit(kern_pcid(asid),
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(unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
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}
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/*
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* flush the entire current user mapping
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*/
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static inline void __native_flush_tlb(void)
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{
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invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
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/*
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* If current->mm == NULL then we borrow a mm which may change during a
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* task switch and therefore we must not be preempted while we write CR3
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* back:
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* If current->mm == NULL then we borrow a mm which may change
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* during a task switch and therefore we must not be preempted
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* while we write CR3 back:
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*/
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preempt_disable();
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native_write_cr3(__native_read_cr3());
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@ -301,7 +361,14 @@ static inline void __native_flush_tlb_global(void)
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*/
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
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asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
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if (!static_cpu_has(X86_FEATURE_PTI))
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return;
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invalidate_user_asid(loaded_mm_asid);
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}
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/*
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@ -78,7 +78,12 @@
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#define X86_CR3_PWT _BITUL(X86_CR3_PWT_BIT)
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#define X86_CR3_PCD_BIT 4 /* Page Cache Disable */
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#define X86_CR3_PCD _BITUL(X86_CR3_PCD_BIT)
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#define X86_CR3_PCID_MASK _AC(0x00000fff,UL) /* PCID Mask */
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#define X86_CR3_PCID_BITS 12
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#define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL))
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#define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */
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#define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT)
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/*
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* Intel CPU features in CR4
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@ -17,6 +17,7 @@
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#include <asm/sigframe.h>
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#include <asm/bootparam.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_XEN
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#include <xen/interface/xen.h>
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@ -94,6 +95,9 @@ void common(void) {
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BLANK();
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DEFINE(PTREGS_SIZE, sizeof(struct pt_regs));
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/* TLB state for the entry code */
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OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state, user_pcid_flush_mask);
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/* Layout info for cpu_entry_area */
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OFFSET(CPU_ENTRY_AREA_tss, cpu_entry_area, tss);
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OFFSET(CPU_ENTRY_AREA_entry_trampoline, cpu_entry_area, entry_trampoline);
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@ -855,7 +855,7 @@ void __init zone_sizes_init(void)
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free_area_init_nodes(max_zone_pfns);
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}
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DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = {
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__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = {
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.loaded_mm = &init_mm,
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.next_asid = 1,
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.cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
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@ -105,6 +105,7 @@ static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
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unsigned long new_mm_cr3;
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if (need_flush) {
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invalidate_user_asid(new_asid);
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new_mm_cr3 = build_cr3(pgdir, new_asid);
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} else {
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new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
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||||
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Reference in a new issue