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MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLB

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For MIPS32R3 supported cores, the EHINV bit needs to be set when
invalidating the TLB. This is necessary because the legacy software
method of representing an invalid TLB entry using an unmapped address
value is not guaranteed to work.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6132/
This commit is contained in:
Leonid Yegoshin 2013-11-14 16:12:25 +00:00 committed by Ralf Baechle
parent 4a0156fbfb
commit 6e7f8b8e47
1 changed files with 3 additions and 1 deletions
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4
arch/mips/include/asm/tlb.h
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@ -18,7 +18,9 @@
*/
#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
#define UNIQUE_ENTRYHI(idx) \
((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \
(cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
#include <asm-generic/tlb.h>