Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: ERROR: "sys_ioctl" [arch/sparc64/solaris/solaris.ko] undefined! [SPARC32]: Make PAGE_SHARED a read-mostly variable. [SPARC32]: Take enable_irq/disable_irq out of line. [SPARC32]: clean include/asm-sparc/irq.h [SPARC32]: Fix rounding errors in ndelay/udelay implementation.
This commit is contained in:
Linus Torvalds
commit
6df8cd3d4f
19 changed files with 217 additions and 182 deletions
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@ -1749,8 +1749,8 @@ fpload:
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__ndelay:
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save %sp, -STACKFRAME_SZ, %sp
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mov %i0, %o0
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call .umul
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mov 0x1ad, %o1 ! 2**32 / (1 000 000 000 / HZ)
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call .umul ! round multiplier up so large ns ok
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mov 0x1ae, %o1 ! 2**32 / (1 000 000 000 / HZ)
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call .umul
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mov %i1, %o1 ! udelay_val
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ba delay_continue
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@ -1760,11 +1760,17 @@ __ndelay:
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__udelay:
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save %sp, -STACKFRAME_SZ, %sp
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mov %i0, %o0
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sethi %hi(0x10c6), %o1
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sethi %hi(0x10c7), %o1 ! round multiplier up so large us ok
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call .umul
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or %o1, %lo(0x10c6), %o1 ! 2**32 / 1 000 000
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or %o1, %lo(0x10c7), %o1 ! 2**32 / 1 000 000
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call .umul
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mov %i1, %o1 ! udelay_val
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sethi %hi(0x028f4b62), %l0 ! Add in rounding constant * 2**32,
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or %g0, %lo(0x028f4b62), %l0
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addcc %o0, %l0, %o0 ! 2**32 * 0.009 999
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bcs,a 3f
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add %o1, 0x01, %o1
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3:
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call .umul
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mov HZ, %o0 ! >>32 earlier for wider range
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@ -47,6 +47,8 @@
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#include <asm/cacheflush.h>
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#include <asm/irq_regs.h>
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#include "irq.h"
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#ifdef CONFIG_SMP
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#define SMP_NOP2 "nop; nop;\n\t"
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#define SMP_NOP3 "nop; nop; nop;\n\t"
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@ -268,7 +270,7 @@ void free_irq(unsigned int irq, void *dev_id)
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kfree(action);
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if (!sparc_irq[cpu_irq].action)
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disable_irq(irq);
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__disable_irq(irq);
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out_unlock:
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spin_unlock_irqrestore(&irq_action_lock, flags);
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@ -464,7 +466,7 @@ int request_fast_irq(unsigned int irq,
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sparc_irq[cpu_irq].action = action;
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enable_irq(irq);
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__enable_irq(irq);
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ret = 0;
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out_unlock:
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@ -544,7 +546,7 @@ int request_irq(unsigned int irq,
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*actionp = action;
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enable_irq(irq);
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__enable_irq(irq);
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ret = 0;
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out_unlock:
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@ -555,6 +557,25 @@ int request_irq(unsigned int irq,
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EXPORT_SYMBOL(request_irq);
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void disable_irq_nosync(unsigned int irq)
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{
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return __disable_irq(irq);
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}
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EXPORT_SYMBOL(disable_irq_nosync);
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void disable_irq(unsigned int irq)
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{
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return __disable_irq(irq);
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}
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EXPORT_SYMBOL(disable_irq);
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void enable_irq(unsigned int irq)
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{
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return __enable_irq(irq);
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}
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EXPORT_SYMBOL(enable_irq);
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/* We really don't need these at all on the Sparc. We only have
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* stubs here because they are exported to modules.
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*/
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68
arch/sparc/kernel/irq.h
Normal file
68
arch/sparc/kernel/irq.h
Normal file
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@ -0,0 +1,68 @@
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#include <asm/btfixup.h>
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/* Dave Redman (djhr@tadpole.co.uk)
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* changed these to function pointers.. it saves cycles and will allow
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* the irq dependencies to be split into different files at a later date
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* sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
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* Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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* Changed these to btfixup entities... It saves cycles :)
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*/
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BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
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BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
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BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, clear_clock_irq, void)
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BTFIXUPDEF_CALL(void, clear_profile_irq, int)
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BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
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static inline void __disable_irq(unsigned int irq)
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{
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BTFIXUP_CALL(disable_irq)(irq);
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}
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static inline void __enable_irq(unsigned int irq)
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{
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BTFIXUP_CALL(enable_irq)(irq);
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}
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static inline void disable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(disable_pil_irq)(irq);
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}
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static inline void enable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(enable_pil_irq)(irq);
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}
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static inline void clear_clock_irq(void)
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{
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BTFIXUP_CALL(clear_clock_irq)();
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}
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static inline void clear_profile_irq(int irq)
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{
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BTFIXUP_CALL(clear_profile_irq)(irq);
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}
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static inline void load_profile_irq(int cpu, int limit)
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{
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BTFIXUP_CALL(load_profile_irq)(cpu, limit);
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}
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extern void (*sparc_init_timers)(irq_handler_t lvl10_irq);
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extern void claim_ticker14(irq_handler_t irq_handler,
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int irq,
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unsigned int timeout);
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#ifdef CONFIG_SMP
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BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, set_irq_udt, int)
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#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
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#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
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#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
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#endif
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@ -36,6 +36,7 @@
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#include <asm/uaccess.h>
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#include <asm/irq_regs.h>
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#include "irq.h"
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/*
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* I studied different documents and many live PROMs both from 2.30
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@ -33,6 +33,8 @@
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#include <asm/tlbflush.h>
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#include <asm/cpudata.h>
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#include "irq.h"
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int smp_num_cpus = 1;
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volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};
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unsigned char boot_cpu_id = 0;
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@ -154,8 +154,6 @@ EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32));
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#else
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EXPORT_SYMBOL(BTFIXUP_CALL(__hard_smp_processor_id));
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#endif
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EXPORT_SYMBOL(BTFIXUP_CALL(enable_irq));
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EXPORT_SYMBOL(BTFIXUP_CALL(disable_irq));
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EXPORT_SYMBOL(BTFIXUP_CALL(mmu_unlockarea));
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EXPORT_SYMBOL(BTFIXUP_CALL(mmu_lockarea));
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EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_sgl));
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@ -18,6 +18,7 @@
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include "irq.h"
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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@ -40,6 +41,20 @@ static struct resource sun4c_timer_eb = { "sun4c_timer" };
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static struct resource sun4c_intr_eb = { "sun4c_intr" };
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#endif
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/*
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* Bit field defines for the interrupt registers on various
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* Sparc machines.
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*/
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/* The sun4c interrupt register. */
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#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
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#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
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#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
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#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
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#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
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#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
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#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
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/* Pointer to the interrupt enable byte
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*
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* Dave Redman (djhr@tadpole.co.uk)
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@ -39,6 +39,8 @@
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#include <asm/cacheflush.h>
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#include <asm/irq_regs.h>
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#include "irq.h"
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/* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */
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/* #define DISTRIBUTE_IRQS */
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@ -188,7 +190,7 @@ void sun4d_free_irq(unsigned int irq, void *dev_id)
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kfree(action);
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if (!(*actionp))
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disable_irq(irq);
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__disable_irq(irq);
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out_unlock:
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spin_unlock_irqrestore(&irq_action_lock, flags);
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@ -346,7 +348,7 @@ int sun4d_request_irq(unsigned int irq,
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else
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*actionp = action;
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enable_irq(irq);
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__enable_irq(irq);
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ret = 0;
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out_unlock:
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@ -36,6 +36,7 @@
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#include <asm/cacheflush.h>
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#include <asm/cpudata.h>
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#include "irq.h"
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#define IRQ_CROSS_CALL 15
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extern ctxd_t *srmmu_ctx_table_phys;
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@ -38,11 +38,85 @@
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#include <asm/sbus.h>
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#include <asm/cacheflush.h>
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#include "irq.h"
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/* On the sun4m, just like the timers, we have both per-cpu and master
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* interrupt registers.
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*/
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/* These registers are used for sending/receiving irqs from/to
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* different cpu's.
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*/
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struct sun4m_intreg_percpu {
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unsigned int tbt; /* Interrupts still pending for this cpu. */
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/* These next two registers are WRITE-ONLY and are only
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* "on bit" sensitive, "off bits" written have NO affect.
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*/
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unsigned int clear; /* Clear this cpus irqs here. */
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unsigned int set; /* Set this cpus irqs here. */
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unsigned char space[PAGE_SIZE - 12];
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};
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/*
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* djhr
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* Actually the clear and set fields in this struct are misleading..
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* according to the SLAVIO manual (and the same applies for the SEC)
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* the clear field clears bits in the mask which will ENABLE that IRQ
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* the set field sets bits in the mask to DISABLE the IRQ.
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*
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* Also the undirected_xx address in the SLAVIO is defined as
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* RESERVED and write only..
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*
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* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
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* sun4m machines, for MP the layout makes more sense.
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*/
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struct sun4m_intregs {
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struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
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unsigned int tbt; /* IRQ's that are still pending. */
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unsigned int irqs; /* Master IRQ bits. */
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/* Again, like the above, two these registers are WRITE-ONLY. */
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unsigned int clear; /* Clear master IRQ's by setting bits here. */
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unsigned int set; /* Set master IRQ's by setting bits here. */
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/* This register is both READ and WRITE. */
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unsigned int undirected_target; /* Which cpu gets undirected irqs. */
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};
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static unsigned long dummy;
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struct sun4m_intregs *sun4m_interrupts;
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unsigned long *irq_rcvreg = &dummy;
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/* Dave Redman (djhr@tadpole.co.uk)
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* The sun4m interrupt registers.
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*/
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#define SUN4M_INT_ENABLE 0x80000000
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#define SUN4M_INT_E14 0x00000080
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#define SUN4M_INT_E10 0x00080000
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#define SUN4M_HARD_INT(x) (0x000000001 << (x))
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#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
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#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
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#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
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#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
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#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
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#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
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#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
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#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
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#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
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#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
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#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
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#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
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#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
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#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
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#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
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#define SUN4M_INT_SBUS(x) (1 << (x+7))
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#define SUN4M_INT_VME(x) (1 << (x))
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/* These tables only apply for interrupts greater than 15..
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*
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* any intr value below 0x10 is considered to be a soft-int
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|
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@ -31,6 +31,8 @@
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#include <asm/oplib.h>
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#include <asm/cpudata.h>
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#include "irq.h"
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#define IRQ_RESCHEDULE 13
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#define IRQ_STOP_CPU 14
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#define IRQ_CROSS_CALL 15
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|
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@ -25,6 +25,8 @@
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#include <asm/irq.h>
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#include <asm/io.h>
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#include "irq.h"
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|
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extern unsigned long lvl14_save[5];
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static unsigned long *linux_lvl14 = NULL;
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static unsigned long obp_lvl14[4];
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|
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@ -62,7 +64,7 @@ void claim_ticker14(irq_handler_t handler,
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/* first we copy the obp handler instructions
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*/
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disable_irq(irq_nr);
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__disable_irq(irq_nr);
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if (!handler)
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return;
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|
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@ -79,6 +81,6 @@ void claim_ticker14(irq_handler_t handler,
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NULL)) {
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install_linux_ticker();
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load_profile_irq(cpu, timeout);
|
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enable_irq(irq_nr);
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__enable_irq(irq_nr);
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}
|
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}
|
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|
|
|
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|
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@ -44,6 +44,8 @@
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#include <asm/of_device.h>
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#include <asm/irq_regs.h>
|
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|
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#include "irq.h"
|
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|
||||
DEFINE_SPINLOCK(rtc_lock);
|
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enum sparc_clock_type sp_clock_typ;
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DEFINE_SPINLOCK(mostek_lock);
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|
|
|
|||
|
|
@ -308,6 +308,9 @@ extern void sun4c_paging_init(void);
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extern void srmmu_paging_init(void);
|
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extern void device_scan(void);
|
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|
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pgprot_t PAGE_SHARED __read_mostly;
|
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EXPORT_SYMBOL(PAGE_SHARED);
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|
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void __init paging_init(void)
|
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{
|
||||
switch(sparc_cpu_model) {
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||||
|
|
|
|||
|
|
@ -2154,7 +2154,7 @@ void __init ld_mmu_srmmu(void)
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BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
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|
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BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
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BTFIXUPSET_INT(page_shared, pgprot_val(SRMMU_PAGE_SHARED));
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PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
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BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
|
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BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
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BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
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|
|
|
|||
|
|
@ -2155,7 +2155,7 @@ void __init ld_mmu_sun4c(void)
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BTFIXUPSET_SIMM13(user_ptrs_per_pgd, KERNBASE / SUN4C_PGDIR_SIZE);
|
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|
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BTFIXUPSET_INT(page_none, pgprot_val(SUN4C_PAGE_NONE));
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BTFIXUPSET_INT(page_shared, pgprot_val(SUN4C_PAGE_SHARED));
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PAGE_SHARED = pgprot_val(SUN4C_PAGE_SHARED);
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BTFIXUPSET_INT(page_copy, pgprot_val(SUN4C_PAGE_COPY));
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BTFIXUPSET_INT(page_readonly, pgprot_val(SUN4C_PAGE_READONLY));
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BTFIXUPSET_INT(page_kernel, pgprot_val(SUN4C_PAGE_KERNEL));
|
||||
|
|
|
|||
|
|
@ -280,6 +280,7 @@ EXPORT_SYMBOL(sys_getgid);
|
|||
EXPORT_SYMBOL(svr4_getcontext);
|
||||
EXPORT_SYMBOL(svr4_setcontext);
|
||||
EXPORT_SYMBOL(compat_sys_ioctl);
|
||||
EXPORT_SYMBOL(sys_ioctl);
|
||||
EXPORT_SYMBOL(sparc32_open);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -7,178 +7,16 @@
|
|||
#ifndef _SPARC_IRQ_H
|
||||
#define _SPARC_IRQ_H
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/threads.h> /* For NR_CPUS */
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/system.h> /* For SUN4M_NCPUS */
|
||||
#include <asm/btfixup.h>
|
||||
|
||||
#define __irq_ino(irq) irq
|
||||
#define __irq_pil(irq) irq
|
||||
|
||||
#define NR_IRQS 16
|
||||
|
||||
#define irq_canonicalize(irq) (irq)
|
||||
|
||||
/* Dave Redman (djhr@tadpole.co.uk)
|
||||
* changed these to function pointers.. it saves cycles and will allow
|
||||
* the irq dependencies to be split into different files at a later date
|
||||
* sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
|
||||
* Jakub Jelinek (jj@sunsite.mff.cuni.cz)
|
||||
* Changed these to btfixup entities... It saves cycles :)
|
||||
*/
|
||||
BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
|
||||
BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
|
||||
BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
|
||||
BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
|
||||
BTFIXUPDEF_CALL(void, clear_clock_irq, void)
|
||||
BTFIXUPDEF_CALL(void, clear_profile_irq, int)
|
||||
BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
|
||||
|
||||
static inline void disable_irq_nosync(unsigned int irq)
|
||||
{
|
||||
BTFIXUP_CALL(disable_irq)(irq);
|
||||
}
|
||||
|
||||
static inline void disable_irq(unsigned int irq)
|
||||
{
|
||||
BTFIXUP_CALL(disable_irq)(irq);
|
||||
}
|
||||
|
||||
static inline void enable_irq(unsigned int irq)
|
||||
{
|
||||
BTFIXUP_CALL(enable_irq)(irq);
|
||||
}
|
||||
|
||||
static inline void disable_pil_irq(unsigned int irq)
|
||||
{
|
||||
BTFIXUP_CALL(disable_pil_irq)(irq);
|
||||
}
|
||||
|
||||
static inline void enable_pil_irq(unsigned int irq)
|
||||
{
|
||||
BTFIXUP_CALL(enable_pil_irq)(irq);
|
||||
}
|
||||
|
||||
static inline void clear_clock_irq(void)
|
||||
{
|
||||
BTFIXUP_CALL(clear_clock_irq)();
|
||||
}
|
||||
|
||||
static inline void clear_profile_irq(int irq)
|
||||
{
|
||||
BTFIXUP_CALL(clear_profile_irq)(irq);
|
||||
}
|
||||
|
||||
static inline void load_profile_irq(int cpu, int limit)
|
||||
{
|
||||
BTFIXUP_CALL(load_profile_irq)(cpu, limit);
|
||||
}
|
||||
|
||||
extern void (*sparc_init_timers)(irq_handler_t lvl10_irq);
|
||||
extern void claim_ticker14(irq_handler_t irq_handler,
|
||||
int irq,
|
||||
unsigned int timeout);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
|
||||
BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
|
||||
BTFIXUPDEF_CALL(void, set_irq_udt, int)
|
||||
|
||||
#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
|
||||
#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
|
||||
#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
|
||||
#endif
|
||||
extern void disable_irq_nosync(unsigned int irq);
|
||||
extern void disable_irq(unsigned int irq);
|
||||
extern void enable_irq(unsigned int irq);
|
||||
|
||||
extern int request_fast_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, __const__ char *devname);
|
||||
|
||||
/* On the sun4m, just like the timers, we have both per-cpu and master
|
||||
* interrupt registers.
|
||||
*/
|
||||
|
||||
/* These registers are used for sending/receiving irqs from/to
|
||||
* different cpu's.
|
||||
*/
|
||||
struct sun4m_intreg_percpu {
|
||||
unsigned int tbt; /* Interrupts still pending for this cpu. */
|
||||
|
||||
/* These next two registers are WRITE-ONLY and are only
|
||||
* "on bit" sensitive, "off bits" written have NO affect.
|
||||
*/
|
||||
unsigned int clear; /* Clear this cpus irqs here. */
|
||||
unsigned int set; /* Set this cpus irqs here. */
|
||||
unsigned char space[PAGE_SIZE - 12];
|
||||
};
|
||||
|
||||
/*
|
||||
* djhr
|
||||
* Actually the clear and set fields in this struct are misleading..
|
||||
* according to the SLAVIO manual (and the same applies for the SEC)
|
||||
* the clear field clears bits in the mask which will ENABLE that IRQ
|
||||
* the set field sets bits in the mask to DISABLE the IRQ.
|
||||
*
|
||||
* Also the undirected_xx address in the SLAVIO is defined as
|
||||
* RESERVED and write only..
|
||||
*
|
||||
* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
|
||||
* sun4m machines, for MP the layout makes more sense.
|
||||
*/
|
||||
struct sun4m_intregs {
|
||||
struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
|
||||
unsigned int tbt; /* IRQ's that are still pending. */
|
||||
unsigned int irqs; /* Master IRQ bits. */
|
||||
|
||||
/* Again, like the above, two these registers are WRITE-ONLY. */
|
||||
unsigned int clear; /* Clear master IRQ's by setting bits here. */
|
||||
unsigned int set; /* Set master IRQ's by setting bits here. */
|
||||
|
||||
/* This register is both READ and WRITE. */
|
||||
unsigned int undirected_target; /* Which cpu gets undirected irqs. */
|
||||
};
|
||||
|
||||
extern struct sun4m_intregs *sun4m_interrupts;
|
||||
|
||||
/*
|
||||
* Bit field defines for the interrupt registers on various
|
||||
* Sparc machines.
|
||||
*/
|
||||
|
||||
/* The sun4c interrupt register. */
|
||||
#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
|
||||
#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
|
||||
#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
|
||||
#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
|
||||
#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
|
||||
#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
|
||||
#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
|
||||
|
||||
/* Dave Redman (djhr@tadpole.co.uk)
|
||||
* The sun4m interrupt registers.
|
||||
*/
|
||||
#define SUN4M_INT_ENABLE 0x80000000
|
||||
#define SUN4M_INT_E14 0x00000080
|
||||
#define SUN4M_INT_E10 0x00080000
|
||||
|
||||
#define SUN4M_HARD_INT(x) (0x000000001 << (x))
|
||||
#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
|
||||
|
||||
#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
|
||||
#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
|
||||
#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
|
||||
#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
|
||||
#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
|
||||
#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
|
||||
#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
|
||||
#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
|
||||
#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
|
||||
#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
|
||||
#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
|
||||
#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
|
||||
#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
|
||||
#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
|
||||
|
||||
#define SUN4M_INT_SBUS(x) (1 << (x+7))
|
||||
#define SUN4M_INT_VME(x) (1 << (x))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -46,7 +46,6 @@ BTFIXUPDEF_SIMM13(user_ptrs_per_pgd)
|
|||
#define pgd_ERROR(e) __builtin_trap()
|
||||
|
||||
BTFIXUPDEF_INT(page_none)
|
||||
BTFIXUPDEF_INT(page_shared)
|
||||
BTFIXUPDEF_INT(page_copy)
|
||||
BTFIXUPDEF_INT(page_readonly)
|
||||
BTFIXUPDEF_INT(page_kernel)
|
||||
|
|
@ -66,7 +65,7 @@ BTFIXUPDEF_INT(page_kernel)
|
|||
#define PTE_SIZE (PTRS_PER_PTE*4)
|
||||
|
||||
#define PAGE_NONE __pgprot(BTFIXUP_INT(page_none))
|
||||
#define PAGE_SHARED __pgprot(BTFIXUP_INT(page_shared))
|
||||
extern pgprot_t PAGE_SHARED;
|
||||
#define PAGE_COPY __pgprot(BTFIXUP_INT(page_copy))
|
||||
#define PAGE_READONLY __pgprot(BTFIXUP_INT(page_readonly))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue