ARM: footbridge: add sched_clock implementation
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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3 changed files with 20 additions and 0 deletions
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@ -10,3 +10,5 @@ extern void footbridge_init_irq(void);
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extern void isa_init_irq(unsigned int irq);
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extern void isa_init_irq(unsigned int irq);
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extern void footbridge_restart(enum reboot_mode, const char *);
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extern void footbridge_restart(enum reboot_mode, const char *);
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extern void footbridge_sched_clock(void);
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@ -9,6 +9,7 @@
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irq.h>
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#include <linux/sched_clock.h>
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#include <asm/irq.h>
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#include <asm/irq.h>
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@ -104,3 +105,19 @@ void __init footbridge_timer_init(void)
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ce->cpumask = cpumask_of(smp_processor_id());
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ce->cpumask = cpumask_of(smp_processor_id());
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clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
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clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
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}
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}
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static u32 notrace footbridge_read_sched_clock(void)
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{
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return ~*CSR_TIMER3_VALUE;
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}
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void __init footbridge_sched_clock(void)
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{
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unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
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*CSR_TIMER3_LOAD = 0;
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*CSR_TIMER3_CLR = 0;
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*CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
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setup_sched_clock(footbridge_read_sched_clock, 24, rate);
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}
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@ -104,6 +104,7 @@ MACHINE_START(EBSA285, "EBSA285")
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.video_start = 0x000a0000,
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.video_start = 0x000a0000,
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.video_end = 0x000bffff,
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.video_end = 0x000bffff,
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.map_io = footbridge_map_io,
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.map_io = footbridge_map_io,
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.init_early = footbridge_sched_clock,
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.init_irq = footbridge_init_irq,
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.init_irq = footbridge_init_irq,
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.init_time = footbridge_timer_init,
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.init_time = footbridge_timer_init,
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.restart = footbridge_restart,
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.restart = footbridge_restart,
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