i2c: add Renesas R-Car I2C driver
R-Car I2C is similar with SH7760 I2C. But the SH7760 I2C driver had many workaround operations, since H/W had bugs. Thus, it was pointless to keep compatible between SH7760 and R-Car I2C drivers. This patch creates new Renesas R-Car I2C driver. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This commit is contained in:
Kuninori Morimoto
Wolfram Sang
parent
d3b64c5934
commit
6ccbe60713
4 changed files with 730 additions and 0 deletions
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@ -712,6 +712,16 @@ config I2C_XLR
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This driver can also be built as a module. If so, the module
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will be called i2c-xlr.
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config I2C_RCAR
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tristate "Renesas R-Car I2C Controller"
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depends on ARCH_SHMOBILE && I2C
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help
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If you say yes to this option, support will be included for the
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R-Car I2C controller.
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This driver can also be built as a module. If so, the module
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will be called i2c-rcar.
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comment "External I2C/SMBus adapter drivers"
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config I2C_DIOLAN_U2C
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@ -70,6 +70,7 @@ obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
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obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
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obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
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obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
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obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
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# External I2C/SMBus adapter drivers
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obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
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709
drivers/i2c/busses/i2c-rcar.c
Normal file
709
drivers/i2c/busses/i2c-rcar.c
Normal file
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@ -0,0 +1,709 @@
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/*
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* drivers/i2c/busses/i2c-rcar.c
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This file is based on the drivers/i2c/busses/i2c-sh7760.c
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* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
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*
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* This file used out-of-tree driver i2c-rcar.c
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* Copyright (C) 2011-2012 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c/i2c-rcar.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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/* register offsets */
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#define ICSCR 0x00 /* slave ctrl */
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#define ICMCR 0x04 /* master ctrl */
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#define ICSSR 0x08 /* slave status */
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#define ICMSR 0x0C /* master status */
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#define ICSIER 0x10 /* slave irq enable */
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#define ICMIER 0x14 /* master irq enable */
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#define ICCCR 0x18 /* clock dividers */
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#define ICSAR 0x1C /* slave address */
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#define ICMAR 0x20 /* master address */
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#define ICRXTX 0x24 /* data port */
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/* ICMCR */
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#define MDBS (1 << 7) /* non-fifo mode switch */
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#define FSCL (1 << 6) /* override SCL pin */
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#define FSDA (1 << 5) /* override SDA pin */
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#define OBPC (1 << 4) /* override pins */
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#define MIE (1 << 3) /* master if enable */
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#define TSBE (1 << 2)
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#define FSB (1 << 1) /* force stop bit */
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#define ESG (1 << 0) /* en startbit gen */
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/* ICMSR */
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#define MNR (1 << 6) /* nack received */
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#define MAL (1 << 5) /* arbitration lost */
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#define MST (1 << 4) /* sent a stop */
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#define MDE (1 << 3)
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#define MDT (1 << 2)
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#define MDR (1 << 1)
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#define MAT (1 << 0) /* slave addr xfer done */
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/* ICMIE */
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#define MNRE (1 << 6) /* nack irq en */
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#define MALE (1 << 5) /* arblos irq en */
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#define MSTE (1 << 4) /* stop irq en */
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#define MDEE (1 << 3)
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#define MDTE (1 << 2)
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#define MDRE (1 << 1)
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#define MATE (1 << 0) /* address sent irq en */
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enum {
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RCAR_BUS_PHASE_ADDR,
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RCAR_BUS_PHASE_DATA,
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RCAR_BUS_PHASE_STOP,
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};
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enum {
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RCAR_IRQ_CLOSE,
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RCAR_IRQ_OPEN_FOR_SEND,
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RCAR_IRQ_OPEN_FOR_RECV,
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RCAR_IRQ_OPEN_FOR_STOP,
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};
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/*
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* flags
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*/
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#define ID_LAST_MSG (1 << 0)
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#define ID_IOERROR (1 << 1)
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#define ID_DONE (1 << 2)
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#define ID_ARBLOST (1 << 3)
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#define ID_NACK (1 << 4)
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struct rcar_i2c_priv {
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void __iomem *io;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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spinlock_t lock;
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wait_queue_head_t wait;
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int pos;
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int irq;
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u32 icccr;
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u32 flags;
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};
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#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
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#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
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#define rcar_i2c_flags_set(p, f) ((p)->flags |= (f))
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#define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
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#define LOOP_TIMEOUT 1024
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/*
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* basic functions
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*/
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static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
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{
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writel(val, priv->io + reg);
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}
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static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
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{
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return readl(priv->io + reg);
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}
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static void rcar_i2c_init(struct rcar_i2c_priv *priv)
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{
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/*
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* reset slave mode.
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* slave mode is not used on this driver
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*/
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rcar_i2c_write(priv, ICSIER, 0);
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rcar_i2c_write(priv, ICSAR, 0);
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rcar_i2c_write(priv, ICSCR, 0);
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rcar_i2c_write(priv, ICSSR, 0);
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/* reset master mode */
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rcar_i2c_write(priv, ICMIER, 0);
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rcar_i2c_write(priv, ICMCR, 0);
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rcar_i2c_write(priv, ICMSR, 0);
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rcar_i2c_write(priv, ICMAR, 0);
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}
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static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open)
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{
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u32 val = MNRE | MALE | MSTE | MATE; /* default */
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switch (open) {
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case RCAR_IRQ_OPEN_FOR_SEND:
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val |= MDEE; /* default + send */
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break;
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case RCAR_IRQ_OPEN_FOR_RECV:
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val |= MDRE; /* default + read */
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break;
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case RCAR_IRQ_OPEN_FOR_STOP:
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val = MSTE; /* stop irq only */
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break;
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case RCAR_IRQ_CLOSE:
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default:
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val = 0; /* all close */
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break;
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}
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rcar_i2c_write(priv, ICMIER, val);
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}
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static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv)
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{
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rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv);
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}
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/*
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* bus control functions
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*/
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static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
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{
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int i;
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for (i = 0; i < LOOP_TIMEOUT; i++) {
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/* make sure that bus is not busy */
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if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
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return 0;
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udelay(1);
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}
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return -EBUSY;
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}
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static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase)
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{
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switch (phase) {
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case RCAR_BUS_PHASE_ADDR:
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rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG);
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break;
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case RCAR_BUS_PHASE_DATA:
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rcar_i2c_write(priv, ICMCR, MDBS | MIE);
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break;
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case RCAR_BUS_PHASE_STOP:
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rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB);
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break;
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}
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}
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/*
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* clock function
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*/
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static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
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u32 bus_speed,
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struct device *dev)
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{
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struct clk *clkp = clk_get(NULL, "peripheral_clk");
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u32 scgd, cdf;
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u32 round, ick;
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u32 scl;
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if (!clkp) {
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dev_err(dev, "there is no peripheral_clk\n");
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return -EIO;
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}
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/*
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* calculate SCL clock
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* see
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* ICCCR
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*
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* ick = clkp / (1 + CDF)
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* ick : I2C internal clock < 20 MHz
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* ticf : I2C SCL falling time = 35 ns here
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* tr : I2C SCL rising time = 200 ns here
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* intd : LSI internal delay = 50 ns here
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* clkp : peripheral_clk
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* F[] : integer up-valuation
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*/
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for (cdf = 0; cdf < 4; cdf++) {
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ick = clk_get_rate(clkp) / (1 + cdf);
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if (ick < 20000000)
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goto ick_find;
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}
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dev_err(dev, "there is no best CDF\n");
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return -EIO;
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ick_find:
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/*
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* it is impossible to calculate large scale
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* number on u32. separate it
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*
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* F[(ticf + tr + intd) * ick]
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* = F[(35 + 200 + 50)ns * ick]
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* = F[285 * ick / 1000000000]
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* = F[(ick / 1000000) * 285 / 1000]
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*/
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round = (ick + 500000) / 1000000 * 285;
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round = (round + 500) / 1000;
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/*
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* Calculation result (= SCL) should be less than
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* bus_speed for hardware safety
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*/
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for (scgd = 0; scgd < 0x40; scgd++) {
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scl = ick / (20 + (scgd * 8) + round);
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if (scl <= bus_speed)
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goto scgd_find;
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}
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dev_err(dev, "it is impossible to calculate best SCL\n");
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return -EIO;
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scgd_find:
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dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
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scl, bus_speed, clk_get_rate(clkp), round, cdf, scgd);
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/*
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* keep icccr value
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*/
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priv->icccr = (scgd << 2 | cdf);
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return 0;
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}
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static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv)
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{
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rcar_i2c_write(priv, ICCCR, priv->icccr);
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}
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/*
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* status functions
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*/
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static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv)
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{
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return rcar_i2c_read(priv, ICMSR);
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}
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#define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff)
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static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit)
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{
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rcar_i2c_write(priv, ICMSR, ~bit);
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}
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/*
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* recv/send functions
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*/
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static int rcar_i2c_recv(struct rcar_i2c_priv *priv)
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{
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rcar_i2c_set_addr(priv, 1);
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rcar_i2c_status_clear(priv);
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rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
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rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV);
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return 0;
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}
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static int rcar_i2c_send(struct rcar_i2c_priv *priv)
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{
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int ret;
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/*
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* It should check bus status when send case
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*/
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ret = rcar_i2c_bus_barrier(priv);
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if (ret < 0)
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return ret;
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rcar_i2c_set_addr(priv, 0);
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rcar_i2c_status_clear(priv);
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rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR);
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rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND);
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return 0;
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}
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#define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE))
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#define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR))
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/*
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* interrupt functions
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*/
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static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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/*
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* FIXME
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* sometimes, unknown interrupt happened.
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* Do nothing
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*/
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if (!(msr & MDE))
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return 0;
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/*
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* If address transfer phase finished,
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* goto data phase.
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*/
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if (msr & MAT)
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rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
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if (priv->pos < msg->len) {
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/*
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* Prepare next data to ICRXTX register.
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* This data will go to _SHIFT_ register.
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*
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* *
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* [ICRXTX] -> [SHIFT] -> [I2C bus]
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*/
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rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
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priv->pos++;
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} else {
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/*
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* The last data was pushed to ICRXTX on _PREV_ empty irq.
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* It is on _SHIFT_ register, and will sent to I2C bus.
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*
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* *
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* [ICRXTX] -> [SHIFT] -> [I2C bus]
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*/
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if (priv->flags & ID_LAST_MSG)
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/*
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* If current msg is the _LAST_ msg,
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* prepare stop condition here.
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* ID_DONE will be set on STOP irq.
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*/
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rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
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else
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/*
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* If current msg is _NOT_ last msg,
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* it doesn't call stop phase.
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* thus, there is no STOP irq.
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* return ID_DONE here.
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*/
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return ID_DONE;
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}
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rcar_i2c_send_restart(priv);
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return 0;
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}
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static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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/*
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* FIXME
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* sometimes, unknown interrupt happened.
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* Do nothing
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*/
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if (!(msr & MDR))
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return 0;
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if (msr & MAT) {
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/*
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* Address transfer phase finished,
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* but, there is no data at this point.
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* Do nothing.
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*/
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} else if (priv->pos < msg->len) {
|
||||
/*
|
||||
* get received data
|
||||
*/
|
||||
msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
|
||||
priv->pos++;
|
||||
}
|
||||
|
||||
/*
|
||||
* If next received data is the _LAST_,
|
||||
* go to STOP phase,
|
||||
* otherwise, go to DATA phase.
|
||||
*/
|
||||
if (priv->pos + 1 >= msg->len)
|
||||
rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
|
||||
else
|
||||
rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA);
|
||||
|
||||
rcar_i2c_recv_restart(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
|
||||
{
|
||||
struct rcar_i2c_priv *priv = ptr;
|
||||
struct device *dev = rcar_i2c_priv_to_dev(priv);
|
||||
u32 msr;
|
||||
|
||||
/*-------------- spin lock -----------------*/
|
||||
spin_lock(&priv->lock);
|
||||
|
||||
msr = rcar_i2c_status_get(priv);
|
||||
|
||||
/*
|
||||
* Arbitration lost
|
||||
*/
|
||||
if (msr & MAL) {
|
||||
/*
|
||||
* CAUTION
|
||||
*
|
||||
* When arbitration lost, device become _slave_ mode.
|
||||
*/
|
||||
dev_dbg(dev, "Arbitration Lost\n");
|
||||
rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop
|
||||
*/
|
||||
if (msr & MST) {
|
||||
dev_dbg(dev, "Stop\n");
|
||||
rcar_i2c_flags_set(priv, ID_DONE);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Nack
|
||||
*/
|
||||
if (msr & MNR) {
|
||||
dev_dbg(dev, "Nack\n");
|
||||
|
||||
/* go to stop phase */
|
||||
rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP);
|
||||
rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP);
|
||||
rcar_i2c_flags_set(priv, ID_NACK);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* recv/send
|
||||
*/
|
||||
if (rcar_i2c_is_recv(priv))
|
||||
rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
|
||||
else
|
||||
rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
|
||||
|
||||
out:
|
||||
if (rcar_i2c_flags_has(priv, ID_DONE)) {
|
||||
rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE);
|
||||
rcar_i2c_status_clear(priv);
|
||||
wake_up(&priv->wait);
|
||||
}
|
||||
|
||||
spin_unlock(&priv->lock);
|
||||
/*-------------- spin unlock -----------------*/
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
|
||||
struct i2c_msg *msgs,
|
||||
int num)
|
||||
{
|
||||
struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
|
||||
struct device *dev = rcar_i2c_priv_to_dev(priv);
|
||||
unsigned long flags;
|
||||
int i, ret, timeout;
|
||||
|
||||
pm_runtime_get_sync(dev);
|
||||
|
||||
/*-------------- spin lock -----------------*/
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
rcar_i2c_init(priv);
|
||||
rcar_i2c_clock_start(priv);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
/*-------------- spin unlock -----------------*/
|
||||
|
||||
ret = -EINVAL;
|
||||
for (i = 0; i < num; i++) {
|
||||
/*-------------- spin lock -----------------*/
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
/* init each data */
|
||||
priv->msg = &msgs[i];
|
||||
priv->pos = 0;
|
||||
priv->flags = 0;
|
||||
if (priv->msg == &msgs[num - 1])
|
||||
rcar_i2c_flags_set(priv, ID_LAST_MSG);
|
||||
|
||||
/* start send/recv */
|
||||
if (rcar_i2c_is_recv(priv))
|
||||
ret = rcar_i2c_recv(priv);
|
||||
else
|
||||
ret = rcar_i2c_send(priv);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
/*-------------- spin unlock -----------------*/
|
||||
|
||||
if (ret < 0)
|
||||
break;
|
||||
|
||||
/*
|
||||
* wait result
|
||||
*/
|
||||
timeout = wait_event_timeout(priv->wait,
|
||||
rcar_i2c_flags_has(priv, ID_DONE),
|
||||
5 * HZ);
|
||||
if (!timeout) {
|
||||
ret = -ETIMEDOUT;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* error handling
|
||||
*/
|
||||
if (rcar_i2c_flags_has(priv, ID_NACK)) {
|
||||
ret = -EREMOTEIO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
|
||||
ret = -EAGAIN;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = i + 1; /* The number of transfer */
|
||||
}
|
||||
|
||||
pm_runtime_put(dev);
|
||||
|
||||
if (ret < 0)
|
||||
dev_err(dev, "error %d : %x\n", ret, priv->flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 rcar_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm rcar_i2c_algo = {
|
||||
.master_xfer = rcar_i2c_master_xfer,
|
||||
.functionality = rcar_i2c_func,
|
||||
};
|
||||
|
||||
static int __devinit rcar_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct i2c_rcar_platform_data *pdata = pdev->dev.platform_data;
|
||||
struct rcar_i2c_priv *priv;
|
||||
struct i2c_adapter *adap;
|
||||
struct resource *res;
|
||||
struct device *dev = &pdev->dev;
|
||||
u32 bus_speed;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "no mmio resources\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
dev_err(dev, "no mem for private data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
bus_speed = 100000; /* default 100 kHz */
|
||||
if (pdata && pdata->bus_speed)
|
||||
bus_speed = pdata->bus_speed;
|
||||
ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
priv->io = devm_ioremap(dev, res->start, resource_size(res));
|
||||
if (!priv->io) {
|
||||
dev_err(dev, "cannot ioremap\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
priv->irq = platform_get_irq(pdev, 0);
|
||||
init_waitqueue_head(&priv->wait);
|
||||
spin_lock_init(&priv->lock);
|
||||
|
||||
adap = &priv->adap;
|
||||
adap->nr = pdev->id;
|
||||
adap->algo = &rcar_i2c_algo;
|
||||
adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
||||
adap->retries = 3;
|
||||
adap->dev.parent = dev;
|
||||
i2c_set_adapdata(adap, priv);
|
||||
strlcpy(adap->name, pdev->name, sizeof(adap->name));
|
||||
|
||||
ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0,
|
||||
dev_name(dev), priv);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "cannot get irq %d\n", priv->irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = i2c_add_numbered_adapter(adap);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "reg adap failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
dev_info(dev, "probed\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devexit rcar_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
i2c_del_adapter(&priv->adap);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rcar_i2c_drv = {
|
||||
.driver = {
|
||||
.name = "i2c-rcar",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = rcar_i2c_probe,
|
||||
.remove = __devexit_p(rcar_i2c_remove),
|
||||
};
|
||||
|
||||
module_platform_driver(rcar_i2c_drv);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
|
||||
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
|
||||
10
include/linux/i2c/i2c-rcar.h
Normal file
10
include/linux/i2c/i2c-rcar.h
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#ifndef __I2C_R_CAR_H__
|
||||
#define __I2C_R_CAR_H__
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
struct i2c_rcar_platform_data {
|
||||
u32 bus_speed;
|
||||
};
|
||||
|
||||
#endif /* __I2C_R_CAR_H__ */
|
||||
Loading…
Reference in a new issue