[ARM] spelling fixes
Spelling fixes in arch/arm/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Simon Arlott
Russell King
parent
fc432e1952
commit
6cbdc8c535
39 changed files with 62 additions and 62 deletions
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@ -6,7 +6,7 @@
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* copy data to/from buffers located outside the DMA region. This
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* only works for systems in which DMA memory is at the bottom of
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* RAM, the remainder of memory is at the top and the DMA memory
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* can be marked as ZONE_DMA. Anything beyond that such as discontigous
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* can be marked as ZONE_DMA. Anything beyond that such as discontiguous
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* DMA windows will require custom implementations that reserve memory
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* areas at early bootup.
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*
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@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq)
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* unmask it, in the same way we need to unmask an interrupt when
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* we first enable it.
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*
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* The GIC has a seperate notion of "end of interrupt" to re-enable
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* The GIC has a separate notion of "end of interrupt" to re-enable
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* an interrupt after handling, in order to support hardware
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* prioritisation.
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*
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@ -20,7 +20,7 @@
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* typically including LCD parameters are loaded by the bootloader at the
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* address PARAM_BASE. As the kernel will overwrite them, we need to store
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* them early in the boot process, then pass them to the appropriate drivers.
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* Not all devices use all paramaters but the format is common to all.
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* Not all devices use all parameters but the format is common to all.
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*/
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#ifdef CONFIG_ARCH_SA1100
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#define PARAM_BASE 0xe8ffc000
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@ -291,7 +291,7 @@ static void sharpsl_chrg_full_timer(unsigned long data)
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}
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/* Charging Finished Interrupt (Not present on Corgi) */
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/* Can trigger at the same time as an AC staus change so
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/* Can trigger at the same time as an AC status change so
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delay until after that has been processed */
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irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
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{
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@ -635,7 +635,7 @@ static int sharpsl_fatal_check(void)
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static int sharpsl_off_charge_error(void)
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{
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dev_err(sharpsl_pm.dev, "Offline Charger: Error occured.\n");
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dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
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sharpsl_pm.machinfo->charge(0);
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sharpsl_pm_led(SHARPSL_LED_ERROR);
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sharpsl_pm.charge_mode = CHRG_ERROR;
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@ -691,14 +691,14 @@ static int sharpsl_off_charge_battery(void)
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time = RCNR;
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while(1) {
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/* Check if any wakeup event had occured */
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/* Check if any wakeup event had occurred */
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if (sharpsl_pm.machinfo->charger_wakeup() != 0)
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return 0;
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/* Check for timeout */
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if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
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return 1;
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if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
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dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occured. Retrying to check\n");
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dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
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sharpsl_pm.full_count++;
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sharpsl_pm.machinfo->charge(0);
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mdelay(SHARPSL_CHARGE_WAIT_TIME);
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@ -714,7 +714,7 @@ static int sharpsl_off_charge_battery(void)
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time = RCNR;
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while(1) {
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/* Check if any wakeup event had occured */
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/* Check if any wakeup event had occurred */
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if (sharpsl_pm.machinfo->charger_wakeup() != 0)
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return 0;
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/* Check for timeout */
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@ -320,7 +320,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[])
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EXPORT_SYMBOL(kernel_execve);
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/*
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* Since loff_t is a 64 bit type we avoid a lot of ABI hastle
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* Since loff_t is a 64 bit type we avoid a lot of ABI hassle
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* with a different argument ordering.
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*/
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asmlinkage long sys_arm_fadvise64_64(int fd, int advice,
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@ -47,7 +47,7 @@
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* @store: store instruction
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*
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* Note: we can trivially conditionalise the store instruction
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* to avoid dirting the data cache.
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* to avoid dirtying the data cache.
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*/
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.macro testop, instr, store
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add r1, r1, r0, lsr #3
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@ -79,7 +79,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
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.pullup_pin = AT91_PIN_PD9,
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};
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/* FIXME: user dependend */
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/* FIXME: user dependant */
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// static struct at91_cf_data __initdata carmeva_cf_data = {
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// .det_pin = AT91_PIN_PB0,
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// .rst_pin = AT91_PIN_PC5,
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@ -100,17 +100,17 @@ static struct spi_board_info carmeva_spi_devices[] = {
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.chip_select = 0,
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.max_speed_hz = 10 * 1000 * 1000,
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},
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{ /* User accessable spi - cs1 (250KHz) */
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{ /* User accessible spi - cs1 (250KHz) */
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.modalias = "spi-cs1",
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.chip_select = 1,
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.max_speed_hz = 250 * 1000,
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},
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{ /* User accessable spi - cs2 (1MHz) */
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{ /* User accessible spi - cs2 (1MHz) */
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.modalias = "spi-cs2",
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.chip_select = 2,
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.max_speed_hz = 1 * 1000 * 1000,
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},
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{ /* User accessable spi - cs3 (10MHz) */
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{ /* User accessible spi - cs3 (10MHz) */
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.modalias = "spi-cs3",
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.chip_select = 3,
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.max_speed_hz = 10 * 1000 * 1000,
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@ -143,7 +143,7 @@ h7202_timer_interrupt(int irq, void *dev_id)
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}
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/*
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* mask multiplexed timer irq's
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* mask multiplexed timer IRQs
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*/
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static void inline mask_timerx_irq (u32 irq)
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{
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@ -153,7 +153,7 @@ static void inline mask_timerx_irq (u32 irq)
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}
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/*
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* unmask multiplexed timer irq's
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* unmask multiplexed timer IRQs
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*/
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static void inline unmask_timerx_irq (u32 irq)
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{
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@ -245,7 +245,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
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if(mpctl0) {
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CSCR |= CSCR_MPLL_RESTART;
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/* Wait until MPLL is stablized */
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/* Wait until MPLL is stabilized */
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while( CSCR & CSCR_MPLL_RESTART );
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imx_set_async_mode();
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@ -131,7 +131,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch,
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* The function setups DMA channel source and destination addresses for transfer
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* specified by provided parameters. The scatter-gather emulation is disabled,
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* because linear data block
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* form the physical address range is transfered.
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* form the physical address range is transferred.
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* Return value: if incorrect parameters are provided -%EINVAL.
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* Zero indicates success.
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*/
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@ -192,7 +192,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
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* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
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* or %DMA_MODE_WRITE from memory to the device
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*
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* The function setups DMA channel state and registers to be ready for transfer
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* The function sets up DMA channel state and registers to be ready for transfer
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* specified by provided parameters. The scatter-gather emulation is set up
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* according to the parameters.
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*
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@ -212,7 +212,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
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*
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* %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
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*
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* Be carefull there and do not mistakenly mix source and target device
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* Be careful here and do not mistakenly mix source and target device
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* port sizes constants, they are really different:
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* %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
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* %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
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@ -495,7 +495,7 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
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/*
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* The cleaning of @sg field would be questionable
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* there, because its value can help to compute
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* remaining/transfered bytes count in the handler
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* remaining/transferred bytes count in the handler
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*/
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/*imx_dma_channels[i].sg = NULL;*/
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@ -989,7 +989,7 @@ void __init iop13xx_pci_init(void)
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"imprecise external abort");
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}
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/* intialize the pci memory space. handle any combination of
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/* initialize the pci memory space. handle any combination of
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* atue and atux enabled/disabled
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*/
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int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
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@ -198,7 +198,7 @@ subsys_initcall(enp2611_pci_init);
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/*************************************************************************
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* ENP-2611 Machine Intialization
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* ENP-2611 Machine Initialization
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*************************************************************************/
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static struct flash_platform_data enp2611_flash_platform_data = {
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.map_name = "cfi_probe",
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@ -195,7 +195,7 @@ void __init ixdp2x00_map_io(void)
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* instances of the kernel. So far so good. Peers on the PCI bus running
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* Linux is a common design in telecom systems. The problem is that instead
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* of all the devices being controlled by a single host, different
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* devices are controlles by different NPUs on the same bus, leading to
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* devices are controlled by different NPUs on the same bus, leading to
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* multiple hosts on the bus. The exact bus layout looks like:
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*
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* Bus 0
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@ -211,7 +211,7 @@ void __init ixdp2x00_map_io(void)
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* | | | | |
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* ... Dev PMC Media Eth0 Eth1 ...
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*
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* The master controlls all but Eth1, which is controlled by the
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* The master controls all but Eth1, which is controlled by the
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* slave. What this means is that the both the master and the slave
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* have to scan the bus, but only one of them can enumerate the bus.
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* In addition, after the bus is scanned, each kernel must remove
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@ -276,7 +276,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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/* Device is located after first MB bridge */
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case 0x0008:
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if (tmp_bus == dev->bus) {
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/* Device is located directy after first MB bridge */
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/* Device is located directly after first MB bridge */
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switch (devpin) {
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case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
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if (machine_is_ixdp2401())
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@ -299,7 +299,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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break;
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case 0x0010:
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if (tmp_bus == dev->bus) {
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/* Device is located directy after second MB bridge */
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/* Device is located directly after second MB bridge */
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/* Secondary bus of second bridge */
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switch (devpin) {
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case DEVPIN(0, 1): /* DB#0 */
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@ -348,7 +348,7 @@ int __init ixdp2x01_pci_init(void)
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subsys_initcall(ixdp2x01_pci_init);
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/*************************************************************************
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* IXDP2x01 Machine Intialization
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* IXDP2x01 Machine Initialization
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*************************************************************************/
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static struct flash_platform_data ixdp2x01_flash_platform_data = {
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.map_name = "cfi_probe",
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@ -102,7 +102,7 @@ int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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}
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/*
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* We don't do error checks by callling clear_master_aborts() b/c the
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* We don't do error checks by calling clear_master_aborts() b/c the
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* assumption is that the caller did a read first to make sure a device
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* exists.
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*/
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@ -389,7 +389,7 @@ struct sys_timer ixp23xx_timer = {
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/*************************************************************************
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* IXP23xx Platform Initializaion
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* IXP23xx Platform Initialization
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*************************************************************************/
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static struct resource ixp23xx_uart_resources[] = {
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{
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@ -1,7 +1,7 @@
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/*
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* arch/arm/mach-ixp4xx/gtwx5715-setup.c
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*
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* Gemtek GTWX5715 (Linksys WRV54G) board settup
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* Gemtek GTWX5715 (Linksys WRV54G) board setup
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*
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* Copyright (C) 2004 George T. Joseph
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* Derived from Coyote
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@ -126,7 +126,7 @@ static struct clcd_panel_extra lcd_panel_extra = {
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*/
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/* The full horozontal cycle (Th) is clock/360/400/450. */
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/* The full horizontal cycle (Th) is clock/360/400/450. */
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/* The full vertical cycle (Tv) is line/251/262/280. */
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#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
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@ -162,7 +162,7 @@ static struct clcd_panel lcd_panel = {
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/* Logic Product Development LCD 6.4" VGA -10 */
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/* Sharp PN LQ64D343 */
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/* The full horozontal cycle (Th) is clock/750/800/900. */
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/* The full horizontal cycle (Th) is clock/750/800/900. */
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/* The full vertical cycle (Tv) is line/515/525/560. */
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#define PIX_CLOCK_TARGET (28330000)
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@ -243,7 +243,7 @@ static struct clcd_panel lcd_panel = {
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* (fdisk, e2fsck). And, at that speed the display may have a visible
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* flicker. */
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/* The full horozontal cycle (Th) is clock/832/1056/1395. */
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/* The full horizontal cycle (Th) is clock/832/1056/1395. */
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#define PIX_CLOCK_TARGET (20000000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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@ -35,7 +35,7 @@ static unsigned long ns9xxx_timer_gettimeoffset(void)
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{
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/* return the microseconds which have passed since the last interrupt
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* was _serviced_. That is, if an interrupt is pending or the counter
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* reloads, return one periode more. */
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* reloads, return one period more. */
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u32 counter1 = SYS_TR(0);
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int pending = SYS_ISR & (1 << IRQ_TIMER0);
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@ -385,7 +385,7 @@ static void __init osk_init(void)
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/* Workaround for wrong CS3 (NOR flash) timing
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* There are some U-Boot versions out there which configure
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* wrong CS3 memory timings. This mainly leads to CRC
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* or similiar errors if you use NOR flash (e.g. with JFFS2)
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* or similar errors if you use NOR flash (e.g. with JFFS2)
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*/
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if (EMIFS_CCS(3) != EMIFS_CS3_VAL)
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EMIFS_CCS(3) = EMIFS_CS3_VAL;
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@ -7,7 +7,7 @@
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*
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* Original version : Laurent Gonzalez
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*
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* Maintainters : http://palmtelinux.sf.net
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* Maintainers : http://palmtelinux.sf.net
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* palmtelinux-developpers@lists.sf.net
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*
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* This program is free software; you can redistribute it and/or modify
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@ -438,7 +438,7 @@ void omap_pm_suspend(void)
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omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
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/*
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* Reenable interrupts
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* Re-enable interrupts
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*/
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local_irq_enable();
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@ -443,7 +443,7 @@ static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
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/*
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* Check the DLL lock state, and return tue if running in unlock mode.
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* This is needed to compenste for the shifted DLL value in unlock mode.
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* This is needed to compensate for the shifted DLL value in unlock mode.
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*/
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static u32 omap2_dll_force_needed(void)
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{
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@ -338,7 +338,7 @@ struct prcm_config {
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/*
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* These represent optimal values for common parts, it won't work for all.
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* As long as you scale down, most parameters are still work, they just
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* become sub-optimal. The RFR value goes in the oppisite direction. If you
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* become sub-optimal. The RFR value goes in the opposite direction. If you
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* don't adjust it down as your clock period increases the refresh interval
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* will not be met. Setting all parameters for complete worst case may work,
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* but may cut memory performance by 2x. Due to errata the DLLs need to be
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@ -384,7 +384,7 @@ struct prcm_config {
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* Filling in table based on H4 boards and 2430-SDPs variants available.
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* There are quite a few more rates combinations which could be defined.
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*
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* When multiple values are defiend the start up will try and choose the
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* When multiple values are defined the start up will try and choose the
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* fastest one. If a 'fast' value is defined, then automatically, the /2
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* one should be included as it can be used. Generally having more that
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* one fast set does not make sense, as static timings need to be changed
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@ -40,7 +40,7 @@
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#define PICTRL_ADRS 0x06
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#define POLCTRL_ADRS 0x07
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/* Resgister Bit Definitions */
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/* Register Bit Definitions */
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#define RESCTL_QVGA 0x01
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||||
#define RESCTL_VGA 0x00
|
||||
|
||||
|
|
@ -55,11 +55,11 @@
|
|||
#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
|
||||
#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
|
||||
#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
|
||||
#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */
|
||||
#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
|
||||
#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
|
||||
|
||||
#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
|
||||
#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */
|
||||
#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
|
||||
#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
|
||||
|
||||
#define PICTRL_INIT_STATE 0x01
|
||||
|
|
@ -145,7 +145,7 @@ static void lcdtg_set_common_voltage(u8 base_data, u8 data)
|
|||
lcdtg_i2c_send_stop(base_data);
|
||||
}
|
||||
|
||||
/* Set Phase Adjuct */
|
||||
/* Set Phase Adjust */
|
||||
static void lcdtg_set_phadadj(int mode)
|
||||
{
|
||||
int adj;
|
||||
|
|
@ -226,7 +226,7 @@ static void lcdtg_hw_init(int mode)
|
|||
/* Signals output enable */
|
||||
corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
|
||||
|
||||
/* Set Phase Adjuct */
|
||||
/* Set Phase Adjust */
|
||||
lcdtg_set_phadadj(mode);
|
||||
|
||||
/* Initialize for Input Signals from ATI */
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ static struct corgissp_machinfo *ssp_machinfo;
|
|||
* There are three devices connected to the SSP interface:
|
||||
* 1. A touchscreen controller (TI ADS7846 compatible)
|
||||
* 2. An LCD contoller (with some Backlight functionality)
|
||||
* 3. A battery moinitoring IC (Maxim MAX1111)
|
||||
* 3. A battery monitoring IC (Maxim MAX1111)
|
||||
*
|
||||
* Each device uses a different speed/mode of communication.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ static unsigned long mpcore_timer_rate;
|
|||
/*
|
||||
* local_timer_ack: checks for a local timer interrupt.
|
||||
*
|
||||
* If a local timer interrupt has occured, acknowledge and return 1.
|
||||
* If a local timer interrupt has occurred, acknowledge and return 1.
|
||||
* Otherwise, return 0.
|
||||
*/
|
||||
int local_timer_ack(void)
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
#include <asm/plat-s3c24xx/devs.h>
|
||||
#include <asm/plat-s3c24xx/cpu.h>
|
||||
|
||||
/* onboard perihpheral map */
|
||||
/* onboard perihperal map */
|
||||
|
||||
static struct map_desc osiris_iodesc[] __initdata = {
|
||||
/* ISA IO areas (may be over-written later) */
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ static unsigned long __init sa1100_get_rtc_time(void)
|
|||
{
|
||||
/*
|
||||
* According to the manual we should be able to let RTTR be zero
|
||||
* and then a default diviser for a 32.768KHz clock is used.
|
||||
* and then a default divisor for a 32.768KHz clock is used.
|
||||
* Apparently this doesn't work, at least for my SA1110 rev 5.
|
||||
* If the clock divider is uninitialized then reset it to the
|
||||
* default value to get the 1Hz clock.
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 1995 Linus Torvalds
|
||||
* Modifications for ARM processor (c) 1995-2001 Russell King
|
||||
* Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc.
|
||||
* Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
|
||||
* - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
|
||||
* Copyright (C) 1996, Cygnus Software Technologies Ltd.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -346,7 +346,7 @@ void __iounmap(volatile void __iomem *addr)
|
|||
#ifndef CONFIG_SMP
|
||||
/*
|
||||
* If this is a section based mapping we need to handle it
|
||||
* specially as the VM subysystem does not know how to handle
|
||||
* specially as the VM subsystem does not know how to handle
|
||||
* such a beast. We need the lock here b/c we need to clear
|
||||
* all the mappings before the area can be reclaimed
|
||||
* by someone else.
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ static struct cachepolicy cache_policies[] __initdata = {
|
|||
};
|
||||
|
||||
/*
|
||||
* These are useful for identifing cache coherency
|
||||
* These are useful for identifying cache coherency
|
||||
* problems by allowing the cache or the cache and
|
||||
* writebuffer to be turned off. (Note: the write
|
||||
* buffer should not be on and the cache off).
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ static int iop3xx_pci_status(void)
|
|||
|
||||
/*
|
||||
* Simply write the address register and read the configuration
|
||||
* data. Note that the 4 nop's ensure that we are able to handle
|
||||
* data. Note that the 4 nops ensure that we are able to handle
|
||||
* a delayed abort (in theory.)
|
||||
*/
|
||||
static u32 iop3xx_read(unsigned long addr)
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
|
|||
}
|
||||
if (info != NULL) {
|
||||
/* Check the length as a lame attempt to check for
|
||||
* binary inconsistancy. */
|
||||
* binary inconsistency. */
|
||||
if (len != NO_LENGTH_CHECK) {
|
||||
/* Word-align len */
|
||||
if (len & 0x03)
|
||||
|
|
|
|||
|
|
@ -1172,7 +1172,7 @@ static void set_b1_regs(void)
|
|||
break;
|
||||
default:
|
||||
BUG();
|
||||
return; /* Supress warning about uninitialized vars */
|
||||
return; /* Suppress warning about uninitialized vars */
|
||||
}
|
||||
|
||||
if (omap_dma_in_1510_mode()) {
|
||||
|
|
|
|||
|
|
@ -59,8 +59,8 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
|
|||
|
||||
/*
|
||||
* Depending on the target RAMFS firewall setup, the public usable amount of
|
||||
* SRAM varies. The default accessable size for all device types is 2k. A GP
|
||||
* device allows ARM11 but not other initators for full size. This
|
||||
* SRAM varies. The default accessible size for all device types is 2k. A GP
|
||||
* device allows ARM11 but not other initiators for full size. This
|
||||
* functionality seems ok until some nice security API happens.
|
||||
*/
|
||||
static int is_sram_locked(void)
|
||||
|
|
@ -71,7 +71,7 @@ static int is_sram_locked(void)
|
|||
type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
|
||||
|
||||
if (type == GP_DEVICE) {
|
||||
/* RAMFW: R/W access to all initators for all qualifier sets */
|
||||
/* RAMFW: R/W access to all initiators for all qualifier sets */
|
||||
if (cpu_is_omap242x()) {
|
||||
__raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
|
||||
__raw_writel(0xCFDE, VA_READPERM0); /* all i-read */
|
||||
|
|
|
|||
|
|
@ -177,7 +177,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
|
|||
|
||||
/* NOTE: SPEED and SUSP aren't configured here. OTG hosts
|
||||
* may be able to use I2C requests to set those bits along
|
||||
* with VBUS switching and overcurrent detction.
|
||||
* with VBUS switching and overcurrent detection.
|
||||
*/
|
||||
|
||||
if (cpu_class_is_omap1() && nwires != 6)
|
||||
|
|
|
|||
|
|
@ -1153,7 +1153,7 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
|
|||
*
|
||||
* hwcfg: the value for xxxSTCn register,
|
||||
* bit 0: 0=increment pointer, 1=leave pointer
|
||||
* bit 1: 0=soucre is AHB, 1=soucre is APB
|
||||
* bit 1: 0=source is AHB, 1=source is APB
|
||||
*
|
||||
* devaddr: physical address of the source
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -555,7 +555,7 @@ static int s3c2410_pm_enter(suspend_state_t state)
|
|||
__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
|
||||
__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
|
||||
|
||||
/* call cpu specific preperation */
|
||||
/* call cpu specific preparation */
|
||||
|
||||
pm_cpu_prep();
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue