Merge branch 'exynos/dt' into late/dt
* exynos/dt: (125 commits) ARM: dts: add PDMA0 changes for exynos5440 ARM: dts: Add cpufreq controller node for Exynos5440 SoC ARM: dts: Fix gmac clock ids due to changes in Exynos5440 ARM: dts: add device tree file for SD5v1 board ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440 ARM: dts: add PMU support in exynos5440 ARM: dts: Add node for GMAC for exynos5440 ARM: dts: list the interrupts generated by pin-controller on Exynos5440 ARM: dts: Add FIMD DT binding Documentation ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts ARM: dts: Add FIMD node to exynos4 ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series ARM: dts: Add display timing node to exynos5250-smdk5250.dts ARM: dts: Add FIMD node to exynos5 ARM: dts: Add virtual GIC DT bindings for exynos5440 ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings ARM: dts: add usb 2.0 clock references to exynos5250 device tree ARM: dts: Add architected timer nodes for exynos5250 ARM: dts: Declare the gic as a15 compatible for exynos5250 ARM: dts: Add HDMI HPD and regulator node for Arndale board ...
This commit is contained in:
Olof Johansson
commit
6cae0fafe3
149 changed files with 6962 additions and 5558 deletions
7
Documentation/devicetree/bindings/arm/samsung/sysreg.txt
Normal file
7
Documentation/devicetree/bindings/arm/samsung/sysreg.txt
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
|
||||
|
||||
Properties:
|
||||
- name : should be 'sysreg';
|
||||
- compatible : should contain "samsung,<chip name>-sysreg", "syscon";
|
||||
For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
|
||||
- reg : offset and length of the register set.
|
||||
288
Documentation/devicetree/bindings/clock/exynos4-clock.txt
Normal file
288
Documentation/devicetree/bindings/clock/exynos4-clock.txt
Normal file
|
|
@ -0,0 +1,288 @@
|
|||
* Samsung Exynos4 Clock Controller
|
||||
|
||||
The Exynos4 clock controller generates and supplies clock to various controllers
|
||||
within the Exynos4 SoC. The clock binding described here is applicable to all
|
||||
SoC's in the Exynos4 family.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
|
||||
- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume. Some of the clocks are available only on a particular
|
||||
Exynos4 SoC and this is specified where applicable.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
xxti 1
|
||||
xusbxti 2
|
||||
fin_pll 3
|
||||
fout_apll 4
|
||||
fout_mpll 5
|
||||
fout_epll 6
|
||||
fout_vpll 7
|
||||
sclk_apll 8
|
||||
sclk_mpll 9
|
||||
sclk_epll 10
|
||||
sclk_vpll 11
|
||||
arm_clk 12
|
||||
aclk200 13
|
||||
aclk100 14
|
||||
aclk160 15
|
||||
aclk133 16
|
||||
mout_mpll_user_t 17 Exynos4x12
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||||
mout_mpll_user_c 18 Exynos4x12
|
||||
mout_core 19
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||||
mout_apll 20
|
||||
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
sclk_fimc0 128
|
||||
sclk_fimc1 129
|
||||
sclk_fimc2 130
|
||||
sclk_fimc3 131
|
||||
sclk_cam0 132
|
||||
sclk_cam1 133
|
||||
sclk_csis0 134
|
||||
sclk_csis1 135
|
||||
sclk_hdmi 136
|
||||
sclk_mixer 137
|
||||
sclk_dac 138
|
||||
sclk_pixel 139
|
||||
sclk_fimd0 140
|
||||
sclk_mdnie0 141 Exynos4412
|
||||
sclk_mdnie_pwm0 12 142 Exynos4412
|
||||
sclk_mipi0 143
|
||||
sclk_audio0 144
|
||||
sclk_mmc0 145
|
||||
sclk_mmc1 146
|
||||
sclk_mmc2 147
|
||||
sclk_mmc3 148
|
||||
sclk_mmc4 149
|
||||
sclk_sata 150 Exynos4210
|
||||
sclk_uart0 151
|
||||
sclk_uart1 152
|
||||
sclk_uart2 153
|
||||
sclk_uart3 154
|
||||
sclk_uart4 155
|
||||
sclk_audio1 156
|
||||
sclk_audio2 157
|
||||
sclk_spdif 158
|
||||
sclk_spi0 159
|
||||
sclk_spi1 160
|
||||
sclk_spi2 161
|
||||
sclk_slimbus 162
|
||||
sclk_fimd1 163 Exynos4210
|
||||
sclk_mipi1 164 Exynos4210
|
||||
sclk_pcm1 165
|
||||
sclk_pcm2 166
|
||||
sclk_i2s1 167
|
||||
sclk_i2s2 168
|
||||
sclk_mipihsi 169 Exynos4412
|
||||
sclk_mfc 170
|
||||
sclk_pcm0 171
|
||||
sclk_g3d 172
|
||||
sclk_pwm_isp 173 Exynos4x12
|
||||
sclk_spi0_isp 174 Exynos4x12
|
||||
sclk_spi1_isp 175 Exynos4x12
|
||||
sclk_uart_isp 176 Exynos4x12
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
fimc0 256
|
||||
fimc1 257
|
||||
fimc2 258
|
||||
fimc3 259
|
||||
csis0 260
|
||||
csis1 261
|
||||
jpeg 262
|
||||
smmu_fimc0 263
|
||||
smmu_fimc1 264
|
||||
smmu_fimc2 265
|
||||
smmu_fimc3 266
|
||||
smmu_jpeg 267
|
||||
vp 268
|
||||
mixer 269
|
||||
tvenc 270 Exynos4210
|
||||
hdmi 271
|
||||
smmu_tv 272
|
||||
mfc 273
|
||||
smmu_mfcl 274
|
||||
smmu_mfcr 275
|
||||
g3d 276
|
||||
g2d 277 Exynos4210
|
||||
rotator 278 Exynos4210
|
||||
mdma 279 Exynos4210
|
||||
smmu_g2d 280 Exynos4210
|
||||
smmu_rotator 281 Exynos4210
|
||||
smmu_mdma 282 Exynos4210
|
||||
fimd0 283
|
||||
mie0 284
|
||||
mdnie0 285 Exynos4412
|
||||
dsim0 286
|
||||
smmu_fimd0 287
|
||||
fimd1 288 Exynos4210
|
||||
mie1 289 Exynos4210
|
||||
dsim1 290 Exynos4210
|
||||
smmu_fimd1 291 Exynos4210
|
||||
pdma0 292
|
||||
pdma1 293
|
||||
pcie_phy 294
|
||||
sata_phy 295 Exynos4210
|
||||
tsi 296
|
||||
sdmmc0 297
|
||||
sdmmc1 298
|
||||
sdmmc2 299
|
||||
sdmmc3 300
|
||||
sdmmc4 301
|
||||
sata 302 Exynos4210
|
||||
sromc 303
|
||||
usb_host 304
|
||||
usb_device 305
|
||||
pcie 306
|
||||
onenand 307
|
||||
nfcon 308
|
||||
smmu_pcie 309
|
||||
gps 310
|
||||
smmu_gps 311
|
||||
uart0 312
|
||||
uart1 313
|
||||
uart2 314
|
||||
uart3 315
|
||||
uart4 316
|
||||
i2c0 317
|
||||
i2c1 318
|
||||
i2c2 319
|
||||
i2c3 320
|
||||
i2c4 321
|
||||
i2c5 322
|
||||
i2c6 323
|
||||
i2c7 324
|
||||
i2c_hdmi 325
|
||||
tsadc 326
|
||||
spi0 327
|
||||
spi1 328
|
||||
spi2 329
|
||||
i2s1 330
|
||||
i2s2 331
|
||||
pcm0 332
|
||||
i2s0 333
|
||||
pcm1 334
|
||||
pcm2 335
|
||||
pwm 336
|
||||
slimbus 337
|
||||
spdif 338
|
||||
ac97 339
|
||||
modemif 340
|
||||
chipid 341
|
||||
sysreg 342
|
||||
hdmi_cec 343
|
||||
mct 344
|
||||
wdt 345
|
||||
rtc 346
|
||||
keyif 347
|
||||
audss 348
|
||||
mipi_hsi 349 Exynos4210
|
||||
mdma2 350 Exynos4210
|
||||
pixelasyncm0 351
|
||||
pixelasyncm1 352
|
||||
fimc_lite0 353 Exynos4x12
|
||||
fimc_lite1 354 Exynos4x12
|
||||
ppmuispx 355 Exynos4x12
|
||||
ppmuispmx 356 Exynos4x12
|
||||
fimc_isp 357 Exynos4x12
|
||||
fimc_drc 358 Exynos4x12
|
||||
fimc_fd 359 Exynos4x12
|
||||
mcuisp 360 Exynos4x12
|
||||
gicisp 361 Exynos4x12
|
||||
smmu_isp 362 Exynos4x12
|
||||
smmu_drc 363 Exynos4x12
|
||||
smmu_fd 364 Exynos4x12
|
||||
smmu_lite0 365 Exynos4x12
|
||||
smmu_lite1 366 Exynos4x12
|
||||
mcuctl_isp 367 Exynos4x12
|
||||
mpwm_isp 368 Exynos4x12
|
||||
i2c0_isp 369 Exynos4x12
|
||||
i2c1_isp 370 Exynos4x12
|
||||
mtcadc_isp 371 Exynos4x12
|
||||
pwm_isp 372 Exynos4x12
|
||||
wdt_isp 373 Exynos4x12
|
||||
uart_isp 374 Exynos4x12
|
||||
asyncaxim 375 Exynos4x12
|
||||
smmu_ispcx 376 Exynos4x12
|
||||
spi0_isp 377 Exynos4x12
|
||||
spi1_isp 378 Exynos4x12
|
||||
pwm_isp_sclk 379 Exynos4x12
|
||||
spi0_isp_sclk 380 Exynos4x12
|
||||
spi1_isp_sclk 381 Exynos4x12
|
||||
uart_isp_sclk 382 Exynos4x12
|
||||
|
||||
[Mux Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
mout_fimc0 384
|
||||
mout_fimc1 385
|
||||
mout_fimc2 386
|
||||
mout_fimc3 387
|
||||
mout_cam0 388
|
||||
mout_cam1 389
|
||||
mout_csis0 390
|
||||
mout_csis1 391
|
||||
mout_g3d0 392
|
||||
mout_g3d1 393
|
||||
mout_g3d 394
|
||||
aclk400_mcuisp 395 Exynos4x12
|
||||
|
||||
[Div Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
div_isp0 450 Exynos4x12
|
||||
div_isp1 451 Exynos4x12
|
||||
div_mcuisp0 452 Exynos4x12
|
||||
div_mcuisp1 453 Exynos4x12
|
||||
div_aclk200 454 Exynos4x12
|
||||
div_aclk400_mcuisp 455 Exynos4x12
|
||||
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4210-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
177
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Normal file
177
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
* Samsung Exynos5250 Clock Controller
|
||||
|
||||
The Exynos5250 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5250 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
fin_pll 1
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
sclk_cam_bayer 128
|
||||
sclk_cam0 129
|
||||
sclk_cam1 130
|
||||
sclk_gscl_wa 131
|
||||
sclk_gscl_wb 132
|
||||
sclk_fimd1 133
|
||||
sclk_mipi1 134
|
||||
sclk_dp 135
|
||||
sclk_hdmi 136
|
||||
sclk_pixel 137
|
||||
sclk_audio0 138
|
||||
sclk_mmc0 139
|
||||
sclk_mmc1 140
|
||||
sclk_mmc2 141
|
||||
sclk_mmc3 142
|
||||
sclk_sata 143
|
||||
sclk_usb3 144
|
||||
sclk_jpeg 145
|
||||
sclk_uart0 146
|
||||
sclk_uart1 147
|
||||
sclk_uart2 148
|
||||
sclk_uart3 149
|
||||
sclk_pwm 150
|
||||
sclk_audio1 151
|
||||
sclk_audio2 152
|
||||
sclk_spdif 153
|
||||
sclk_spi0 154
|
||||
sclk_spi1 155
|
||||
sclk_spi2 156
|
||||
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
gscl0 256
|
||||
gscl1 257
|
||||
gscl2 258
|
||||
gscl3 259
|
||||
gscl_wa 260
|
||||
gscl_wb 261
|
||||
smmu_gscl0 262
|
||||
smmu_gscl1 263
|
||||
smmu_gscl2 264
|
||||
smmu_gscl3 265
|
||||
mfc 266
|
||||
smmu_mfcl 267
|
||||
smmu_mfcr 268
|
||||
rotator 269
|
||||
jpeg 270
|
||||
mdma1 271
|
||||
smmu_rotator 272
|
||||
smmu_jpeg 273
|
||||
smmu_mdma1 274
|
||||
pdma0 275
|
||||
pdma1 276
|
||||
sata 277
|
||||
usbotg 278
|
||||
mipi_hsi 279
|
||||
sdmmc0 280
|
||||
sdmmc1 281
|
||||
sdmmc2 282
|
||||
sdmmc3 283
|
||||
sromc 284
|
||||
usb2 285
|
||||
usb3 286
|
||||
sata_phyctrl 287
|
||||
sata_phyi2c 288
|
||||
uart0 289
|
||||
uart1 290
|
||||
uart2 291
|
||||
uart3 292
|
||||
uart4 293
|
||||
i2c0 294
|
||||
i2c1 295
|
||||
i2c2 296
|
||||
i2c3 297
|
||||
i2c4 298
|
||||
i2c5 299
|
||||
i2c6 300
|
||||
i2c7 301
|
||||
i2c_hdmi 302
|
||||
adc 303
|
||||
spi0 304
|
||||
spi1 305
|
||||
spi2 306
|
||||
i2s1 307
|
||||
i2s2 308
|
||||
pcm1 309
|
||||
pcm2 310
|
||||
pwm 311
|
||||
spdif 312
|
||||
ac97 313
|
||||
hsi2c0 314
|
||||
hsi2c1 315
|
||||
hs12c2 316
|
||||
hs12c3 317
|
||||
chipid 318
|
||||
sysreg 319
|
||||
pmu 320
|
||||
cmu_top 321
|
||||
cmu_core 322
|
||||
cmu_mem 323
|
||||
tzpc0 324
|
||||
tzpc1 325
|
||||
tzpc2 326
|
||||
tzpc3 327
|
||||
tzpc4 328
|
||||
tzpc5 329
|
||||
tzpc6 330
|
||||
tzpc7 331
|
||||
tzpc8 332
|
||||
tzpc9 333
|
||||
hdmi_cec 334
|
||||
mct 335
|
||||
wdt 336
|
||||
rtc 337
|
||||
tmu 338
|
||||
fimd1 339
|
||||
mie1 340
|
||||
dsim0 341
|
||||
dp 342
|
||||
mixer 343
|
||||
hdmi 345
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
61
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
Normal file
61
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
* Samsung Exynos5440 Clock Controller
|
||||
|
||||
The Exynos5440 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5440 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be "samsung,exynos5440-clock".
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
xtal 1
|
||||
arm_clk 2
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
spi_baud 16
|
||||
pb0_250 17
|
||||
pr0_250 18
|
||||
pr1_250 19
|
||||
b_250 20
|
||||
b_125 21
|
||||
b_200 22
|
||||
sata 23
|
||||
usb 24
|
||||
gmac0 25
|
||||
cs250 26
|
||||
pb0_250_o 27
|
||||
pr0_250_o 28
|
||||
pr1_250_o 29
|
||||
b_250_o 30
|
||||
b_125_o 31
|
||||
b_200_o 32
|
||||
sata_o 33
|
||||
usb_o 34
|
||||
gmac0_o 35
|
||||
cs250_o 36
|
||||
|
||||
Example: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
20
Documentation/devicetree/bindings/gpu/samsung-g2d.txt
Normal file
20
Documentation/devicetree/bindings/gpu/samsung-g2d.txt
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
* Samsung 2D Graphics Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible : value should be one among the following:
|
||||
(a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC
|
||||
(b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs
|
||||
(c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
- interrupts : G2D interrupt number to the CPU.
|
||||
|
||||
Example:
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -21,3 +21,24 @@ Required properties:
|
|||
|
||||
- samsung,mfc-l : Base address of the second memory bank used by MFC
|
||||
for DMA contiguous memory allocation and its size.
|
||||
|
||||
Optional properties:
|
||||
- samsung,power-domain : power-domain property defined with a phandle
|
||||
to respective power domain.
|
||||
|
||||
Example:
|
||||
SoC specific DT entry:
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
Board specific DT entry:
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
Samsung's Multi Core Timer (MCT)
|
||||
|
||||
The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
|
||||
global timer and CPU local timers. The global timer is a 64-bit free running
|
||||
up-counter and can generate 4 interrupts when the counter reaches one of the
|
||||
four preset counter values. The CPU local timers are 32-bit free running
|
||||
down-counters and generate an interrupt when the counter expires. There is
|
||||
one CPU local timer instantiated in MCT for every CPU in the system.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "samsung,exynos4210-mct".
|
||||
(a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
|
||||
(b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
|
||||
|
||||
- reg: base address of the mct controller and length of the address space
|
||||
it occupies.
|
||||
|
||||
- interrupts: the list of interrupts generated by the controller. The following
|
||||
should be the order of the interrupts specified. The local timer interrupts
|
||||
should be specified after the four global timer interrupts have been
|
||||
specified.
|
||||
|
||||
0: Global Timer Interrupt 0
|
||||
1: Global Timer Interrupt 1
|
||||
2: Global Timer Interrupt 2
|
||||
3: Global Timer Interrupt 3
|
||||
4: Local Timer Interrupt 0
|
||||
5: Local Timer Interrupt 1
|
||||
6: ..
|
||||
7: ..
|
||||
i: Local Timer Interrupt n
|
||||
|
||||
Example 1: In this example, the system uses only the first global timer
|
||||
interrupt generated by MCT and the remaining three global timer
|
||||
interrupts are unused. Two local timer interrupts have been
|
||||
specified.
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
|
||||
<0 42 0>, <0 48 0>;
|
||||
};
|
||||
|
||||
Example 2: In this example, the MCT global and local timer interrupts are
|
||||
connected to two seperate interrupt controllers. Hence, an
|
||||
interrupt-map is created to map the interrupts to the respective
|
||||
interrupt controllers.
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
50
Documentation/devicetree/bindings/usb/exynos-usb.txt
Normal file
50
Documentation/devicetree/bindings/usb/exynos-usb.txt
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
Samsung Exynos SoC USB controller
|
||||
|
||||
The USB devices interface with USB controllers on Exynos SOCs.
|
||||
The device node has following properties.
|
||||
|
||||
EHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ehci" for USB 2.0
|
||||
EHCI controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- clocks: from common clock binding: handle to usb clock.
|
||||
- clock-names: from common clock binding: Shall be "usbhost".
|
||||
|
||||
Optional properties:
|
||||
- samsung,vbus-gpio: if present, specifies the GPIO that
|
||||
needs to be pulled up for the bus to be powered.
|
||||
|
||||
Example:
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
|
||||
clocks = <&clock 285>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
OHCI
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos4210-ohci" for USB 2.0
|
||||
OHCI companion controller in host mode.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- clocks: from common clock binding: handle to usb clock.
|
||||
- clock-names: from common clock binding: Shall be "usbhost".
|
||||
|
||||
Example:
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
|
||||
clocks = <&clock 285>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
65
Documentation/devicetree/bindings/video/samsung-fimd.txt
Normal file
65
Documentation/devicetree/bindings/video/samsung-fimd.txt
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
Device-Tree bindings for Samsung SoC display controller (FIMD)
|
||||
|
||||
FIMD (Fully Interactive Mobile Display) is the Display Controller for the
|
||||
Samsung series of SoCs which transfers the image data from a video memory
|
||||
buffer to an external LCD interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be one of the following
|
||||
"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
|
||||
"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
|
||||
"samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */
|
||||
"samsung,s5pc100-fimd"; /* for S5PC100 SoC */
|
||||
"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
|
||||
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
|
||||
"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
|
||||
|
||||
- reg: physical base address and length of the FIMD registers set.
|
||||
|
||||
- interrupt-parent: should be the phandle of the fimd controller's
|
||||
parent interrupt controller.
|
||||
|
||||
- interrupts: should contain a list of all FIMD IP block interrupts in the
|
||||
order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
|
||||
format depends on the interrupt controller used.
|
||||
|
||||
- interrupt-names: should contain the interrupt names: "fifo", "vsync",
|
||||
"lcd_sys", in the same order as they were listed in the interrupts
|
||||
property.
|
||||
|
||||
- pinctrl-0: pin control group to be used for this controller.
|
||||
|
||||
- pinctrl-names: must contain a "default" entry.
|
||||
|
||||
- clocks: must include clock specifiers corresponding to entries in the
|
||||
clock-names property.
|
||||
|
||||
- clock-names: list of clock names sorted in the same order as the clocks
|
||||
property. Must contain "sclk_fimd" and "fimd".
|
||||
|
||||
Optional Properties:
|
||||
- samsung,power-domain: a phandle to FIMD power domain node.
|
||||
|
||||
Example:
|
||||
|
||||
SoC specific DT entry:
|
||||
|
||||
fimd@11c00000 {
|
||||
compatible = "samsung,exynos4210-fimd";
|
||||
interrupt-parent = <&combiner>;
|
||||
reg = <0x11c00000 0x20000>;
|
||||
interrupt-names = "fifo", "vsync", "lcd_sys";
|
||||
interrupts = <11 0>, <11 1>, <11 2>;
|
||||
clocks = <&clock 140>, <&clock 283>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
samsung,power-domain = <&pd_lcd0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Board specific DT entry:
|
||||
|
||||
fimd@11c00000 {
|
||||
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -769,8 +769,10 @@ config ARCH_SA1100
|
|||
config ARCH_S3C24XX
|
||||
bool "Samsung S3C24XX SoCs"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
@ -787,10 +789,11 @@ config ARCH_S3C64XX
|
|||
bool "Samsung S3C64XX"
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select ARM_VIC
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V6
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
@ -824,9 +827,11 @@ config ARCH_S5P64X0
|
|||
|
||||
config ARCH_S5PC100
|
||||
bool "Samsung S5PC100"
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select HAVE_CLK
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
|
|
@ -859,6 +864,7 @@ config ARCH_EXYNOS
|
|||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
|
|
@ -1656,7 +1662,7 @@ config LOCAL_TIMERS
|
|||
bool "Use local timer interrupts"
|
||||
depends on SMP
|
||||
default y
|
||||
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
|
||||
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
|
||||
help
|
||||
Enable support for local timers on SMP platforms, rather then the
|
||||
legacy IPI broadcast method. Local timers allows the system
|
||||
|
|
|
|||
|
|
@ -42,7 +42,11 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
|||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
|
||||
exynos4210-smdkv310.dtb \
|
||||
exynos4210-trats.dtb \
|
||||
exynos4412-odroidx.dtb \
|
||||
exynos4412-smdk4412.dtb \
|
||||
exynos4412-origen.dtb \
|
||||
exynos5250-arndale.dtb \
|
||||
exynos5440-sd5v1.dtb \
|
||||
exynos5250-smdk5250.dtb \
|
||||
exynos5250-snow.dtb \
|
||||
exynos5440-ssdk5440.dtb
|
||||
|
|
|
|||
|
|
@ -19,31 +19,168 @@
|
|||
chosen {
|
||||
};
|
||||
|
||||
pinctrl@11400000 {
|
||||
/*
|
||||
* Disabled pullups since external part has its own pullups and
|
||||
* double-pulling gets us out of spec in some cases.
|
||||
*/
|
||||
i2c2_bus: i2c2-bus {
|
||||
samsung,pin-pud = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12C60000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <378000>;
|
||||
gpios = <&gpb3 0 2 3 0>,
|
||||
<&gpb3 1 2 3 0>;
|
||||
|
||||
max77686@09 {
|
||||
compatible = "maxim,max77686";
|
||||
reg = <0x09>;
|
||||
|
||||
voltage-regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "P1.0V_LDO_OUT1";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "P1.8V_LDO_OUT2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "P1.8V_LDO_OUT3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "P1.1V_LDO_OUT7";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "P1.0V_LDO_OUT8";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "P1.8V_LDO_OUT10";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "P3.0V_LDO_OUT12";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "P1.8V_LDO_OUT14";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "P1.0V_LDO_OUT15";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "P1.8V_LDO_OUT16";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "P1.8V_BUCK_OUT5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "P1.35V_BUCK_OUT6";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "P2.0V_BUCK_OUT7";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "P2.85V_BUCK_OUT8";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <378000>;
|
||||
gpios = <&gpb3 2 2 3 0>,
|
||||
<&gpb3 3 2 3 0>;
|
||||
};
|
||||
|
||||
i2c@12C80000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <66000>;
|
||||
|
||||
/*
|
||||
* Disabled pullups since external part has its own pullups and
|
||||
* double-pulling gets us out of spec in some cases.
|
||||
*/
|
||||
gpios = <&gpa0 6 3 0 0>,
|
||||
<&gpa0 7 3 0 0>;
|
||||
|
||||
hdmiddc@50 {
|
||||
compatible = "samsung,exynos5-hdmiddc";
|
||||
reg = <0x50>;
|
||||
|
|
@ -53,8 +190,6 @@
|
|||
i2c@12C90000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <66000>;
|
||||
gpios = <&gpa1 2 3 3 0>,
|
||||
<&gpa1 3 3 3 0>;
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
|
|
@ -64,8 +199,6 @@
|
|||
i2c@12CB0000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <66000>;
|
||||
gpios = <&gpa2 2 3 3 0>,
|
||||
<&gpa2 3 3 3 0>;
|
||||
};
|
||||
|
||||
i2c@12CC0000 {
|
||||
|
|
@ -75,8 +208,6 @@
|
|||
i2c@12CD0000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <66000>;
|
||||
gpios = <&gpb2 2 3 3 0>,
|
||||
<&gpb2 3 3 3 0>;
|
||||
};
|
||||
|
||||
i2c@12CE0000 {
|
||||
|
|
@ -98,15 +229,12 @@
|
|||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
|
||||
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
|
||||
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
|
||||
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
|
||||
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -122,15 +250,13 @@
|
|||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
|
||||
wp-gpios = <&gpc2 1 0 0 3>;
|
||||
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
|
||||
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
|
||||
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
|
||||
wp-gpios = <&gpc2 1 0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -143,11 +269,11 @@
|
|||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
/* See board-specific dts files for pin setup */
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
/* See board-specific dts files for GPIOs */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -156,9 +282,6 @@
|
|||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
gpios = <&gpa2 4 2 3 0>,
|
||||
<&gpa2 6 2 3 0>,
|
||||
<&gpa2 7 2 3 0>;
|
||||
samsung,spi-src-clk = <0>;
|
||||
num-cs = <1>;
|
||||
};
|
||||
|
|
@ -168,7 +291,7 @@
|
|||
};
|
||||
|
||||
hdmi {
|
||||
hpd-gpio = <&gpx3 7 0xf 1 3>;
|
||||
hpd-gpio = <&gpx3 7 0>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
|
|
@ -176,7 +299,7 @@
|
|||
|
||||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpx1 3 0 0x10000 0>;
|
||||
gpios = <&gpx1 3 1>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -82,10 +82,17 @@
|
|||
reg = <0x10440000 0x1000>;
|
||||
};
|
||||
|
||||
sys_reg: sysreg {
|
||||
compatible = "samsung,exynos4-sysreg", "syscon";
|
||||
reg = <0x10010000 0x400>;
|
||||
};
|
||||
|
||||
watchdog@10060000 {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 43 0>;
|
||||
clocks = <&clock 345>;
|
||||
clock-names = "watchdog";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -93,6 +100,8 @@
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <0 44 0>, <0 45 0>;
|
||||
clocks = <&clock 346>;
|
||||
clock-names = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -100,6 +109,8 @@
|
|||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100A0000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&clock 347>;
|
||||
clock-names = "keypad";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -107,6 +118,8 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12510000 0x100>;
|
||||
interrupts = <0 73 0>;
|
||||
clocks = <&clock 297>, <&clock 145>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -114,6 +127,8 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12520000 0x100>;
|
||||
interrupts = <0 74 0>;
|
||||
clocks = <&clock 298>, <&clock 146>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -121,6 +136,8 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12530000 0x100>;
|
||||
interrupts = <0 75 0>;
|
||||
clocks = <&clock 299>, <&clock 147>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -128,6 +145,16 @@
|
|||
compatible = "samsung,exynos4210-sdhci";
|
||||
reg = <0x12540000 0x100>;
|
||||
interrupts = <0 76 0>;
|
||||
clocks = <&clock 300>, <&clock 148>;
|
||||
clock-names = "hsmmc", "mmc_busclk.2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mfc: codec@13400000 {
|
||||
compatible = "samsung,mfc-v5";
|
||||
reg = <0x13400000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -135,6 +162,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 312>, <&clock 151>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -142,6 +171,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13810000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 313>, <&clock 152>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -149,6 +180,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -156,6 +189,8 @@
|
|||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13830000 0x100>;
|
||||
interrupts = <0 55 0>;
|
||||
clocks = <&clock 315>, <&clock 154>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -165,6 +200,10 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13860000 0x100>;
|
||||
interrupts = <0 58 0>;
|
||||
clocks = <&clock 317>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -174,6 +213,10 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13870000 0x100>;
|
||||
interrupts = <0 59 0>;
|
||||
clocks = <&clock 318>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -183,6 +226,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13880000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
clocks = <&clock 319>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -192,6 +237,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x13890000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
clocks = <&clock 320>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -201,6 +248,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138A0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
clocks = <&clock 321>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -210,6 +259,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138B0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
clocks = <&clock 322>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -219,6 +270,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138C0000 0x100>;
|
||||
interrupts = <0 64 0>;
|
||||
clocks = <&clock 323>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -228,6 +281,8 @@
|
|||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x138D0000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 324>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -239,6 +294,10 @@
|
|||
rx-dma-channel = <&pdma0 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 327>, <&clock 159>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -250,6 +309,10 @@
|
|||
rx-dma-channel = <&pdma1 6>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 328>, <&clock 160>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -261,6 +324,10 @@
|
|||
rx-dma-channel = <&pdma0 8>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 329>, <&clock 161>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -275,6 +342,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12680000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 292>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -284,6 +353,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12690000 0x1000>;
|
||||
interrupts = <0 36 0>;
|
||||
clocks = <&clock 293>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -293,9 +364,23 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12850000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 279>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
fimd: fimd@11c00000 {
|
||||
compatible = "samsung,exynos4210-fimd";
|
||||
interrupt-parent = <&combiner>;
|
||||
reg = <0x11c00000 0x20000>;
|
||||
interrupt-names = "fifo", "vsync", "lcd_sys";
|
||||
interrupts = <11 0>, <11 1>, <11 2>;
|
||||
clocks = <&clock 140>, <&clock 283>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
samsung,power-domain = <&pd_lcd0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -57,6 +57,16 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
g2d@12800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -121,4 +131,16 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -30,16 +30,19 @@
|
|||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
samsung,sdhci-bus-width = <4>;
|
||||
linux,mmc_cap_4_bit_data;
|
||||
samsung,sdhci-cd-internal;
|
||||
gpio-cd = <&gpk2 2 2 3 3>;
|
||||
gpios = <&gpk2 0 2 0 3>,
|
||||
<&gpk2 1 2 0 3>,
|
||||
<&gpk2 3 2 3 3>,
|
||||
<&gpk2 4 2 3 3>,
|
||||
<&gpk2 5 2 3 3>,
|
||||
<&gpk2 6 2 3 3>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
g2d@12800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -59,25 +62,32 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@11000000 {
|
||||
keypad_rows: keypad-rows {
|
||||
samsung,pins = "gpx2-0", "gpx2-1";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
keypad_cols: keypad-cols {
|
||||
samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
|
||||
"gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
keypad@100A0000 {
|
||||
samsung,keypad-num-rows = <2>;
|
||||
samsung,keypad-num-columns = <8>;
|
||||
linux,keypad-no-autorepeat;
|
||||
linux,keypad-wakeup;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&keypad_rows &keypad_cols>;
|
||||
status = "okay";
|
||||
|
||||
row-gpios = <&gpx2 0 3 3 0>,
|
||||
<&gpx2 1 3 3 0>;
|
||||
|
||||
col-gpios = <&gpx1 0 3 0 0>,
|
||||
<&gpx1 1 3 0 0>,
|
||||
<&gpx1 2 3 0 0>,
|
||||
<&gpx1 3 3 0 0>,
|
||||
<&gpx1 4 3 0 0>,
|
||||
<&gpx1 5 3 0 0>,
|
||||
<&gpx1 6 3 0 0>,
|
||||
<&gpx1 7 3 0 0>;
|
||||
|
||||
key_1 {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <3>;
|
||||
|
|
@ -143,9 +153,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
gpios = <&gpd1 0 2 3 0>,
|
||||
<&gpd1 1 2 3 0>;
|
||||
samsung,i2c-max-bus-freq = <100000>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
|
|
@ -160,9 +168,6 @@
|
|||
};
|
||||
|
||||
spi_2: spi@13940000 {
|
||||
gpios = <&gpc1 1 5 3 0>,
|
||||
<&gpc1 3 5 3 0>,
|
||||
<&gpc1 4 5 3 0>;
|
||||
status = "okay";
|
||||
|
||||
w25x80@0 {
|
||||
|
|
@ -173,7 +178,7 @@
|
|||
spi-max-frequency = <1000000>;
|
||||
|
||||
controller-data {
|
||||
cs-gpio = <&gpc1 2 1 0 3>;
|
||||
cs-gpio = <&gpc1 2 0>;
|
||||
samsung,spi-feedback-delay = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -189,4 +194,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -289,4 +289,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,6 +47,36 @@
|
|||
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &gic 0 69 0>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 0 42 0>,
|
||||
<0x5 0 &gic 0 48 0>;
|
||||
};
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4210-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4210-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
|
@ -76,4 +106,11 @@
|
|||
reg = <0x100C0000 0x100>;
|
||||
interrupts = <2 4>;
|
||||
};
|
||||
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,4 +25,26 @@
|
|||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x8000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
109
arch/arm/boot/dts/exynos4412-odroidx.dts
Normal file
109
arch/arm/boot/dts/exynos4412-odroidx.dts
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Hardkernel's Exynos4412 based ODROID-X board device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
|
||||
*
|
||||
* Device tree source file for Hardkernel's ODROID-X board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Hardkernel ODROID-X board based on Exynos4412";
|
||||
compatible = "hardkernel,odroid-x", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led1 {
|
||||
label = "led1:heart";
|
||||
gpios = <&gpc1 0 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led2 {
|
||||
label = "led2:mmc0";
|
||||
gpios = <&gpc1 2 1>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator_p3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "p3v3_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpa1 1 1>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
rtc@10070000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
451
arch/arm/boot/dts/exynos4412-origen.dts
Normal file
451
arch/arm/boot/dts/exynos4412-origen.dts
Normal file
|
|
@ -0,0 +1,451 @@
|
|||
/*
|
||||
* Insignal's Exynos4412 based Origen board device tree source
|
||||
*
|
||||
* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Device tree source file for Insignal's Origen board which is based on
|
||||
* Samsung's Exynos4412 SoC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Origen evaluation board based on Exynos4412";
|
||||
compatible = "insignal,origen4412", "samsung,exynos4412";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs ="console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
mmc_reg: voltage-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VMEM_VDD_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpx1 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&mmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mshc@12550000 {
|
||||
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fimd@11c00000 {
|
||||
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing {
|
||||
clock-frequency = <50000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hfront-porch = <64>;
|
||||
hback-porch = <16>;
|
||||
hsync-len = <48>;
|
||||
vback-porch = <64>;
|
||||
vfront-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13820000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@13860000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
s5m8767_pmic@66 {
|
||||
compatible = "samsung,s5m8767-pmic";
|
||||
reg = <0x66>;
|
||||
|
||||
s5m8767,pmic-buck-default-dvs-idx = <3>;
|
||||
|
||||
s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
|
||||
<&gpx2 4 0>,
|
||||
<&gpx2 5 0>;
|
||||
|
||||
s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
|
||||
<&gpm3 6 0>,
|
||||
<&gpm3 7 0>;
|
||||
|
||||
s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>,
|
||||
<1100000>, <1100000>;
|
||||
|
||||
s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>,
|
||||
<1200000>, <1200000>;
|
||||
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "VDD_ALIVE";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VDDQ_M12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "VDDIOAP_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "VDDQ_PRE";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "VDD18_2M";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "VDD10_MPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "VDD10_XPLL";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "VDD10_MIPI";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
regulator-name = "VDD33_LCD";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "VDD18_MIPI";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD18_ABB1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "VDD33_UOTG";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "VDDIOPERI_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "VDD18_ABB02";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "VDD10_USH";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "VDD18_HSIC";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "VDDIOAP_MMC012_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo18_reg: LDO18 {
|
||||
regulator-name = "VDDIOPERI_28";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo19_reg: LDO19 {
|
||||
regulator-name = "DVDD25";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo20_reg: LDO20 {
|
||||
regulator-name = "VDD28_CAM";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "VDD28_AF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo22_reg: LDO22 {
|
||||
regulator-name = "VDDA28_2M";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo23_reg: LDO23 {
|
||||
regulator-name = "VDD28_TF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo24_reg: LDO24 {
|
||||
regulator-name = "VDD33_A31";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "VDD18_CAM";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo26_reg: LDO26 {
|
||||
regulator-name = "VDD18_A31";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo27_reg: LDO27 {
|
||||
regulator-name = "GPS_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
ldo28_reg: LDO28 {
|
||||
regulator-name = "DVDD12";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "vdd_m12";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "vdd12_5m";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
|
||||
buck9_reg: BUCK9 {
|
||||
regulator-name = "vddf28_emmc";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>; /* Normal Mode */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -27,6 +27,27 @@
|
|||
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
|
||||
};
|
||||
|
||||
g2d@10800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
g2d@10800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@12530000 {
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
codec@13400000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -42,4 +63,16 @@
|
|||
serial@13830000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
xusbxti {
|
||||
compatible = "samsung,clock-xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,4 +25,30 @@
|
|||
gic:interrupt-controller@10490000 {
|
||||
cpu-offset = <0x4000>;
|
||||
};
|
||||
|
||||
mct@10050000 {
|
||||
compatible = "samsung,exynos4412-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>, <6 0>, <7 0>;
|
||||
clocks = <&clock 3>, <&clock 344>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &gic 0 57 0>,
|
||||
<0x1 0 &combiner 12 5>,
|
||||
<0x2 0 &combiner 12 6>,
|
||||
<0x3 0 &combiner 12 7>,
|
||||
<0x4 0 &gic 1 12 0>,
|
||||
<0x5 0 &gic 1 12 0>,
|
||||
<0x6 0 &gic 1 12 0>,
|
||||
<0x7 0 &gic 1 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -36,6 +36,12 @@
|
|||
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10030000 {
|
||||
compatible = "samsung,exynos4412-clock";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos4x12-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
|
|
@ -66,4 +72,11 @@
|
|||
reg = <0x106E0000 0x1000>;
|
||||
interrupts = <0 72 0>;
|
||||
};
|
||||
|
||||
g2d@10800000 {
|
||||
compatible = "samsung,exynos4212-g2d";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
452
arch/arm/boot/dts/exynos5250-arndale.dts
Normal file
452
arch/arm/boot/dts/exynos5250-arndale.dts
Normal file
|
|
@ -0,0 +1,452 @@
|
|||
/*
|
||||
* Samsung's Exynos5250 based Arndale board device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5250.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Insignal Arndale evaluation board based on EXYNOS5250";
|
||||
compatible = "insignal,arndale", "samsung,exynos5250";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySAC2,115200";
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
samsung,mfc-r = <0x43000000 0x800000>;
|
||||
samsung,mfc-l = <0x51000000 0x800000>;
|
||||
};
|
||||
|
||||
i2c@12C60000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
samsung,i2c-slave-addr = <0x66>;
|
||||
|
||||
s5m8767_pmic@66 {
|
||||
compatible = "samsung,s5m8767-pmic";
|
||||
reg = <0x66>;
|
||||
|
||||
s5m8767,pmic-buck2-dvs-voltage = <1300000>;
|
||||
s5m8767,pmic-buck3-dvs-voltage = <1100000>;
|
||||
s5m8767,pmic-buck4-dvs-voltage = <1200000>;
|
||||
s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>,
|
||||
<&gpd1 1 0>,
|
||||
<&gpd1 2 0>;
|
||||
s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>,
|
||||
<&gpx2 4 0>,
|
||||
<&gpx2 5 0>;
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "VDD_ALIVE_1.0V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "VDD_28IO_DP_1.35V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "VDD_COMMON1_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "VDD_IOPERI_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "VDD_EXT_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "VDD_MPLL_1.1V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "VDD_XPLL_1.1V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "VDD_COMMON2_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
regulator-name = "VDD_33ON_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "VDD_COMMON3_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD_ABB2_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "VDD_USB_3.0V";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "VDDQ_C2C_W_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "VDD18_ABB0_3_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "VDD10_COMMON4_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo16_reg: LDO16 {
|
||||
regulator-name = "VDD18_HSIC_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "VDDQ_MMC2_3_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo18_reg: LDO18 {
|
||||
regulator-name = "VDD_33ON_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo22_reg: LDO22 {
|
||||
regulator-name = "EXT_33_OFF";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo23_reg: LDO23 {
|
||||
regulator-name = "EXT_28_OFF";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "PVDD_LDO25";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
ldo26_reg: LDO26 {
|
||||
regulator-name = "EXT_18_OFF";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "VDD_MEM_1.35V";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1355000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
op_mode = <1>;
|
||||
};
|
||||
|
||||
buck9_reg: BUCK9 {
|
||||
regulator-name = "VDD_33_OFF_EXT1";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
op_mode = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12C70000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C80000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12C90000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CB0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CC0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CD0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
vmmc-supply = <&mmc_reg>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
fifo-depth = <0x80>;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
vmmc-supply = <&mmc_reg>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
};
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
menu {
|
||||
label = "SW-TACT2";
|
||||
gpios = <&gpx1 4 1>;
|
||||
linux,code = <139>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
home {
|
||||
label = "SW-TACT3";
|
||||
gpios = <&gpx1 5 1>;
|
||||
linux,code = <102>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
up {
|
||||
label = "SW-TACT4";
|
||||
gpios = <&gpx1 6 1>;
|
||||
linux,code = <103>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
down {
|
||||
label = "SW-TACT5";
|
||||
gpios = <&gpx1 7 1>;
|
||||
linux,code = <108>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "SW-TACT6";
|
||||
gpios = <&gpx2 0 1>;
|
||||
linux,code = <158>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
wakeup {
|
||||
label = "SW-TACT7";
|
||||
gpios = <&gpx2 1 1>;
|
||||
linux,code = <143>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
hpd-gpio = <&gpx3 7 2>;
|
||||
vdd_osc-supply = <&ldo10_reg>;
|
||||
vdd_pll-supply = <&ldo8_reg>;
|
||||
vdd-supply = <&ldo8_reg>;
|
||||
};
|
||||
|
||||
mmc_reg: voltage-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_33ON_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpx1 1 1>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_hdmi_en: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hdmi-en";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
783
arch/arm/boot/dts/exynos5250-pinctrl.dtsi
Normal file
783
arch/arm/boot/dts/exynos5250-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,783 @@
|
|||
/*
|
||||
* Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
|
||||
* tree nodes are listed in this file.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
pinctrl@11400000 {
|
||||
gpa0: gpa0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa1: gpa1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa2: gpa2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb0: gpb0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb1: gpb1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb2: gpb2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb3: gpb3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc0: gpc0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc1: gpc1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc2: gpc2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc3: gpc3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd0: gpd0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd1: gpd1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpy0: gpy0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy1: gpy1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy2: gpy2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy3: gpy3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy4: gpy4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy5: gpy5 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy6: gpy6 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpc4: gpc4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpx0: gpx0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&combiner>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
|
||||
<26 0>, <26 1>, <27 0>, <27 1>;
|
||||
};
|
||||
|
||||
gpx1: gpx1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&combiner>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
|
||||
<30 0>, <30 1>, <31 0>, <31 1>;
|
||||
};
|
||||
|
||||
gpx2: gpx2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpx3: gpx3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart0_data: uart0-data {
|
||||
samsung,pins = "gpa0-0", "gpa0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
uart0_fctl: uart0-fctl {
|
||||
samsung,pins = "gpa0-2", "gpa0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c2_bus: i2c2-bus {
|
||||
samsung,pins = "gpa0-6", "gpa0-7";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c2_hs_bus: i2c2-hs-bus {
|
||||
samsung,pins = "gpa0-6", "gpa0-7";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
uart2_data: uart2-data {
|
||||
samsung,pins = "gpa1-0", "gpa1-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
uart2_fctl: uart2-fctl {
|
||||
samsung,pins = "gpa1-2", "gpa1-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c3_bus: i2c3-bus {
|
||||
samsung,pins = "gpa1-2", "gpa1-3";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c3_hs_bus: i2c3-hs-bus {
|
||||
samsung,pins = "gpa1-2", "gpa1-3";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
uart3_data: uart3-data {
|
||||
samsung,pins = "gpa1-4", "gpa1-4";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
spi0_bus: spi0-bus {
|
||||
samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c4_bus: i2c4-bus {
|
||||
samsung,pins = "gpa2-0", "gpa2-1";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c5_bus: i2c5-bus {
|
||||
samsung,pins = "gpa2-2", "gpa2-3";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
spi1_bus: spi1-bus {
|
||||
samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2s1_bus: i2s1-bus {
|
||||
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
|
||||
"gpb0-4";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pcm1_bus: pcm1-bus {
|
||||
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
|
||||
"gpb0-4";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
ac97_bus: ac97-bus {
|
||||
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
|
||||
"gpb0-4";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2s2_bus: i2s2-bus {
|
||||
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
|
||||
"gpb1-4";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
pcm2_bus: pcm2-bus {
|
||||
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
|
||||
"gpb1-4";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
spdif_bus: spdif-bus {
|
||||
samsung,pins = "gpb1-0", "gpb1-1";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
spi2_bus: spi2-bus {
|
||||
samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
|
||||
samsung,pin-function = <5>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c6_bus: i2c6-bus {
|
||||
samsung,pins = "gpb1-3", "gpb1-4";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c7_bus: i2c7-bus {
|
||||
samsung,pins = "gpb2-2", "gpb2-3";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c0_bus: i2c0-bus {
|
||||
samsung,pins = "gpb3-0", "gpb3-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c1_bus: i2c1-bus {
|
||||
samsung,pins = "gpb3-2", "gpb3-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c0_hs_bus: i2c0-hs-bus {
|
||||
samsung,pins = "gpb3-0", "gpb3-1";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c1_hs_bus: i2c1-hs-bus {
|
||||
samsung,pins = "gpb3-2", "gpb3-3";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
sd0_clk: sd0-clk {
|
||||
samsung,pins = "gpc0-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd0_cmd: sd0-cmd {
|
||||
samsung,pins = "gpc0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd0_cd: sd0-cd {
|
||||
samsung,pins = "gpc0-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd0_bus1: sd0-bus-width1 {
|
||||
samsung,pins = "gpc0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd0_bus4: sd0-bus-width4 {
|
||||
samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd0_bus8: sd0-bus-width8 {
|
||||
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd1_clk: sd1-clk {
|
||||
samsung,pins = "gpc2-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd1_cmd: sd1-cmd {
|
||||
samsung,pins = "gpc2-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd1_cd: sd1-cd {
|
||||
samsung,pins = "gpc2-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd1_bus1: sd1-bus-width1 {
|
||||
samsung,pins = "gpc2-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd1_bus4: sd1-bus-width4 {
|
||||
samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_clk: sd2-clk {
|
||||
samsung,pins = "gpc3-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_cmd: sd2-cmd {
|
||||
samsung,pins = "gpc3-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_cd: sd2-cd {
|
||||
samsung,pins = "gpc3-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_bus1: sd2-bus-width1 {
|
||||
samsung,pins = "gpc3-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_bus4: sd2-bus-width4 {
|
||||
samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_bus8: sd2-bus-width8 {
|
||||
samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd3_clk: sd3-clk {
|
||||
samsung,pins = "gpc4-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd3_cmd: sd3-cmd {
|
||||
samsung,pins = "gpc4-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd3_cd: sd3-cd {
|
||||
samsung,pins = "gpc4-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd3_bus1: sd3-bus-width1 {
|
||||
samsung,pins = "gpc4-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd3_bus4: sd3-bus-width4 {
|
||||
samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
uart1_data: uart1-data {
|
||||
samsung,pins = "gpd0-0", "gpd0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
uart1_fctl: uart1-fctl {
|
||||
samsung,pins = "gpd0-2", "gpd0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@13400000 {
|
||||
gpe0: gpe0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe1: gpe1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf0: gpf0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf1: gpf1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg0: gpg0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg1: gpg1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg2: gpg2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gph0: gph0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gph1: gph1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
cam_gpio_a: cam-gpio-a {
|
||||
samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
|
||||
"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
|
||||
"gpe1-0", "gpe1-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_gpio_b: cam-gpio-b {
|
||||
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
|
||||
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_i2c2_bus: cam-i2c2-bus {
|
||||
samsung,pins = "gpe0-6", "gpe1-0";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_spi1_bus: cam-spi1-bus {
|
||||
samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
|
||||
samsung,pin-function = <4>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_i2c1_bus: cam-i2c1-bus {
|
||||
samsung,pins = "gpf0-2", "gpf0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_i2c0_bus: cam-i2c0-bus {
|
||||
samsung,pins = "gpf0-0", "gpf0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_spi0_bus: cam-spi0-bus {
|
||||
samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_bayrgb_bus: cam-bayrgb-bus {
|
||||
samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
|
||||
"gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
|
||||
"gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
|
||||
"gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
|
||||
"gpg2-0", "gpg2-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
cam_port_a: cam-port-a {
|
||||
samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3",
|
||||
"gph1-0", "gph1-1", "gph1-2", "gph1-3",
|
||||
"gph1-4", "gph1-5", "gph1-6", "gph1-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@10d10000 {
|
||||
gpv0: gpv0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv1: gpv1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv2: gpv2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv3: gpv3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv4: gpv4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
c2c_rxd: c2c-rxd {
|
||||
samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
|
||||
"gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
|
||||
"gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
|
||||
"gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
c2c_txd: c2c-txd {
|
||||
samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
|
||||
"gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
|
||||
"gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
|
||||
"gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samaung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@03680000 {
|
||||
gpz: gpz {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
i2s0_bus: i2s0-bus {
|
||||
samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
|
||||
"gpz-4", "gpz-5", "gpz-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -30,8 +30,6 @@
|
|||
i2c@12C60000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
gpios = <&gpb3 0 2 3 0>,
|
||||
<&gpb3 1 2 3 0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "samsung,s524ad0xd1";
|
||||
|
|
@ -42,8 +40,6 @@
|
|||
i2c@12C70000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <20000>;
|
||||
gpios = <&gpb3 2 2 3 0>,
|
||||
<&gpb3 3 2 3 0>;
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "samsung,s524ad0xd1";
|
||||
|
|
@ -74,8 +70,6 @@
|
|||
i2c@12C80000 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <66000>;
|
||||
gpios = <&gpa0 6 3 3 0>,
|
||||
<&gpa0 7 3 3 0>;
|
||||
|
||||
hdmiddc@50 {
|
||||
compatible = "samsung,exynos5-hdmiddc";
|
||||
|
|
@ -122,15 +116,12 @@
|
|||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
|
||||
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
|
||||
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
|
||||
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
|
||||
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -146,17 +137,13 @@
|
|||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
|
||||
disable-wp;
|
||||
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
|
||||
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
|
||||
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
|
||||
<&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
|
||||
<&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -169,10 +156,6 @@
|
|||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
gpios = <&gpa2 4 2 3 0>,
|
||||
<&gpa2 6 2 3 0>,
|
||||
<&gpa2 7 2 3 0>;
|
||||
|
||||
w25q80bw@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -181,7 +164,7 @@
|
|||
spi-max-frequency = <1000000>;
|
||||
|
||||
controller-data {
|
||||
cs-gpio = <&gpa2 5 1 0 3>;
|
||||
cs-gpio = <&gpa2 5 0>;
|
||||
samsung,spi-feedback-delay = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -203,7 +186,7 @@
|
|||
};
|
||||
|
||||
hdmi {
|
||||
hpd-gpio = <&gpx3 7 0xf 1 3>;
|
||||
hpd-gpio = <&gpx3 7 0>;
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
|
|
@ -212,9 +195,7 @@
|
|||
};
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>,
|
||||
<&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>,
|
||||
<&gpz 6 2 0 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2s1: i2s@12D60000 {
|
||||
|
|
@ -231,4 +212,40 @@
|
|||
samsung,i2s-controller = <&i2s0>;
|
||||
samsung,audio-codec = <&wm8994>;
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing@0 {
|
||||
/* 1280x800 */
|
||||
clock-frequency = <50000>;
|
||||
hactive = <1280>;
|
||||
vactive = <800>;
|
||||
hfront-porch = <4>;
|
||||
hback-porch = <4>;
|
||||
hsync-len = <4>;
|
||||
vback-porch = <4>;
|
||||
vfront-porch = <4>;
|
||||
vsync-len = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,12 +16,27 @@
|
|||
model = "Google Snow";
|
||||
compatible = "google,snow", "samsung,exynos5250";
|
||||
|
||||
pinctrl@11400000 {
|
||||
sd3_clk: sd3-clk {
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
sd3_cmd: sd3-cmd {
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
sd3_bus4: sd3-bus-width4 {
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
lid-switch {
|
||||
label = "Lid";
|
||||
gpios = <&gpx3 5 0 0x10000 0>;
|
||||
gpios = <&gpx3 5 1>;
|
||||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0>; /* SW_LID */
|
||||
debounce-interval = <1>;
|
||||
|
|
@ -35,9 +50,19 @@
|
|||
*/
|
||||
dwmmc3@12230000 {
|
||||
slot@0 {
|
||||
gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
|
||||
<&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
|
||||
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
samsung,vbus-gpio = <&gpx1 1 1 3 3>;
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xxti {
|
||||
compatible = "samsung,clock-xxti";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/include/ "exynos5250-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos5250";
|
||||
|
|
@ -44,13 +45,45 @@
|
|||
i2c6 = &i2c_6;
|
||||
i2c7 = &i2c_7;
|
||||
i2c8 = &i2c_8;
|
||||
pinctrl0 = &pinctrl_0;
|
||||
pinctrl1 = &pinctrl_1;
|
||||
pinctrl2 = &pinctrl_2;
|
||||
pinctrl3 = &pinctrl_3;
|
||||
};
|
||||
|
||||
pd_gsc: gsc-power-domain@0x10044000 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
};
|
||||
|
||||
pd_mfc: mfc-power-domain@0x10044040 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044040 0x20>;
|
||||
};
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@10481000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
|
||||
reg = <0x10481000 0x1000>,
|
||||
<0x10482000 0x1000>,
|
||||
<0x10484000 0x2000>,
|
||||
<0x10486000 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
combiner:interrupt-controller@10440000 {
|
||||
|
|
@ -69,58 +102,129 @@
|
|||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
|
||||
};
|
||||
|
||||
mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0x800>;
|
||||
interrupt-controller;
|
||||
#interrups-cells = <2>;
|
||||
interrupt-parent = <&mct_map>;
|
||||
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
||||
<4 0>, <5 0>;
|
||||
clocks = <&clock 1>, <&clock 335>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
|
||||
mct_map: mct-map {
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0x0 0 &combiner 23 3>,
|
||||
<0x1 0 &combiner 23 4>,
|
||||
<0x2 0 &combiner 25 2>,
|
||||
<0x3 0 &combiner 25 3>,
|
||||
<0x4 0 &gic 0 120 0>,
|
||||
<0x5 0 &gic 0 121 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,exynos5250-pinctrl";
|
||||
reg = <0x11400000 0x1000>;
|
||||
interrupts = <0 46 0>;
|
||||
|
||||
wakup_eint: wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos4210-wakeup-eint";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 32 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_1: pinctrl@13400000 {
|
||||
compatible = "samsung,exynos5250-pinctrl";
|
||||
reg = <0x13400000 0x1000>;
|
||||
interrupts = <0 45 0>;
|
||||
};
|
||||
|
||||
pinctrl_2: pinctrl@10d10000 {
|
||||
compatible = "samsung,exynos5250-pinctrl";
|
||||
reg = <0x10d10000 0x1000>;
|
||||
interrupts = <0 50 0>;
|
||||
};
|
||||
|
||||
pinctrl_3: pinctrl@03680000 {
|
||||
compatible = "samsung,exynos5250-pinctrl";
|
||||
reg = <0x0368000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&clock 336>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
compatible = "samsung,mfc-v6";
|
||||
reg = <0x11000000 0x10000>;
|
||||
interrupts = <0 96 0>;
|
||||
samsung,power-domain = <&pd_mfc>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x101E0000 0x100>;
|
||||
interrupts = <0 43 0>, <0 44 0>;
|
||||
clocks = <&clock 337>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
tmu@10060000 {
|
||||
compatible = "samsung,exynos5250-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock 338>;
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
clocks = <&clock 289>, <&clock 146>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C10000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C10000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
clocks = <&clock 290>, <&clock 147>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C20000 0x100>;
|
||||
interrupts = <0 53 0>;
|
||||
clocks = <&clock 291>, <&clock 148>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@12C30000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C30000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 292>, <&clock 149>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
sata@122F0000 {
|
||||
compatible = "samsung,exynos5-sata-ahci";
|
||||
reg = <0x122F0000 0x1ff>;
|
||||
interrupts = <0 115 0>;
|
||||
clocks = <&clock 277>, <&clock 143>;
|
||||
clock-names = "sata", "sclk_sata";
|
||||
};
|
||||
|
||||
sata-phy@12170000 {
|
||||
|
|
@ -134,6 +238,10 @@
|
|||
interrupts = <0 56 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 294>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_bus>;
|
||||
};
|
||||
|
||||
i2c_1: i2c@12C70000 {
|
||||
|
|
@ -142,6 +250,10 @@
|
|||
interrupts = <0 57 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 295>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_bus>;
|
||||
};
|
||||
|
||||
i2c_2: i2c@12C80000 {
|
||||
|
|
@ -150,6 +262,10 @@
|
|||
interrupts = <0 58 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 296>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_bus>;
|
||||
};
|
||||
|
||||
i2c_3: i2c@12C90000 {
|
||||
|
|
@ -158,6 +274,10 @@
|
|||
interrupts = <0 59 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 297>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_bus>;
|
||||
};
|
||||
|
||||
i2c_4: i2c@12CA0000 {
|
||||
|
|
@ -166,6 +286,10 @@
|
|||
interrupts = <0 60 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 298>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_bus>;
|
||||
};
|
||||
|
||||
i2c_5: i2c@12CB0000 {
|
||||
|
|
@ -174,6 +298,10 @@
|
|||
interrupts = <0 61 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 299>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_bus>;
|
||||
};
|
||||
|
||||
i2c_6: i2c@12CC0000 {
|
||||
|
|
@ -182,6 +310,10 @@
|
|||
interrupts = <0 62 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 300>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_bus>;
|
||||
};
|
||||
|
||||
i2c_7: i2c@12CD0000 {
|
||||
|
|
@ -190,6 +322,10 @@
|
|||
interrupts = <0 63 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 301>;
|
||||
clock-names = "i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7_bus>;
|
||||
};
|
||||
|
||||
i2c_8: i2c@12CE0000 {
|
||||
|
|
@ -198,6 +334,8 @@
|
|||
interrupts = <0 64 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 302>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@121D0000 {
|
||||
|
|
@ -205,6 +343,8 @@
|
|||
reg = <0x121D0000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 288>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
spi_0: spi@12d20000 {
|
||||
|
|
@ -216,6 +356,10 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 304>, <&clock 154>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_bus>;
|
||||
};
|
||||
|
||||
spi_1: spi@12d30000 {
|
||||
|
|
@ -227,6 +371,10 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 305>, <&clock 155>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_bus>;
|
||||
};
|
||||
|
||||
spi_2: spi@12d40000 {
|
||||
|
|
@ -238,6 +386,10 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 306>, <&clock 156>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_bus>;
|
||||
};
|
||||
|
||||
dwmmc_0: dwmmc0@12200000 {
|
||||
|
|
@ -246,6 +398,8 @@
|
|||
interrupts = <0 75 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 280>, <&clock 139>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_1: dwmmc1@12210000 {
|
||||
|
|
@ -254,6 +408,8 @@
|
|||
interrupts = <0 76 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 281>, <&clock 140>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_2: dwmmc2@12220000 {
|
||||
|
|
@ -262,6 +418,8 @@
|
|||
interrupts = <0 77 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 282>, <&clock 141>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
dwmmc_3: dwmmc3@12230000 {
|
||||
|
|
@ -270,6 +428,8 @@
|
|||
interrupts = <0 78 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 283>, <&clock 142>;
|
||||
clock-names = "biu", "ciu";
|
||||
};
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
|
|
@ -283,6 +443,8 @@
|
|||
samsung,supports-rstclr;
|
||||
samsung,supports-secdai;
|
||||
samsung,idma-addr = <0x03000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_bus>;
|
||||
};
|
||||
|
||||
i2s1: i2s@12D60000 {
|
||||
|
|
@ -291,6 +453,8 @@
|
|||
dmas = <&pdma1 12
|
||||
&pdma1 11>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1_bus>;
|
||||
};
|
||||
|
||||
i2s2: i2s@12D70000 {
|
||||
|
|
@ -299,6 +463,26 @@
|
|||
dmas = <&pdma0 12
|
||||
&pdma0 11>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s2_bus>;
|
||||
};
|
||||
|
||||
usb@12110000 {
|
||||
compatible = "samsung,exynos4210-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
|
||||
clocks = <&clock 285>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
usb@12120000 {
|
||||
compatible = "samsung,exynos4210-ohci";
|
||||
reg = <0x12120000 0x100>;
|
||||
interrupts = <0 71 0>;
|
||||
|
||||
clocks = <&clock 285>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
amba {
|
||||
|
|
@ -312,6 +496,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121A0000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&clock 275>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -321,6 +507,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121B0000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
clocks = <&clock 276>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -330,6 +518,8 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
|
|
@ -339,287 +529,58 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x11C10000 0x1000>;
|
||||
interrupts = <0 124 0>;
|
||||
clocks = <&clock 271>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-controllers {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
gpio-controller;
|
||||
ranges;
|
||||
|
||||
gpa0: gpio-controller@11400000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpa1: gpio-controller@11400020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpa2: gpio-controller@11400040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb0: gpio-controller@11400060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb1: gpio-controller@11400080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb2: gpio-controller@114000A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb3: gpio-controller@114000C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc0: gpio-controller@114000E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc1: gpio-controller@11400100 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400100 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc2: gpio-controller@11400120 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400120 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc3: gpio-controller@11400140 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400140 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc4: gpio-controller@114002E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114002E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpd0: gpio-controller@11400160 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400160 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpd1: gpio-controller@11400180 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400180 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy0: gpio-controller@114001A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy1: gpio-controller@114001C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy2: gpio-controller@114001E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy3: gpio-controller@11400200 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400200 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy4: gpio-controller@11400220 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400220 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy5: gpio-controller@11400240 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400240 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy6: gpio-controller@11400260 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400260 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx0: gpio-controller@11400C00 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C00 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx1: gpio-controller@11400C20 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C20 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx2: gpio-controller@11400C40 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C40 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx3: gpio-controller@11400C60 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400C60 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe0: gpio-controller@13400000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe1: gpio-controller@13400020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf0: gpio-controller@13400040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf1: gpio-controller@13400060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg0: gpio-controller@13400080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg1: gpio-controller@134000A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpg2: gpio-controller@134000C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gph0: gpio-controller@134000E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x134000E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gph1: gpio-controller@13400100 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x13400100 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv0: gpio-controller@10D10000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv1: gpio-controller@10D10020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv2: gpio-controller@10D10040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv3: gpio-controller@10D10060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D10080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpv4: gpio-controller@10D10080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x10D100C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpz: gpio-controller@03860000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x03860000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gsc_0: gsc@0x13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 256>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_1: gsc@0x13e10000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e10000 0x1000>;
|
||||
interrupts = <0 86 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 257>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_2: gsc@0x13e20000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e20000 0x1000>;
|
||||
interrupts = <0 87 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 258>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
gsc_3: gsc@0x13e30000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e30000 0x1000>;
|
||||
interrupts = <0 88 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock 259>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
hdmi {
|
||||
compatible = "samsung,exynos5-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock 333>, <&clock 136>, <&clock 137>,
|
||||
<&clock 333>, <&clock 333>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
||||
"sclk_hdmiphy", "hdmiphy";
|
||||
};
|
||||
|
||||
mixer {
|
||||
|
|
@ -627,4 +588,28 @@
|
|||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
};
|
||||
|
||||
dp-controller {
|
||||
compatible = "samsung,exynos5-dp";
|
||||
reg = <0x145b0000 0x1000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dptx-phy {
|
||||
reg = <0x10040720>;
|
||||
samsung,enable-mask = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
fimd {
|
||||
compatible = "samsung,exynos5250-fimd";
|
||||
interrupt-parent = <&combiner>;
|
||||
reg = <0x14400000 0x40000>;
|
||||
interrupt-names = "fifo", "vsync", "lcd_sys";
|
||||
interrupts = <18 4>, <18 5>, <18 6>;
|
||||
clocks = <&clock 133>, <&clock 339>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
39
arch/arm/boot/dts/exynos5440-sd5v1.dts
Normal file
39
arch/arm/boot/dts/exynos5440-sd5v1.dts
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* SAMSUNG SD5v1 board device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5440.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SAMSUNG SD5v1 board based on EXYNOS5440";
|
||||
compatible = "samsung,sd5v1", "samsung,exynos5440";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
|
||||
};
|
||||
|
||||
fixed-rate-clocks {
|
||||
xtal {
|
||||
compatible = "samsung,clock-xtal";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac: ethernet@00230000 {
|
||||
fixed_phy;
|
||||
phy_addr = <1>;
|
||||
};
|
||||
|
||||
spi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -16,31 +16,18 @@
|
|||
model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
|
||||
compatible = "samsung,ssdk5440", "samsung,exynos5440";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
|
||||
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
|
||||
};
|
||||
|
||||
spi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@F0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc {
|
||||
status = "disabled";
|
||||
fixed-rate-clocks {
|
||||
xtal {
|
||||
compatible = "samsung,clock-xtal";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,63 +16,89 @@
|
|||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
clock: clock-controller@0x160000 {
|
||||
compatible = "samsung,exynos5440-clock";
|
||||
reg = <0x160000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic:interrupt-controller@2E0000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
|
||||
reg = <0x2E1000 0x1000>,
|
||||
<0x2E2000 0x1000>,
|
||||
<0x2E4000 0x2000>,
|
||||
<0x2E6000 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
common {
|
||||
compatible = "samsung,exynos5440";
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
|
||||
interrupts = <0 52 4>,
|
||||
<0 53 4>,
|
||||
<0 54 4>,
|
||||
<0 55 4>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,cortex-a15-timer",
|
||||
"arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
cpufreq@160000 {
|
||||
compatible = "samsung,exynos5440-cpufreq";
|
||||
reg = <0x160000 0x1000>;
|
||||
interrupts = <0 57 0>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
1200000 1025000
|
||||
1000000 975000
|
||||
800000 925000
|
||||
>;
|
||||
};
|
||||
|
||||
serial@B0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <0 2 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
serial@C0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xC0000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
clocks = <&clock 21>, <&clock 21>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
spi {
|
||||
|
|
@ -83,11 +109,15 @@
|
|||
rx-dma-channel = <&pdma0 4>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>, <&clock 16>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
compatible = "samsung,exynos5440-pinctrl";
|
||||
reg = <0xE0000 0x1000>;
|
||||
interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
|
||||
<0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -110,25 +140,42 @@
|
|||
};
|
||||
|
||||
i2c@F0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0xF0000 0x1000>;
|
||||
interrupts = <0 5 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
compatible = "samsung,exynos5440-i2c";
|
||||
reg = <0x100000 0x1000>;
|
||||
interrupts = <0 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "i2c";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <0 1 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
gmac: ethernet@00230000 {
|
||||
compatible = "snps,dwmac-3.70a";
|
||||
reg = <0x00230000 0x8000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 31 4>;
|
||||
interrupt-names = "macirq";
|
||||
phy-mode = "sgmii";
|
||||
clocks = <&clock 25>;
|
||||
clock-names = "stmmaceth";
|
||||
};
|
||||
|
||||
amba {
|
||||
|
|
@ -138,19 +185,23 @@
|
|||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
pdma0: pdma@121A0000 {
|
||||
pdma0: pdma@00121000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 46 0>;
|
||||
clocks = <&clock 8>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
|
||||
pdma1: pdma@121B0000 {
|
||||
pdma1: pdma@00120000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
clocks = <&clock 8>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
|
|
@ -161,5 +212,7 @@
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <0 17 0>, <0 16 0>;
|
||||
clocks = <&clock 21>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ config SOC_EXYNOS5250
|
|||
bool "SAMSUNG EXYNOS5250"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
select S5P_DEV_MFC
|
||||
|
|
@ -79,12 +80,6 @@ config SOC_EXYNOS5440
|
|||
help
|
||||
Enable EXYNOS5440 SoC support
|
||||
|
||||
config EXYNOS4_MCT
|
||||
bool
|
||||
default y
|
||||
help
|
||||
Use MCT (Multi Core Timer) as kernel timers
|
||||
|
||||
config EXYNOS_DEV_DMA
|
||||
bool
|
||||
help
|
||||
|
|
@ -276,8 +271,8 @@ config MACH_UNIVERSAL_C210
|
|||
select S5P_DEV_ONENAND
|
||||
select S5P_DEV_TV
|
||||
select S5P_GPIO_INT
|
||||
select S5P_HRT
|
||||
select S5P_SETUP_MIPIPHY
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board.
|
||||
|
|
@ -406,10 +401,12 @@ config MACH_EXYNOS4_DT
|
|||
bool "Samsung Exynos4 Machine using device tree"
|
||||
depends on ARCH_EXYNOS4
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select CPU_EXYNOS4210
|
||||
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
|
||||
select PINCTRL
|
||||
select PINCTRL_EXYNOS
|
||||
select S5P_DEV_MFC
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung Exynos4 machine with device tree enabled.
|
||||
|
|
@ -422,6 +419,7 @@ config MACH_EXYNOS5_DT
|
|||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung EXYNOS5 machine with device tree enabled.
|
||||
|
|
|
|||
|
|
@ -13,10 +13,6 @@ obj- :=
|
|||
# Core
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += common.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
|
||||
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
|
||||
|
|
@ -26,8 +22,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
|
|||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
||||
obj-$(CONFIG_EXYNOS4_MCT) += mct.o
|
||||
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
||||
# machine support
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clksrc_clk exynos4_clk_aclk_133;
|
||||
extern struct clksrc_clk exynos4_clk_mout_mpll;
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_corebus;
|
||||
extern struct clksrc_sources exynos4_clkset_group;
|
||||
|
||||
extern struct clk *exynos4_clkset_aclk_top_list[];
|
||||
extern struct clk *exynos4_clkset_group_list[];
|
||||
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d0;
|
||||
extern struct clksrc_sources exynos4_clkset_mout_g2d1;
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4210_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4210_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4210_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4210_clkset_mout_g2d = {
|
||||
.sources = exynos4210_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.id = -1,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_corebus,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &exynos4_clkset_group,
|
||||
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4210_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.11",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4210_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4210_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4210_clock_suspend NULL
|
||||
#define exynos4210_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
.suspend = exynos4210_clock_suspend,
|
||||
.resume = exynos4210_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4210_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 8;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4210_clock_syscore_ops);
|
||||
}
|
||||
|
|
@ -1,201 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4212 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clock-exynos4.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
|
||||
};
|
||||
#endif
|
||||
|
||||
static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
[1] = &exynos4_clk_mout_mpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clk_src_mpll_user = {
|
||||
.sources = clk_src_mpll_user_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_mpll_user = {
|
||||
.clk = {
|
||||
.name = "mout_mpll_user",
|
||||
},
|
||||
.sources = &clk_src_mpll_user,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d0,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
},
|
||||
.sources = &exynos4_clkset_mout_g2d1,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
|
||||
[0] = &exynos4x12_clk_mout_g2d0.clk,
|
||||
[1] = &exynos4x12_clk_mout_g2d1.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
|
||||
.sources = exynos4x12_clkset_mout_g2d_list,
|
||||
.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
&clk_mout_mpll_user,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
},
|
||||
.sources = &exynos4x12_clkset_mout_g2d,
|
||||
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
|
||||
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.9",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.12",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (7 << 8),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.13",
|
||||
.enable = exynos4212_clk_ip_isp1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.14",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "sysmmu",
|
||||
.devname = "exynos-sysmmu.15",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.0",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "flite",
|
||||
.devname = "exynos-fimc-lite.1",
|
||||
.enable = exynos4212_clk_ip_isp0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.enable = exynos4_clk_ip_dmc_ctrl,
|
||||
.ctrlbit = (1 << 23),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4212_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4212_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4212_clock_suspend NULL
|
||||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
static struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4212_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
exynos4_clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
|
||||
exynos4_clk_mout_mpll.reg_src.shift = 12;
|
||||
exynos4_clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4212_clock_syscore_ops);
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -25,6 +25,8 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
|
|
@ -39,7 +41,6 @@
|
|||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
|
@ -65,17 +66,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
|
|||
static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos5440_map_io(void);
|
||||
static void exynos4_init_clocks(int xtal);
|
||||
static void exynos5_init_clocks(int xtal);
|
||||
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static int exynos_init(void);
|
||||
|
||||
unsigned long xxti_f = 0, xusbxti_f = 0;
|
||||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
{
|
||||
.idcode = EXYNOS4210_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4210,
|
||||
|
|
@ -83,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4212_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4212,
|
||||
|
|
@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS4412_CPU_ID,
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4412,
|
||||
|
|
@ -99,7 +97,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = EXYNOS5250_SOC_ID,
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5_map_io,
|
||||
.init_clocks = exynos5_init_clocks,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5250,
|
||||
}, {
|
||||
|
|
@ -256,11 +253,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSTIMER,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
|
||||
|
|
@ -402,43 +394,26 @@ static void __init exynos5_map_io(void)
|
|||
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
|
||||
}
|
||||
|
||||
static void __init exynos4_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
exynos4210_register_clocks();
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
exynos4212_register_clocks();
|
||||
|
||||
exynos4_register_clocks();
|
||||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
static void __init exynos5440_map_io(void)
|
||||
{
|
||||
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
||||
}
|
||||
|
||||
static void __init exynos5_init_clocks(int xtal)
|
||||
void __init exynos_init_time(void)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
/* EXYNOS5440 can support only common clock framework */
|
||||
|
||||
if (soc_is_exynos5440())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS5250
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
exynos5_register_clocks();
|
||||
exynos5_setup_clocks();
|
||||
if (of_have_populated_dt()) {
|
||||
#ifdef CONFIG_OF
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
#endif
|
||||
} else {
|
||||
/* todo: remove after migrating legacy E4 platforms to dt */
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
exynos4_clk_init(NULL);
|
||||
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
|
||||
#endif
|
||||
mct_init();
|
||||
}
|
||||
}
|
||||
|
||||
void __init exynos4_init_irq(void)
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@
|
|||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||
|
||||
extern void exynos4_timer_init(void);
|
||||
#include <linux/of.h>
|
||||
|
||||
extern void mct_init(void);
|
||||
void exynos_init_time(void);
|
||||
extern unsigned long xxti_f, xusbxti_f;
|
||||
|
||||
struct map_desc;
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
|
|
@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
|
|||
void exynos5_restart(char mode, const char *cmd);
|
||||
void exynos_init_late(void);
|
||||
|
||||
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
|
||||
void exynos4_clk_init(struct device_node *np);
|
||||
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS
|
||||
int exynos_pm_late_initcall(void);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -30,8 +30,6 @@
|
|||
|
||||
/* For EXYNOS4 and EXYNOS5 */
|
||||
|
||||
#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
|
||||
|
||||
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
|
||||
|
||||
/* For EXYNOS4 SoCs */
|
||||
|
|
@ -323,8 +321,6 @@
|
|||
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
|
||||
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
|
||||
|
||||
#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
|
||||
#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
|
||||
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
|
||||
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
|
||||
|
|
@ -419,8 +415,6 @@
|
|||
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
|
||||
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
|
||||
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@
|
|||
#define EXYNOS5_PA_CMU 0x10010000
|
||||
|
||||
#define EXYNOS4_PA_SYSTIMER 0x10050000
|
||||
#define EXYNOS5_PA_SYSTIMER 0x101C0000
|
||||
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS5_PA_WATCHDOG 0x101D0000
|
||||
|
|
|
|||
|
|
@ -256,113 +256,6 @@
|
|||
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
|
||||
|
||||
/* For EXYNOS5250 */
|
||||
|
||||
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
|
||||
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
|
||||
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
|
||||
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
|
||||
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
|
||||
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
|
||||
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
|
||||
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
|
||||
|
||||
#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
|
||||
#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
|
||||
|
||||
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
|
||||
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
|
||||
|
||||
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
|
||||
|
||||
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
|
||||
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
|
||||
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
|
||||
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
|
||||
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
|
||||
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
|
||||
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
|
||||
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
|
||||
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
|
||||
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
|
||||
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
|
||||
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
|
||||
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
|
||||
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
|
||||
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
|
||||
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
|
||||
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
|
||||
|
||||
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
|
||||
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
|
||||
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
|
||||
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
|
||||
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
|
||||
|
||||
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
|
||||
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
|
||||
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
|
||||
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
|
||||
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
|
||||
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
|
||||
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
|
||||
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
|
||||
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
|
||||
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
|
||||
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
|
||||
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
|
||||
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
|
||||
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
|
||||
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
|
||||
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
|
||||
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
|
||||
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
|
||||
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
|
||||
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
|
||||
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
|
||||
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
|
||||
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
|
||||
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
|
||||
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
|
||||
|
||||
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
|
||||
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
|
||||
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
|
||||
|
||||
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
|
||||
|
||||
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
|
||||
|
||||
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
|
||||
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
|
||||
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
|
||||
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
|
||||
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
|
||||
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
|
||||
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
|
||||
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
|
||||
|
||||
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
|
||||
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
|
||||
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
|
||||
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
|
||||
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
|
||||
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
|
||||
|
||||
/* Compatibility defines and inclusion */
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
|
|
|||
|
|
@ -1,53 +0,0 @@
|
|||
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 MCT configutation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_MCT_H
|
||||
#define __ASM_ARCH_REGS_MCT_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
|
||||
|
||||
#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
|
||||
#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
|
||||
#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
|
||||
|
||||
#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
|
||||
#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
|
||||
#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
|
||||
|
||||
#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
|
||||
|
||||
#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
|
||||
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
|
||||
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
|
||||
|
||||
#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
|
||||
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
|
||||
#define EXYNOS4_MCT_L_MASK (0xffffff00)
|
||||
|
||||
#define MCT_L_TCNTB_OFFSET (0x00)
|
||||
#define MCT_L_ICNTB_OFFSET (0x08)
|
||||
#define MCT_L_TCON_OFFSET (0x20)
|
||||
#define MCT_L_INT_CSTAT_OFFSET (0x30)
|
||||
#define MCT_L_INT_ENB_OFFSET (0x34)
|
||||
#define MCT_L_WSTAT_OFFSET (0x40)
|
||||
|
||||
#define MCT_G_TCON_START (1 << 8)
|
||||
#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
|
||||
#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
|
||||
|
||||
#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
|
||||
#define MCT_L_TCON_INT_START (1 << 1)
|
||||
#define MCT_L_TCON_TIMER_START (1 << 0)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_MCT_H */
|
||||
|
|
@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
|
|||
static void __init armlex4210_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(armlex4210_uartcfgs,
|
||||
ARRAY_SIZE(armlex4210_uartcfgs));
|
||||
}
|
||||
|
|
@ -202,6 +201,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
|||
.map_io = armlex4210_map_io,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -11,121 +11,26 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the Exynos4 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
|
||||
"exynos4-sdhci.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
|
||||
"exynos4-sdhci.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
|
||||
"exynos4-sdhci.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
|
||||
"exynos4-sdhci.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
|
||||
"exynos-sysmmu.0", NULL), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
|
||||
"exynos-sysmmu.1", NULL), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
|
||||
"exynos-sysmmu.3", NULL), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
|
||||
"exynos-sysmmu.5", NULL), /* FIMC0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
|
||||
"exynos-sysmmu.6", NULL), /* FIMC1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
|
||||
"exynos-sysmmu.7", NULL), /* FIMC2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
|
||||
"exynos-sysmmu.8", NULL), /* FIMC3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMD0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
|
||||
"exynos-sysmmu.12", NULL), /* IS0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
|
||||
"exynos-sysmmu.13", NULL), /* IS1(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
|
||||
"exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
|
||||
"exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos4_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos4_dt_machine_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos4_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos4_dt_compat[] __initdata = {
|
||||
|
|
@ -135,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static void __init exynos4_reserve(void)
|
||||
{
|
||||
#ifdef CONFIG_S5P_DEV_MFC
|
||||
struct s5p_mfc_dt_meminfo mfc_mem;
|
||||
|
||||
/* Reserve memory for MFC only if it's available */
|
||||
mfc_mem.compatible = "samsung,mfc-v5";
|
||||
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
|
||||
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
|
||||
mfc_mem.lsize);
|
||||
#endif
|
||||
}
|
||||
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
||||
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
|
|
@ -142,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
|||
.map_io = exynos4_dt_map_io,
|
||||
.init_machine = exynos4_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos4_dt_compat,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = exynos4_reserve,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -11,151 +11,21 @@
|
|||
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The following lookup table is used to override device names when devices
|
||||
* are registered from device tree. This is temporarily added to enable
|
||||
* device tree support addition for the EXYNOS5 architecture.
|
||||
*
|
||||
* For drivers that require platform data to be provided from the machine
|
||||
* file, a platform data pointer can also be supplied along with the
|
||||
* devices names. Usually, the platform data elements that cannot be parsed
|
||||
* from the device tree by the drivers (example: function pointers) are
|
||||
* supplied. But it should be noted that this is a temporary mechanism and
|
||||
* at some point, the drivers should be capable of parsing all the platform
|
||||
* data from the device tree.
|
||||
*/
|
||||
static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
|
||||
"exynos4210-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
|
||||
"exynos4210-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
|
||||
"exynos4210-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
|
||||
"s3c2440-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
|
||||
"s3c2440-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
|
||||
"s3c2440-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
|
||||
"s3c2440-i2c.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
|
||||
"s3c2440-i2c.4", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
|
||||
"s3c2440-i2c.5", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
|
||||
"s3c2440-i2c.6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
|
||||
"s3c2440-i2c.7", NULL),
|
||||
OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
|
||||
"s3c2440-hdmiphy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
|
||||
"dw_mmc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
|
||||
"dw_mmc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
|
||||
"dw_mmc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
|
||||
"dw_mmc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
|
||||
"exynos4210-spi.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
|
||||
"exynos4210-spi.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
|
||||
"exynos4210-spi.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
|
||||
"exynos5-sata", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
|
||||
"exynos5-sata-phy", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
|
||||
"exynos5-sata-phy-i2c", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
|
||||
"exynos-gsc.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
|
||||
"exynos-gsc.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
|
||||
"exynos-gsc.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
|
||||
"exynos-gsc.3", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
|
||||
"exynos5-hdmi", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
|
||||
"exynos5-mixer", NULL),
|
||||
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
|
||||
"samsung-i2s.0", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
|
||||
"samsung-i2s.1", NULL),
|
||||
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
|
||||
"samsung-i2s.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
|
||||
"exynos-sysmmu.0", "mfc"), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
|
||||
"exynos-sysmmu.1", "mfc"), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
|
||||
"exynos-sysmmu.3", "jpeg"), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
|
||||
"exynos-sysmmu.5", "gscl"), /* GSCL0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
|
||||
"exynos-sysmmu.6", "gscl"), /* GSCL1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
|
||||
"exynos-sysmmu.7", "gscl"), /* GSCL2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
|
||||
"exynos-sysmmu.8", "gscl"), /* GSCL3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
|
||||
"exynos-sysmmu.9", NULL), /* FIMC-IS0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMC-IS1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
|
||||
"exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
|
||||
"exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
|
||||
"exynos-sysmmu.14", NULL), /* G2D */
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
|
||||
"exynos4210-uart.0", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init exynos5_dt_map_io(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
exynos_init_io(NULL, 0);
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
|
||||
s3c24xx_init_clocks(24000000);
|
||||
}
|
||||
|
||||
static void __init exynos5_dt_machine_init(void)
|
||||
|
|
@ -182,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("samsung,exynos5250"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5250_auxdata_lookup, NULL);
|
||||
else if (of_machine_is_compatible("samsung,exynos5440"))
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
exynos5440_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static char const *exynos5_dt_compat[] __initdata = {
|
||||
|
|
@ -216,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
|||
.map_io = exynos5_dt_map_io,
|
||||
.init_machine = exynos5_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.dt_compat = exynos5_dt_compat,
|
||||
.restart = exynos5_restart,
|
||||
.reserve = exynos5_reserve,
|
||||
|
|
|
|||
|
|
@ -1330,8 +1330,9 @@ static struct platform_device *nuri_devices[] __initdata = {
|
|||
static void __init nuri_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init nuri_reserve(void)
|
||||
|
|
@ -1380,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
|
|||
.map_io = nuri_map_io,
|
||||
.init_machine = nuri_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &nuri_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -754,8 +754,9 @@ static void s5p_tv_setup(void)
|
|||
static void __init origen_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init origen_power_init(void)
|
||||
|
|
@ -815,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
|
|||
.map_io = origen_map_io,
|
||||
.init_machine = origen_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &origen_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
|
|||
static void __init smdk4x12_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
|
||||
}
|
||||
|
||||
|
|
@ -376,7 +375,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
@ -390,7 +389,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
|
|||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
.reserve = &smdk4x12_reserve,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -371,8 +371,9 @@ static void s5p_tv_setup(void)
|
|||
static void __init smdkv310_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
|
||||
xxti_f = 12000000;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void __init smdkv310_reserve(void)
|
||||
|
|
@ -423,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
|
|||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -436,7 +437,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
|
|||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos4_timer_init,
|
||||
.init_time = exynos_init_time,
|
||||
.reserve = &smdkv310_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
#include <plat/mfc.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/s5p-time.h>
|
||||
#include <plat/samsung-time.h>
|
||||
#include <plat/camport.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
|
@ -1092,9 +1092,10 @@ static struct platform_device *universal_devices[] __initdata = {
|
|||
static void __init universal_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
|
||||
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
|
||||
xxti_f = 0;
|
||||
xusbxti_f = 24000000;
|
||||
}
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
|
|
@ -1152,7 +1153,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
|
|||
.map_io = universal_map_io,
|
||||
.init_machine = universal_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = s5p_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.reserve = &universal_reserve,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ config CPU_S3C2410
|
|||
select S3C2410_CLOCK
|
||||
select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
|
||||
select S3C2410_PM if PM
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Support for S3C2410 and S3C2410A family from the S3C24XX line
|
||||
of Samsung Mobile CPUs.
|
||||
|
|
@ -41,6 +42,7 @@ config CPU_S3C2412
|
|||
select CPU_LLSERIAL_S3C2440
|
||||
select S3C2412_DMA if S3C24XX_DMA
|
||||
select S3C2412_PM if PM
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
|
||||
|
||||
|
|
@ -53,6 +55,7 @@ config CPU_S3C2416
|
|||
select S3C2443_COMMON
|
||||
select S3C2443_DMA if S3C24XX_DMA
|
||||
select SAMSUNG_CLKSRC
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Support for the S3C2416 SoC from the S3C24XX line
|
||||
|
||||
|
|
@ -63,6 +66,7 @@ config CPU_S3C2440
|
|||
select S3C2410_CLOCK
|
||||
select S3C2410_PM if PM
|
||||
select S3C2440_DMA if S3C24XX_DMA
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Support for S3C2440 Samsung Mobile CPU based systems.
|
||||
|
||||
|
|
@ -72,6 +76,7 @@ config CPU_S3C2442
|
|||
select CPU_LLSERIAL_S3C2440
|
||||
select S3C2410_CLOCK
|
||||
select S3C2410_PM if PM
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Support for S3C2442 Samsung Mobile CPU based systems.
|
||||
|
||||
|
|
@ -87,6 +92,7 @@ config CPU_S3C2443
|
|||
select S3C2443_COMMON
|
||||
select S3C2443_DMA if S3C24XX_DMA
|
||||
select SAMSUNG_CLKSRC
|
||||
select SAMSUNG_HRT
|
||||
help
|
||||
Support for the S3C2443 SoC from the S3C24XX line
|
||||
|
||||
|
|
|
|||
|
|
@ -34,8 +34,6 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/regs-irq.h>
|
||||
|
||||
#include <plat/irq.h>
|
||||
|
||||
#include "bast.h"
|
||||
|
||||
#define irqdbf(x...)
|
||||
|
|
|
|||
|
|
@ -40,7 +40,6 @@
|
|||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,6 @@
|
|||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/s3c2412.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <plat/s3c2416.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/cpu.h>
|
||||
|
|
|
|||
|
|
@ -41,7 +41,6 @@
|
|||
|
||||
#include <plat/cpu-freq.h>
|
||||
|
||||
#include <plat/s3c2443.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/cpu.h>
|
||||
|
|
|
|||
|
|
@ -41,11 +41,12 @@
|
|||
|
||||
#include <linux/platform_data/mtd-nand-s3c2410.h>
|
||||
|
||||
#include <plat/common-smdk.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include "common-smdk.h"
|
||||
|
||||
/* LED devices */
|
||||
|
||||
static struct s3c24xx_led_platdata smdk_pdata_led4 = {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
|
||||
*
|
||||
/*
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
|
|
@ -47,14 +47,11 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/s3c2412.h>
|
||||
#include <plat/s3c2416.h>
|
||||
#include <plat/s3c244x.h>
|
||||
#include <plat/s3c2443.h>
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/pll.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/* table of supported CPUs */
|
||||
|
||||
static const char name_s3c2410[] = "S3C2410";
|
||||
|
|
|
|||
|
|
@ -12,8 +12,94 @@
|
|||
#ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
|
||||
#define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
|
||||
|
||||
void s3c2410_restart(char mode, const char *cmd);
|
||||
void s3c244x_restart(char mode, const char *cmd);
|
||||
struct s3c2410_uartcfg;
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2410
|
||||
extern int s3c2410_init(void);
|
||||
extern int s3c2410a_init(void);
|
||||
extern void s3c2410_map_io(void);
|
||||
extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
extern void s3c2410_init_clocks(int xtal);
|
||||
extern void s3c2410_restart(char mode, const char *cmd);
|
||||
#else
|
||||
#define s3c2410_init_clocks NULL
|
||||
#define s3c2410_init_uarts NULL
|
||||
#define s3c2410_map_io NULL
|
||||
#define s3c2410_init NULL
|
||||
#define s3c2410a_init NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2412
|
||||
extern int s3c2412_init(void);
|
||||
extern void s3c2412_map_io(void);
|
||||
extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
extern void s3c2412_init_clocks(int xtal);
|
||||
extern int s3c2412_baseclk_add(void);
|
||||
extern void s3c2412_restart(char mode, const char *cmd);
|
||||
#else
|
||||
#define s3c2412_init_clocks NULL
|
||||
#define s3c2412_init_uarts NULL
|
||||
#define s3c2412_map_io NULL
|
||||
#define s3c2412_init NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2416
|
||||
extern int s3c2416_init(void);
|
||||
extern void s3c2416_map_io(void);
|
||||
extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
extern void s3c2416_init_clocks(int xtal);
|
||||
extern int s3c2416_baseclk_add(void);
|
||||
extern void s3c2416_restart(char mode, const char *cmd);
|
||||
extern void s3c2416_init_irq(void);
|
||||
|
||||
extern struct syscore_ops s3c2416_irq_syscore_ops;
|
||||
#else
|
||||
#define s3c2416_init_clocks NULL
|
||||
#define s3c2416_init_uarts NULL
|
||||
#define s3c2416_map_io NULL
|
||||
#define s3c2416_init NULL
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
|
||||
extern void s3c244x_map_io(void);
|
||||
extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
extern void s3c244x_init_clocks(int xtal);
|
||||
extern void s3c244x_restart(char mode, const char *cmd);
|
||||
#else
|
||||
#define s3c244x_init_clocks NULL
|
||||
#define s3c244x_init_uarts NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
extern int s3c2440_init(void);
|
||||
extern void s3c2440_map_io(void);
|
||||
#else
|
||||
#define s3c2440_init NULL
|
||||
#define s3c2440_map_io NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2442
|
||||
extern int s3c2442_init(void);
|
||||
extern void s3c2442_map_io(void);
|
||||
#else
|
||||
#define s3c2442_init NULL
|
||||
#define s3c2442_map_io NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2443
|
||||
extern int s3c2443_init(void);
|
||||
extern void s3c2443_map_io(void);
|
||||
extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
extern void s3c2443_init_clocks(int xtal);
|
||||
extern int s3c2443_baseclk_add(void);
|
||||
extern void s3c2443_restart(char mode, const char *cmd);
|
||||
extern void s3c2443_init_irq(void);
|
||||
#else
|
||||
#define s3c2443_init_clocks NULL
|
||||
#define s3c2443_init_uarts NULL
|
||||
#define s3c2443_map_io NULL
|
||||
#define s3c2443_init NULL
|
||||
#endif
|
||||
|
||||
extern struct syscore_ops s3c24xx_irq_syscore_ops;
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@
|
|||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
#include <plat/regs-iis.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@
|
|||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
#include <plat/regs-iis.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@
|
|||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
#include <plat/regs-iis.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@
|
|||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
#include <plat/regs-iis.h>
|
||||
#include <plat/regs-spi.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,127 +0,0 @@
|
|||
/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
|
||||
*
|
||||
* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
|
||||
* http://www.simtec.co.uk/products/SWLINUX/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* S3C2410 MMC/SDIO register definitions
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_REGS_SDI
|
||||
#define __ASM_ARM_REGS_SDI "regs-sdi.h"
|
||||
|
||||
#define S3C2410_SDICON (0x00)
|
||||
#define S3C2410_SDIPRE (0x04)
|
||||
#define S3C2410_SDICMDARG (0x08)
|
||||
#define S3C2410_SDICMDCON (0x0C)
|
||||
#define S3C2410_SDICMDSTAT (0x10)
|
||||
#define S3C2410_SDIRSP0 (0x14)
|
||||
#define S3C2410_SDIRSP1 (0x18)
|
||||
#define S3C2410_SDIRSP2 (0x1C)
|
||||
#define S3C2410_SDIRSP3 (0x20)
|
||||
#define S3C2410_SDITIMER (0x24)
|
||||
#define S3C2410_SDIBSIZE (0x28)
|
||||
#define S3C2410_SDIDCON (0x2C)
|
||||
#define S3C2410_SDIDCNT (0x30)
|
||||
#define S3C2410_SDIDSTA (0x34)
|
||||
#define S3C2410_SDIFSTA (0x38)
|
||||
|
||||
#define S3C2410_SDIDATA (0x3C)
|
||||
#define S3C2410_SDIIMSK (0x40)
|
||||
|
||||
#define S3C2440_SDIDATA (0x40)
|
||||
#define S3C2440_SDIIMSK (0x3C)
|
||||
|
||||
#define S3C2440_SDICON_SDRESET (1<<8)
|
||||
#define S3C2440_SDICON_MMCCLOCK (1<<5)
|
||||
#define S3C2410_SDICON_BYTEORDER (1<<4)
|
||||
#define S3C2410_SDICON_SDIOIRQ (1<<3)
|
||||
#define S3C2410_SDICON_RWAITEN (1<<2)
|
||||
#define S3C2410_SDICON_FIFORESET (1<<1)
|
||||
#define S3C2410_SDICON_CLOCKTYPE (1<<0)
|
||||
|
||||
#define S3C2410_SDICMDCON_ABORT (1<<12)
|
||||
#define S3C2410_SDICMDCON_WITHDATA (1<<11)
|
||||
#define S3C2410_SDICMDCON_LONGRSP (1<<10)
|
||||
#define S3C2410_SDICMDCON_WAITRSP (1<<9)
|
||||
#define S3C2410_SDICMDCON_CMDSTART (1<<8)
|
||||
#define S3C2410_SDICMDCON_SENDERHOST (1<<6)
|
||||
#define S3C2410_SDICMDCON_INDEX (0x3f)
|
||||
|
||||
#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12)
|
||||
#define S3C2410_SDICMDSTAT_CMDSENT (1<<11)
|
||||
#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
|
||||
#define S3C2410_SDICMDSTAT_RSPFIN (1<<9)
|
||||
#define S3C2410_SDICMDSTAT_XFERING (1<<8)
|
||||
#define S3C2410_SDICMDSTAT_INDEX (0xff)
|
||||
|
||||
#define S3C2440_SDIDCON_DS_BYTE (0<<22)
|
||||
#define S3C2440_SDIDCON_DS_HALFWORD (1<<22)
|
||||
#define S3C2440_SDIDCON_DS_WORD (2<<22)
|
||||
#define S3C2410_SDIDCON_IRQPERIOD (1<<21)
|
||||
#define S3C2410_SDIDCON_TXAFTERRESP (1<<20)
|
||||
#define S3C2410_SDIDCON_RXAFTERCMD (1<<19)
|
||||
#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18)
|
||||
#define S3C2410_SDIDCON_BLOCKMODE (1<<17)
|
||||
#define S3C2410_SDIDCON_WIDEBUS (1<<16)
|
||||
#define S3C2410_SDIDCON_DMAEN (1<<15)
|
||||
#define S3C2410_SDIDCON_STOP (1<<14)
|
||||
#define S3C2440_SDIDCON_DATSTART (1<<14)
|
||||
#define S3C2410_SDIDCON_DATMODE (3<<12)
|
||||
#define S3C2410_SDIDCON_BLKNUM (0x7ff)
|
||||
|
||||
/* constants for S3C2410_SDIDCON_DATMODE */
|
||||
#define S3C2410_SDIDCON_XFER_READY (0<<12)
|
||||
#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
|
||||
#define S3C2410_SDIDCON_XFER_RXSTART (2<<12)
|
||||
#define S3C2410_SDIDCON_XFER_TXSTART (3<<12)
|
||||
|
||||
#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
|
||||
#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12)
|
||||
|
||||
#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10)
|
||||
#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
|
||||
#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */
|
||||
#define S3C2410_SDIDSTA_CRCFAIL (1<<7)
|
||||
#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6)
|
||||
#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5)
|
||||
#define S3C2410_SDIDSTA_XFERFINISH (1<<4)
|
||||
#define S3C2410_SDIDSTA_BUSYFINISH (1<<3)
|
||||
#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */
|
||||
#define S3C2410_SDIDSTA_TXDATAON (1<<1)
|
||||
#define S3C2410_SDIDSTA_RXDATAON (1<<0)
|
||||
|
||||
#define S3C2440_SDIFSTA_FIFORESET (1<<16)
|
||||
#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */
|
||||
#define S3C2410_SDIFSTA_TFDET (1<<13)
|
||||
#define S3C2410_SDIFSTA_RFDET (1<<12)
|
||||
#define S3C2410_SDIFSTA_TFHALF (1<<11)
|
||||
#define S3C2410_SDIFSTA_TFEMPTY (1<<10)
|
||||
#define S3C2410_SDIFSTA_RFLAST (1<<9)
|
||||
#define S3C2410_SDIFSTA_RFFULL (1<<8)
|
||||
#define S3C2410_SDIFSTA_RFHALF (1<<7)
|
||||
#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
|
||||
|
||||
#define S3C2410_SDIIMSK_RESPONSECRC (1<<17)
|
||||
#define S3C2410_SDIIMSK_CMDSENT (1<<16)
|
||||
#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15)
|
||||
#define S3C2410_SDIIMSK_RESPONSEND (1<<14)
|
||||
#define S3C2410_SDIIMSK_READWAIT (1<<13)
|
||||
#define S3C2410_SDIIMSK_SDIOIRQ (1<<12)
|
||||
#define S3C2410_SDIIMSK_FIFOFAIL (1<<11)
|
||||
#define S3C2410_SDIIMSK_CRCSTATUS (1<<10)
|
||||
#define S3C2410_SDIIMSK_DATACRC (1<<9)
|
||||
#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8)
|
||||
#define S3C2410_SDIIMSK_DATAFINISH (1<<7)
|
||||
#define S3C2410_SDIIMSK_BUSYFINISH (1<<6)
|
||||
#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */
|
||||
#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4)
|
||||
#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3)
|
||||
#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2)
|
||||
#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1)
|
||||
#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0)
|
||||
|
||||
#endif /* __ASM_ARM_REGS_SDI */
|
||||
|
|
@ -16,10 +16,15 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/irq.h>
|
||||
#include <plat/map-base.h>
|
||||
#include <plat/map-s3c.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/regs-irqtype.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/irq.h>
|
||||
|
||||
#define S3C_IRQTYPE_NONE 0
|
||||
#define S3C_IRQTYPE_EINT 1
|
||||
|
|
@ -175,8 +174,7 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* FIXME: make static when it's out of plat-samsung/irq.h */
|
||||
int s3c_irqext_type(struct irq_data *data, unsigned int type)
|
||||
static int s3c_irqext_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
void __iomem *extint_reg;
|
||||
void __iomem *gpcon_reg;
|
||||
|
|
@ -224,7 +222,7 @@ static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
|
|||
extint_offset, type);
|
||||
}
|
||||
|
||||
struct irq_chip s3c_irq_chip = {
|
||||
static struct irq_chip s3c_irq_chip = {
|
||||
.name = "s3c",
|
||||
.irq_ack = s3c_irq_ack,
|
||||
.irq_mask = s3c_irq_mask,
|
||||
|
|
@ -232,7 +230,7 @@ struct irq_chip s3c_irq_chip = {
|
|||
.irq_set_wake = s3c_irq_wake
|
||||
};
|
||||
|
||||
struct irq_chip s3c_irq_level_chip = {
|
||||
static struct irq_chip s3c_irq_level_chip = {
|
||||
.name = "s3c-level",
|
||||
.irq_mask = s3c_irq_mask,
|
||||
.irq_unmask = s3c_irq_unmask,
|
||||
|
|
|
|||
|
|
@ -63,6 +63,8 @@
|
|||
#include <linux/mtd/map.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static struct resource amlm5900_nor_resource =
|
||||
|
|
@ -160,6 +162,7 @@ static void __init amlm5900_map_io(void)
|
|||
s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FB_S3C2410
|
||||
|
|
@ -237,6 +240,6 @@ MACHINE_START(AML_M5900, "AML_M5900")
|
|||
.map_io = amlm5900_map_io,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = amlm5900_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "anubis.h"
|
||||
#include "common.h"
|
||||
|
|
@ -410,6 +411,7 @@ static void __init anubis_map_io(void)
|
|||
s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
/* check for the newer revision boards with large page nand */
|
||||
|
||||
|
|
@ -444,6 +446,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
|
|||
.map_io = anubis_map_io,
|
||||
.init_machine = anubis_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <linux/platform_data/mmc-s3cmci.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
|
@ -192,6 +193,7 @@ static void __init at2440evb_map_io(void)
|
|||
s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
|
||||
s3c24xx_init_clocks(16934400);
|
||||
s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init at2440evb_init(void)
|
||||
|
|
@ -210,6 +212,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
|
|||
.map_io = at2440evb_map_io,
|
||||
.init_machine = at2440evb_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "bast.h"
|
||||
#include "common.h"
|
||||
|
|
@ -576,6 +577,7 @@ static void __init bast_map_io(void)
|
|||
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init bast_init(void)
|
||||
|
|
@ -605,6 +607,6 @@ MACHINE_START(BAST, "Simtec-BAST")
|
|||
.map_io = bast_map_io,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = bast_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -81,6 +81,7 @@
|
|||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "gta02.h"
|
||||
|
|
@ -501,6 +502,7 @@ static void __init gta02_map_io(void)
|
|||
s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -589,6 +591,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
|
|||
.map_io = gta02_map_io,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = gta02_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@
|
|||
#include <plat/pll.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/regs-serial.h>
|
||||
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "h1940.h"
|
||||
|
|
@ -646,6 +646,7 @@ static void __init h1940_map_io(void)
|
|||
s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
/* setup PM */
|
||||
|
||||
|
|
@ -741,6 +742,6 @@ MACHINE_START(H1940, "IPAQ-H1940")
|
|||
.reserve = h1940_reserve,
|
||||
.init_irq = h1940_init_irq,
|
||||
.init_machine = h1940_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -46,14 +46,15 @@
|
|||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <plat/s3c2412.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
#include <linux/platform_data/usb-s3c2410_udc.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "s3c2412-power.h"
|
||||
|
||||
static struct map_desc jive_iodesc[] __initdata = {
|
||||
|
|
@ -506,6 +507,7 @@ static void __init jive_map_io(void)
|
|||
s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void jive_power_off(void)
|
||||
|
|
@ -661,6 +663,6 @@ MACHINE_START(JIVE, "JIVE")
|
|||
.init_irq = s3c24xx_init_irq,
|
||||
.map_io = jive_map_io,
|
||||
.init_machine = jive_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@
|
|||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include <sound/s3c24xx_uda134x.h>
|
||||
|
||||
|
|
@ -525,6 +526,7 @@ static void __init mini2440_map_io(void)
|
|||
s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -687,6 +689,6 @@ MACHINE_START(MINI2440, "MINI2440")
|
|||
.map_io = mini2440_map_io,
|
||||
.init_machine = mini2440_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -48,8 +48,8 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <linux/platform_data/mmc-s3cmci.h>
|
||||
#include <plat/s3c2410.h>
|
||||
#include <linux/platform_data/usb-s3c2410_udc.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
|
@ -536,6 +536,7 @@ static void __init n30_map_io(void)
|
|||
n30_hwinit();
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
/* GPB3 is the line that controls the pull-up for the USB D+ line */
|
||||
|
|
@ -589,7 +590,7 @@ MACHINE_START(N30, "Acer-N30")
|
|||
Ben Dooks <ben-linux@fluff.org>
|
||||
*/
|
||||
.atag_offset = 0x100,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.init_machine = n30_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.map_io = n30_map_io,
|
||||
|
|
@ -600,7 +601,7 @@ MACHINE_START(N35, "Acer-N35")
|
|||
/* Maintainer: Christer Weinigel <christer@weinigel.se>
|
||||
*/
|
||||
.atag_offset = 0x100,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.init_machine = n30_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.map_io = n30_map_io,
|
||||
|
|
|
|||
|
|
@ -41,11 +41,10 @@
|
|||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/s3c244x.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
|
@ -137,6 +136,7 @@ static void __init nexcoder_map_io(void)
|
|||
s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
nexcoder_sensorboard_init();
|
||||
}
|
||||
|
|
@ -153,6 +153,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
|
|||
.map_io = nexcoder_map_io,
|
||||
.init_machine = nexcoder_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
|
@ -384,6 +385,7 @@ static void __init osiris_map_io(void)
|
|||
s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
/* check for the newer revision boards with large page nand */
|
||||
|
||||
|
|
@ -426,6 +428,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
|
|||
.map_io = osiris_map_io,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = osiris_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "otom.h"
|
||||
|
|
@ -102,6 +102,7 @@ static void __init otom11_map_io(void)
|
|||
s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init otom11_init(void)
|
||||
|
|
@ -116,6 +117,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
|
|||
.map_io = otom11_map_io,
|
||||
.init_machine = otom11_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -55,13 +55,14 @@
|
|||
#include <linux/platform_data/usb-s3c2410_udc.h>
|
||||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
|
||||
#include <plat/common-smdk.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "common-smdk.h"
|
||||
|
||||
static struct map_desc qt2410_iodesc[] __initdata = {
|
||||
{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
|
||||
|
|
@ -304,6 +305,7 @@ static void __init qt2410_map_io(void)
|
|||
s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
|
||||
s3c24xx_init_clocks(12*1000*1000);
|
||||
s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init qt2410_machine_init(void)
|
||||
|
|
@ -343,6 +345,6 @@ MACHINE_START(QT2410, "QT2410")
|
|||
.map_io = qt2410_map_io,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = qt2410_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@
|
|||
#include <plat/pm.h>
|
||||
#include <plat/regs-iic.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "h1940.h"
|
||||
|
|
@ -741,6 +742,7 @@ static void __init rx1950_map_io(void)
|
|||
s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
|
||||
s3c24xx_init_clocks(16934000);
|
||||
s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
/* setup PM */
|
||||
|
||||
|
|
@ -813,6 +815,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
|
|||
.reserve = rx1950_reserve,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = rx1950_init_machine,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "h1940.h"
|
||||
|
|
@ -179,6 +180,7 @@ static void __init rx3715_map_io(void)
|
|||
s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
|
||||
s3c24xx_init_clocks(16934000);
|
||||
s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
/* H1940 and RX3715 need to reserve this for suspend */
|
||||
|
|
@ -212,6 +214,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
|
|||
.reserve = rx3715_reserve,
|
||||
.init_irq = rx3715_init_irq,
|
||||
.init_machine = rx3715_init_machine,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -51,10 +51,10 @@
|
|||
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <plat/common-smdk.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "common-smdk.h"
|
||||
|
||||
static struct map_desc smdk2410_iodesc[] __initdata = {
|
||||
/* nothing here yet */
|
||||
|
|
@ -101,6 +101,7 @@ static void __init smdk2410_map_io(void)
|
|||
s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk2410_init(void)
|
||||
|
|
@ -117,6 +118,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
|
|||
.map_io = smdk2410_map_io,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = smdk2410_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -41,13 +41,13 @@
|
|||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
#include <mach/fb.h>
|
||||
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/s3c2412.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include <plat/common-smdk.h>
|
||||
#include "common.h"
|
||||
#include "common-smdk.h"
|
||||
|
||||
static struct map_desc smdk2413_iodesc[] __initdata = {
|
||||
};
|
||||
|
|
@ -106,6 +106,7 @@ static void __init smdk2413_map_io(void)
|
|||
s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk2413_machine_init(void)
|
||||
|
|
@ -132,7 +133,7 @@ MACHINE_START(S3C2413, "S3C2413")
|
|||
.init_irq = s3c24xx_init_irq,
|
||||
.map_io = smdk2413_map_io,
|
||||
.init_machine = smdk2413_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
||||
|
|
@ -144,7 +145,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
|
|||
.init_irq = s3c24xx_init_irq,
|
||||
.map_io = smdk2413_map_io,
|
||||
.init_machine = smdk2413_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
||||
|
|
@ -156,6 +157,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
|
|||
.init_irq = s3c24xx_init_irq,
|
||||
.map_io = smdk2413_map_io,
|
||||
.init_machine = smdk2413_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -42,7 +42,6 @@
|
|||
#include <linux/platform_data/leds-s3c24xx.h>
|
||||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
|
||||
#include <plat/s3c2416.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
|
|
@ -51,10 +50,12 @@
|
|||
#include <plat/sdhci.h>
|
||||
#include <linux/platform_data/usb-s3c2410_udc.h>
|
||||
#include <linux/platform_data/s3c-hsudc.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include <plat/fb.h>
|
||||
|
||||
#include <plat/common-smdk.h>
|
||||
#include "common.h"
|
||||
#include "common-smdk.h"
|
||||
|
||||
static struct map_desc smdk2416_iodesc[] __initdata = {
|
||||
/* ISA IO Space map (memory space selected by A24) */
|
||||
|
|
@ -221,6 +222,7 @@ static void __init smdk2416_map_io(void)
|
|||
s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk2416_machine_init(void)
|
||||
|
|
@ -253,6 +255,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
|
|||
.init_irq = s3c2416_init_irq,
|
||||
.map_io = smdk2416_map_io,
|
||||
.init_machine = smdk2416_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2416_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -38,15 +38,13 @@
|
|||
#include <mach/fb.h>
|
||||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/s3c244x.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <plat/common-smdk.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "common-smdk.h"
|
||||
|
||||
static struct map_desc smdk2440_iodesc[] __initdata = {
|
||||
/* ISA IO Space map (memory space selected by A24) */
|
||||
|
|
@ -163,6 +161,7 @@ static void __init smdk2440_map_io(void)
|
|||
s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
|
||||
s3c24xx_init_clocks(16934400);
|
||||
s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk2440_machine_init(void)
|
||||
|
|
@ -181,6 +180,6 @@ MACHINE_START(S3C2440, "SMDK2440")
|
|||
.init_irq = s3c24xx_init_irq,
|
||||
.map_io = smdk2440_map_io,
|
||||
.init_machine = smdk2440_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c244x_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -38,13 +38,13 @@
|
|||
#include <mach/fb.h>
|
||||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/s3c2443.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include <plat/common-smdk.h>
|
||||
#include "common.h"
|
||||
#include "common-smdk.h"
|
||||
|
||||
static struct map_desc smdk2443_iodesc[] __initdata = {
|
||||
/* ISA IO Space map (memory space selected by A24) */
|
||||
|
|
@ -122,6 +122,7 @@ static void __init smdk2443_map_io(void)
|
|||
s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk2443_machine_init(void)
|
||||
|
|
@ -143,6 +144,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
|
|||
.init_irq = s3c2443_init_irq,
|
||||
.map_io = smdk2443_map_io,
|
||||
.init_machine = smdk2443_machine_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2443_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/map.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
|
@ -136,6 +137,7 @@ static void __init tct_hammer_map_io(void)
|
|||
s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init tct_hammer_init(void)
|
||||
|
|
@ -149,6 +151,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
|
|||
.map_io = tct_hammer_map_io,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = tct_hammer_init,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@
|
|||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "bast.h"
|
||||
#include "common.h"
|
||||
|
|
@ -332,6 +333,7 @@ static void __init vr1000_map_io(void)
|
|||
s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init vr1000_init(void)
|
||||
|
|
@ -354,6 +356,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
|
|||
.map_io = vr1000_map_io,
|
||||
.init_machine = vr1000_init,
|
||||
.init_irq = s3c24xx_init_irq,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2410_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -41,12 +41,12 @@
|
|||
#include <linux/platform_data/i2c-s3c2410.h>
|
||||
#include <linux/platform_data/mtd-nand-s3c2410.h>
|
||||
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/s3c2412.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/samsung-time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static struct map_desc vstms_iodesc[] __initdata = {
|
||||
};
|
||||
|
|
@ -143,6 +143,7 @@ static void __init vstms_map_io(void)
|
|||
s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init vstms_init(void)
|
||||
|
|
@ -160,6 +161,6 @@ MACHINE_START(VSTMS, "VSTMS")
|
|||
.init_irq = s3c24xx_init_irq,
|
||||
.init_machine = vstms_init,
|
||||
.map_io = vstms_map_io,
|
||||
.init_time = s3c24xx_timer_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@
|
|||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/s3c2412.h>
|
||||
|
||||
#include "regs-dsc.h"
|
||||
#include "s3c2412-power.h"
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
#include <mach/regs-clock.h>
|
||||
#include <plat/regs-serial.h>
|
||||
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/clock.h>
|
||||
|
|
|
|||
|
|
@ -44,7 +44,6 @@
|
|||
#include <plat/pm.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-spi.h>
|
||||
#include <plat/s3c2412.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "regs-dsc.h"
|
||||
|
|
|
|||
|
|
@ -50,7 +50,6 @@
|
|||
#include <plat/gpio-core.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/gpio-cfg-helpers.h>
|
||||
#include <plat/s3c2416.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
|
|
|||
|
|
@ -33,7 +33,6 @@
|
|||
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/s3c244x.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <plat/gpio-core.h>
|
||||
|
|
|
|||
|
|
@ -44,7 +44,6 @@
|
|||
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/s3c244x.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <plat/gpio-core.h>
|
||||
|
|
|
|||
|
|
@ -36,7 +36,6 @@
|
|||
#include <plat/gpio-core.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/gpio-cfg-helpers.h>
|
||||
#include <plat/s3c2443.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/fb-core.h>
|
||||
|
|
|
|||
|
|
@ -37,8 +37,6 @@
|
|||
#include <plat/regs-serial.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/s3c2410.h>
|
||||
#include <plat/s3c244x.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue