ath9k_hw: Fill get_isr() for AR9003
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
John W. Linville
parent
1547da37db
commit
6c84ce08aa
5 changed files with 146 additions and 0 deletions
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@ -32,6 +32,138 @@ static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
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static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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{
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u32 isr = 0;
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u32 mask2 = 0;
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struct ath9k_hw_capabilities *pCap = &ah->caps;
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u32 sync_cause = 0;
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struct ath_common *common = ath9k_hw_common(ah);
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if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
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if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
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== AR_RTC_STATUS_ON)
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isr = REG_READ(ah, AR_ISR);
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}
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sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
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*masked = 0;
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if (!isr && !sync_cause)
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return false;
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if (isr) {
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if (isr & AR_ISR_BCNMISC) {
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u32 isr2;
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isr2 = REG_READ(ah, AR_ISR_S2);
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mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
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MAP_ISR_S2_TIM);
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mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
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MAP_ISR_S2_DTIM);
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mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
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MAP_ISR_S2_DTIMSYNC);
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mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
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MAP_ISR_S2_CABEND);
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mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
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MAP_ISR_S2_GTT);
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mask2 |= ((isr2 & AR_ISR_S2_CST) <<
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MAP_ISR_S2_CST);
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mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
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MAP_ISR_S2_TSFOOR);
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR_S2, isr2);
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isr &= ~AR_ISR_BCNMISC;
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}
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}
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if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
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isr = REG_READ(ah, AR_ISR_RAC);
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if (isr == 0xffffffff) {
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*masked = 0;
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return false;
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}
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*masked = isr & ATH9K_INT_COMMON;
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if (ah->config.rx_intr_mitigation)
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if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
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*masked |= ATH9K_INT_RXLP;
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if (ah->config.tx_intr_mitigation)
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if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
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*masked |= ATH9K_INT_TX;
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if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
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*masked |= ATH9K_INT_RXLP;
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if (isr & AR_ISR_HP_RXOK)
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*masked |= ATH9K_INT_RXHP;
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if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
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*masked |= ATH9K_INT_TX;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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u32 s0, s1;
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s0 = REG_READ(ah, AR_ISR_S0);
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REG_WRITE(ah, AR_ISR_S0, s0);
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s1 = REG_READ(ah, AR_ISR_S1);
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REG_WRITE(ah, AR_ISR_S1, s1);
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isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
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AR_ISR_TXEOL);
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}
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}
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if (isr & AR_ISR_GENTMR) {
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u32 s5;
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if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
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s5 = REG_READ(ah, AR_ISR_S5_S);
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else
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s5 = REG_READ(ah, AR_ISR_S5);
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ah->intr_gen_timer_trigger =
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MS(s5, AR_ISR_S5_GENTIMER_TRIG);
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ah->intr_gen_timer_thresh =
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MS(s5, AR_ISR_S5_GENTIMER_THRESH);
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if (ah->intr_gen_timer_trigger)
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*masked |= ATH9K_INT_GENTIMER;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR_S5, s5);
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isr &= ~AR_ISR_GENTMR;
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}
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}
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*masked |= mask2;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR, isr);
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(void) REG_READ(ah, AR_ISR);
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}
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}
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if (sync_cause) {
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if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
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REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
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REG_WRITE(ah, AR_RC, 0);
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*masked |= ATH9K_INT_FATAL;
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}
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if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
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ath_print(common, ATH_DBG_INTERRUPT,
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"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
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REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
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(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
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}
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return true;
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}
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@ -22,6 +22,14 @@
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#define AR_CtrlStat 0x00004000
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#define AR_TxRxDesc 0x00008000
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#define MAP_ISR_S2_CST 6
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#define MAP_ISR_S2_GTT 6
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#define MAP_ISR_S2_TIM 3
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#define MAP_ISR_S2_CABEND 0
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#define MAP_ISR_S2_DTIMSYNC 7
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#define MAP_ISR_S2_DTIM 7
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#define MAP_ISR_S2_TSFOOR 4
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struct ar9003_rxs {
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u32 ds_info;
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u32 status1;
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@ -2145,6 +2145,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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pCap->tx_desc_len = sizeof(struct ath_desc);
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}
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if (AR_SREV_9300_20_OR_LATER(ah))
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pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
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return 0;
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}
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@ -179,6 +179,7 @@ enum ath9k_hw_caps {
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ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
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ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
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ATH9K_HW_CAP_EDMA = BIT(17),
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ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
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};
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enum ath9k_capability_type {
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@ -169,6 +169,8 @@
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#define AR_ISR 0x0080
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#define AR_ISR_RXOK 0x00000001
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#define AR_ISR_RXDESC 0x00000002
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#define AR_ISR_HP_RXOK 0x00000001
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#define AR_ISR_LP_RXOK 0x00000002
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#define AR_ISR_RXERR 0x00000004
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#define AR_ISR_RXNOPKT 0x00000008
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#define AR_ISR_RXEOL 0x00000010
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