drm/i915: Add intel implementation of the pageflip ioctl
Acked-by: Jakob Bornecrantz <jakob@vmware.com> Acked-by: Thomas Hellström <thomas@shipmail.org> Review-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse "Orange Smoothie" Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kristian Høgsberg
Eric Anholt
parent
f40d6817a5
commit
6b95a207c1
6 changed files with 291 additions and 38 deletions
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@ -536,6 +536,10 @@ typedef struct drm_i915_private {
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/* indicate whether the LVDS_BORDER should be enabled or not */
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unsigned int lvds_border_bits;
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struct drm_crtc *plane_to_crtc_mapping[2];
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struct drm_crtc *pipe_to_crtc_mapping[2];
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wait_queue_head_t pending_flip_queue;
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/* Reclocking support */
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bool render_reclock_avail;
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bool lvds_downclock_avail;
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@ -639,6 +643,13 @@ struct drm_i915_gem_object {
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* Advice: are the backing pages purgeable?
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*/
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int madv;
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/**
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* Number of crtcs where this object is currently the fb, but
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* will be page flipped away on the next vblank. When it
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* reaches 0, dev_priv->pending_flip_queue will be woken up.
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*/
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atomic_t pending_flip;
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};
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/**
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@ -830,6 +841,7 @@ void i915_gem_free_all_phys_object(struct drm_device *dev);
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int i915_gem_object_get_pages(struct drm_gem_object *obj);
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void i915_gem_object_put_pages(struct drm_gem_object *obj);
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void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
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void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
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void i915_gem_shrinker_init(void);
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void i915_gem_shrinker_exit(void);
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@ -2771,6 +2771,22 @@ i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
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old_write_domain);
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}
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void
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i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
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{
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switch (obj->write_domain) {
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case I915_GEM_DOMAIN_GTT:
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i915_gem_object_flush_gtt_write_domain(obj);
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break;
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case I915_GEM_DOMAIN_CPU:
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i915_gem_object_flush_cpu_write_domain(obj);
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break;
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default:
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i915_gem_object_flush_gpu_write_domain(obj);
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break;
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}
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}
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/**
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* Moves a single object to the GTT read, and possibly write domain.
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*
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@ -3536,6 +3552,41 @@ i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
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return 0;
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}
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static int
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i915_gem_wait_for_pending_flip(struct drm_device *dev,
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struct drm_gem_object **object_list,
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int count)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj_priv;
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DEFINE_WAIT(wait);
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int i, ret = 0;
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for (;;) {
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prepare_to_wait(&dev_priv->pending_flip_queue,
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&wait, TASK_INTERRUPTIBLE);
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for (i = 0; i < count; i++) {
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obj_priv = object_list[i]->driver_private;
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if (atomic_read(&obj_priv->pending_flip) > 0)
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break;
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}
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if (i == count)
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break;
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if (!signal_pending(current)) {
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mutex_unlock(&dev->struct_mutex);
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schedule();
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mutex_lock(&dev->struct_mutex);
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continue;
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}
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ret = -ERESTARTSYS;
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break;
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}
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finish_wait(&dev_priv->pending_flip_queue, &wait);
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return ret;
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}
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int
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i915_gem_execbuffer(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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@ -3551,7 +3602,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
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int ret, ret2, i, pinned = 0;
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uint64_t exec_offset;
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uint32_t seqno, flush_domains, reloc_index;
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int pin_tries;
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int pin_tries, flips;
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#if WATCH_EXEC
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DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
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@ -3623,6 +3674,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
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}
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/* Look up object handles */
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flips = 0;
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for (i = 0; i < args->buffer_count; i++) {
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object_list[i] = drm_gem_object_lookup(dev, file_priv,
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exec_list[i].handle);
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@ -3641,6 +3693,14 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
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goto err;
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}
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obj_priv->in_execbuffer = true;
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flips += atomic_read(&obj_priv->pending_flip);
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}
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if (flips > 0) {
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ret = i915_gem_wait_for_pending_flip(dev, object_list,
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args->buffer_count);
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if (ret)
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goto err;
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}
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/* Pin and relocate */
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@ -4625,8 +4685,8 @@ i915_gem_load(struct drm_device *dev)
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for (i = 0; i < 8; i++)
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I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
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}
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i915_gem_detect_bit_6_swizzle(dev);
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init_waitqueue_head(&dev_priv->pending_flip_queue);
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}
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/*
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@ -43,10 +43,13 @@
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* we leave them always unmasked in IMR and then control enabling them through
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* PIPESTAT alone.
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*/
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#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
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#define I915_INTERRUPT_ENABLE_FIX \
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(I915_ASLE_INTERRUPT | \
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
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/** Interrupts that we mask and unmask at runtime. */
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#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
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@ -643,14 +646,22 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
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}
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if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
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intel_prepare_page_flip(dev, 0);
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if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
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intel_prepare_page_flip(dev, 1);
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if (pipea_stats & vblank_status) {
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vblank++;
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drm_handle_vblank(dev, 0);
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intel_finish_page_flip(dev, 0);
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}
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if (pipeb_stats & vblank_status) {
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vblank++;
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drm_handle_vblank(dev, 1);
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intel_finish_page_flip(dev, 1);
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}
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if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
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@ -157,6 +157,8 @@
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#define MI_OVERLAY_ON (0x1<<21)
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#define MI_OVERLAY_OFF (0x2<<21)
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#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
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#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
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#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
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#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
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#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
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#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
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@ -1190,6 +1190,51 @@ static void intel_update_fbc(struct drm_crtc *crtc,
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dev_priv->display.disable_fbc(dev);
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}
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static int
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intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
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{
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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u32 alignment;
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int ret;
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switch (obj_priv->tiling_mode) {
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case I915_TILING_NONE:
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alignment = 64 * 1024;
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break;
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case I915_TILING_X:
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/* pin() will align the object as required by fence */
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alignment = 0;
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break;
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case I915_TILING_Y:
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/* FIXME: Is this true? */
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DRM_ERROR("Y tiled not allowed for scan out buffers\n");
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return -EINVAL;
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default:
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BUG();
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}
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alignment = 256 * 1024;
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ret = i915_gem_object_pin(obj, alignment);
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if (ret != 0)
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return ret;
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/* Install a fence for tiled scan-out. Pre-i965 always needs a
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* fence, whereas 965+ only requires a fence if using
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* framebuffer compression. For simplicity, we always install
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* a fence as the cost is not that onerous.
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*/
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if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
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obj_priv->tiling_mode != I915_TILING_NONE) {
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ret = i915_gem_object_get_fence_reg(obj);
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if (ret != 0) {
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i915_gem_object_unpin(obj);
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return ret;
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}
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}
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return 0;
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}
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static int
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intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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@ -1209,7 +1254,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
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int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
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int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
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u32 dspcntr, alignment;
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u32 dspcntr;
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int ret;
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/* no fb bound */
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@ -1231,24 +1276,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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obj = intel_fb->obj;
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obj_priv = obj->driver_private;
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switch (obj_priv->tiling_mode) {
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case I915_TILING_NONE:
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alignment = 64 * 1024;
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break;
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case I915_TILING_X:
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/* pin() will align the object as required by fence */
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alignment = 0;
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break;
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case I915_TILING_Y:
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/* FIXME: Is this true? */
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DRM_ERROR("Y tiled not allowed for scan out buffers\n");
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return -EINVAL;
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default:
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BUG();
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}
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mutex_lock(&dev->struct_mutex);
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ret = i915_gem_object_pin(obj, alignment);
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ret = intel_pin_and_fence_fb_obj(dev, obj);
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if (ret != 0) {
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mutex_unlock(&dev->struct_mutex);
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return ret;
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@ -1261,20 +1290,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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return ret;
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}
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/* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
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* whereas 965+ only requires a fence if using framebuffer compression.
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* For simplicity, we always install a fence as the cost is not that onerous.
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*/
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if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
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obj_priv->tiling_mode != I915_TILING_NONE) {
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ret = i915_gem_object_get_fence_reg(obj);
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if (ret != 0) {
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i915_gem_object_unpin(obj);
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mutex_unlock(&dev->struct_mutex);
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return ret;
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}
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}
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dspcntr = I915_READ(dspcntr_reg);
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/* Mask out pixel format bits in case we change it */
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dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
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@ -4068,6 +4083,153 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
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kfree(intel_crtc);
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}
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struct intel_unpin_work {
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struct work_struct work;
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struct drm_device *dev;
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struct drm_gem_object *obj;
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struct drm_pending_vblank_event *event;
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int pending;
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};
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static void intel_unpin_work_fn(struct work_struct *__work)
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{
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struct intel_unpin_work *work =
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container_of(__work, struct intel_unpin_work, work);
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mutex_lock(&work->dev->struct_mutex);
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i915_gem_object_unpin(work->obj);
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drm_gem_object_unreference(work->obj);
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mutex_unlock(&work->dev->struct_mutex);
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kfree(work);
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}
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void intel_finish_page_flip(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_unpin_work *work;
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struct drm_i915_gem_object *obj_priv;
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struct drm_pending_vblank_event *e;
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struct timeval now;
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unsigned long flags;
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/* Ignore early vblank irqs */
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if (intel_crtc == NULL)
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return;
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spin_lock_irqsave(&dev->event_lock, flags);
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work = intel_crtc->unpin_work;
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if (work == NULL || !work->pending) {
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spin_unlock_irqrestore(&dev->event_lock, flags);
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return;
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}
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intel_crtc->unpin_work = NULL;
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drm_vblank_put(dev, intel_crtc->pipe);
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if (work->event) {
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e = work->event;
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do_gettimeofday(&now);
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e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
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e->event.tv_sec = now.tv_sec;
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e->event.tv_usec = now.tv_usec;
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list_add_tail(&e->base.link,
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&e->base.file_priv->event_list);
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wake_up_interruptible(&e->base.file_priv->event_wait);
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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obj_priv = work->obj->driver_private;
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if (atomic_dec_and_test(&obj_priv->pending_flip))
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DRM_WAKEUP(&dev_priv->pending_flip_queue);
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schedule_work(&work->work);
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}
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void intel_prepare_page_flip(struct drm_device *dev, int plane)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc =
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to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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if (intel_crtc->unpin_work)
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intel_crtc->unpin_work->pending = 1;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static int intel_crtc_page_flip(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_framebuffer *intel_fb;
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struct drm_i915_gem_object *obj_priv;
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struct drm_gem_object *obj;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_unpin_work *work;
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unsigned long flags;
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int ret;
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RING_LOCALS;
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work = kzalloc(sizeof *work, GFP_KERNEL);
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if (work == NULL)
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return -ENOMEM;
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mutex_lock(&dev->struct_mutex);
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work->event = event;
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work->dev = crtc->dev;
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intel_fb = to_intel_framebuffer(crtc->fb);
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work->obj = intel_fb->obj;
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INIT_WORK(&work->work, intel_unpin_work_fn);
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/* We borrow the event spin lock for protecting unpin_work */
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spin_lock_irqsave(&dev->event_lock, flags);
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if (intel_crtc->unpin_work) {
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spin_unlock_irqrestore(&dev->event_lock, flags);
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kfree(work);
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mutex_unlock(&dev->struct_mutex);
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return -EBUSY;
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}
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intel_crtc->unpin_work = work;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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intel_fb = to_intel_framebuffer(fb);
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obj = intel_fb->obj;
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ret = intel_pin_and_fence_fb_obj(dev, obj);
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if (ret != 0) {
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kfree(work);
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mutex_unlock(&dev->struct_mutex);
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return ret;
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}
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||||
/* Reference the old fb object for the scheduled work. */
|
||||
drm_gem_object_reference(work->obj);
|
||||
|
||||
crtc->fb = fb;
|
||||
i915_gem_object_flush_write_domain(obj);
|
||||
drm_vblank_get(dev, intel_crtc->pipe);
|
||||
obj_priv = obj->driver_private;
|
||||
atomic_inc(&obj_priv->pending_flip);
|
||||
|
||||
BEGIN_LP_RING(4);
|
||||
OUT_RING(MI_DISPLAY_FLIP |
|
||||
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
|
||||
OUT_RING(fb->pitch);
|
||||
OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
|
||||
OUT_RING((fb->width << 16) | fb->height);
|
||||
ADVANCE_LP_RING();
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_crtc_helper_funcs intel_helper_funcs = {
|
||||
.dpms = intel_crtc_dpms,
|
||||
.mode_fixup = intel_crtc_mode_fixup,
|
||||
|
|
@ -4084,12 +4246,14 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
|
|||
.gamma_set = intel_crtc_gamma_set,
|
||||
.set_config = drm_crtc_helper_set_config,
|
||||
.destroy = intel_crtc_destroy,
|
||||
.page_flip = intel_crtc_page_flip,
|
||||
};
|
||||
|
||||
|
||||
static void intel_crtc_init(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct intel_crtc *intel_crtc;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int i;
|
||||
|
||||
intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
|
||||
|
|
|
|||
|
|
@ -148,6 +148,7 @@ struct intel_crtc {
|
|||
struct timer_list idle_timer;
|
||||
bool lowfreq_avail;
|
||||
struct intel_overlay *overlay;
|
||||
struct intel_unpin_work *unpin_work;
|
||||
};
|
||||
|
||||
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
|
||||
|
|
@ -211,6 +212,9 @@ extern int intel_framebuffer_create(struct drm_device *dev,
|
|||
struct drm_framebuffer **fb,
|
||||
struct drm_gem_object *obj);
|
||||
|
||||
extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
|
||||
extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
|
||||
|
||||
extern void intel_setup_overlay(struct drm_device *dev);
|
||||
extern void intel_cleanup_overlay(struct drm_device *dev);
|
||||
extern int intel_overlay_switch_off(struct intel_overlay *overlay);
|
||||
|
|
|
|||
Loading…
Reference in a new issue