ARM: vexpress: Motherboard RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express motherboard. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This commit is contained in:
Pawel Moll
parent
8deed1786a
commit
6a3719562b
4 changed files with 309 additions and 6 deletions
201
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
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201
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
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@ -0,0 +1,201 @@
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/*
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* ARM Ltd. Versatile Express
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*
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* Motherboard Express uATX
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* V2M-P1
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*
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* HBI-0190D
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*
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* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
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* Technical Reference Manual)
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*
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* WARNING! The hardware described in this file is independent from the
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* original variant (vexpress-v2m.dtsi), but there is a strong
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* correspondence between the two configurations.
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*
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* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
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* CHANGES TO vexpress-v2m.dtsi!
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*/
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/ {
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aliases {
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arm,v2m_timer = &v2m_timer01;
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};
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motherboard {
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compatible = "simple-bus";
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arm,v2m-memory-map = "rs1";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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flash@0,00000000 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<4 0x00000000 0x04000000>;
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bank-width = <4>;
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};
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psram@1,00000000 {
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compatible = "arm,vexpress-psram", "mtd-ram";
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reg = <1 0x00000000 0x02000000>;
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bank-width = <4>;
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};
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vram@2,00000000 {
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compatible = "arm,vexpress-vram";
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reg = <2 0x00000000 0x00800000>;
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};
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ethernet@2,02000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <2 0x02000000 0x10000>;
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interrupts = <15>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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};
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usb@2,03000000 {
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compatible = "nxp,usb-isp1761";
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reg = <2 0x03000000 0x20000>;
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interrupts = <16>;
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port1-otg;
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};
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iofpga@3,00000000 {
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compatible = "arm,amba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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sysreg@010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x010000 0x1000>;
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};
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sysctl@020000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x020000 0x1000>;
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};
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/* PCI-E I2C bus */
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v2m_i2c_pcie: i2c@030000 {
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compatible = "arm,versatile-i2c";
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reg = <0x030000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie-switch@60 {
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compatible = "idt,89hpes32h8";
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reg = <0x60>;
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};
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};
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aaci@040000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x040000 0x1000>;
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interrupts = <11>;
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};
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mmci@050000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x050000 0x1000>;
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interrupts = <9 10>;
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};
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kmi@060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x060000 0x1000>;
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interrupts = <12>;
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};
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kmi@070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x070000 0x1000>;
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interrupts = <13>;
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};
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v2m_serial0: uart@090000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x090000 0x1000>;
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interrupts = <5>;
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};
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v2m_serial1: uart@0a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <6>;
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};
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v2m_serial2: uart@0b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b0000 0x1000>;
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interrupts = <7>;
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};
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v2m_serial3: uart@0c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c0000 0x1000>;
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interrupts = <8>;
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};
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wdt@0f0000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f0000 0x1000>;
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interrupts = <0>;
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};
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v2m_timer01: timer@110000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x110000 0x1000>;
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interrupts = <2>;
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};
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v2m_timer23: timer@120000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x120000 0x1000>;
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};
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/* DVI I2C bus */
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v2m_i2c_dvi: i2c@160000 {
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compatible = "arm,versatile-i2c";
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reg = <0x160000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dvi-transmitter@39 {
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compatible = "sil,sii9022-tpi", "sil,sii9022";
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reg = <0x39>;
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};
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dvi-transmitter@60 {
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compatible = "sil,sii9022-cpi", "sil,sii9022";
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reg = <0x60>;
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};
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};
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rtc@170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x170000 0x1000>;
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interrupts = <4>;
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};
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compact-flash@1a0000 {
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compatible = "arm,vexpress-cf", "ata-generic";
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reg = <0x1a0000 0x100
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0x1a0100 0xf00>;
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reg-shift = <2>;
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};
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clcd@1f0000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x1f0000 0x1000>;
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interrupts = <14>;
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};
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};
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};
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};
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@ -10,12 +10,34 @@
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* published by the Free Software Foundation.
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*/
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#define DEBUG_LL_UART_OFFSET 0x00009000
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#define DEBUG_LL_PHYS_BASE 0x10000000
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#define DEBUG_LL_UART_OFFSET 0x00009000
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#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
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#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
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#define DEBUG_LL_VIRT_BASE 0xf8000000
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.macro addruart,rp,rv,tmp
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mov \rp, #DEBUG_LL_UART_OFFSET
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orr \rv, \rp, #0xf8000000 @ virtual base
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orr \rp, \rp, #0x10000000 @ physical base
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@ Make an educated guess regarding the memory map:
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@ - the original A9 core tile, which has MPCore peripherals
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@ located at 0x1e000000, should use UART at 0x10009000
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@ - all other (RS1 complaint) tiles use UART mapped
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@ at 0x1c090000
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mrc p15, 4, \tmp, c15, c0, 0
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cmp \tmp, #0x1e000000
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@ Original memory map
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moveq \rp, #DEBUG_LL_UART_OFFSET
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orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
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orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
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@ RS1 memory map
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movne \rp, #DEBUG_LL_UART_OFFSET_RS1
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orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
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orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
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.endm
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#include <asm/hardware/debug-pl01x.S>
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@ -22,7 +22,27 @@
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#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
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#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
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#define get_uart_base() (0x10000000 + 0x00009000)
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#define UART_BASE 0x10009000
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#define UART_BASE_RS1 0x1c090000
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static unsigned long get_uart_base(void)
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{
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unsigned long mpcore_periph;
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/*
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* Make an educated guess regarding the memory map:
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* - the original A9 core tile, which has MPCore peripherals
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* located at 0x1e000000, should use UART at 0x10009000
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* - all other (RS1 complaint) tiles use UART mapped
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* at 0x1c090000
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*/
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
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if (mpcore_periph == 0x1e000000)
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return UART_BASE;
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else
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return UART_BASE_RS1;
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}
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/*
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* This does not append a newline
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@ -486,9 +486,36 @@ MACHINE_END
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#if defined(CONFIG_ARCH_VEXPRESS_DT)
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static struct map_desc v2m_rs1_io_desc __initdata = {
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.virtual = V2M_PERIPH,
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.pfn = __phys_to_pfn(0x1c000000),
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.length = SZ_2M,
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.type = MT_DEVICE,
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};
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static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
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int depth, void *data)
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{
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const char **map = data;
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if (strcmp(uname, "motherboard") != 0)
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return 0;
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*map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
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return 1;
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}
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void __init v2m_dt_map_io(void)
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{
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iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
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const char *map = NULL;
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of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
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if (map && strcmp(map, "rs1") == 0)
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iotable_init(&v2m_rs1_io_desc, 1);
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else
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iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
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#if defined(CONFIG_SMP)
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vexpress_dt_smp_map_io();
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@ -535,6 +562,35 @@ static struct clk_lookup v2m_dt_lookups[] = {
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.dev_id = "1001f000.clcd",
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.clk = &osc1_clk,
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},
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/* RS1 memory map */
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{ /* PL180 MMCI */
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.dev_id = "mb:mmci", /* 1c050000.mmci */
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.clk = &osc2_clk,
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}, { /* PL050 KMI0 */
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.dev_id = "1c060000.kmi",
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.clk = &osc2_clk,
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}, { /* PL050 KMI1 */
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.dev_id = "1c070000.kmi",
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.clk = &osc2_clk,
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}, { /* PL011 UART0 */
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.dev_id = "1c090000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART1 */
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.dev_id = "1c0a0000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART2 */
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.dev_id = "1c0b0000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART3 */
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.dev_id = "1c0c0000.uart",
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.clk = &osc2_clk,
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}, { /* SP805 WDT */
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.dev_id = "1c0f0000.wdt",
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.clk = &v2m_ref_clk,
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}, { /* PL111 CLCD */
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.dev_id = "1c1f0000.clcd",
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.clk = &osc1_clk,
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},
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};
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void __init v2m_dt_init_early(void)
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@ -597,6 +653,10 @@ static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
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&v2m_flash_data),
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OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
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/* RS1 memory map */
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OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
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&v2m_flash_data),
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OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
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{}
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};
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