msm-geni-serial: Correct the interrupt polling logic in uart

Correct the interrupt polling logic in uart and depend on the
interrupt routine instead of polling where ever possible.

Change-Id: Ia01889549d7edbe380e2e58b92efb2a0b3b34e7b
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
This commit is contained in:
Prudhvi Yarlagadda 2020-01-22 17:26:49 +05:30 committed by Gerrit - the friendly Code Review server
parent 7a55aabe29
commit 6a0ff35cad
2 changed files with 577 additions and 271 deletions

File diff suppressed because it is too large Load diff

View file

@ -330,6 +330,7 @@ struct se_geni_rsc {
#define TX_EOT (BIT(1))
#define TX_SBE (BIT(2))
#define TX_RESET_DONE (BIT(3))
#define TX_GENI_CANCEL_IRQ (BIT(14))
/* SE_DMA_RX_IRQ_STAT Register fields */
#define RX_DMA_DONE (BIT(0))
@ -338,9 +339,15 @@ struct se_geni_rsc {
#define RX_RESET_DONE (BIT(3))
#define RX_FLUSH_DONE (BIT(4))
#define RX_GENI_GP_IRQ (GENMASK(10, 5))
#define RX_GENI_CANCEL_IRQ (BIT(11))
#define RX_GENI_CANCEL_IRQ (BIT(14))
#define RX_GENI_GP_IRQ_EXT (GENMASK(13, 12))
/* DMA DEBUG Register fields */
#define DMA_TX_ACTIVE (BIT(0))
#define DMA_RX_ACTIVE (BIT(1))
#define DMA_TX_STATE (GENMASK(7, 4))
#define DMA_RX_STATE (GENMASK(11, 8))
#define DEFAULT_BUS_WIDTH (4)
#define DEFAULT_SE_CLK (19200000)