Macros to access the register of processors using the new MIPS
Multithreading ASE, also know as MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h new file mode 100644
This commit is contained in:
Ralf Baechle
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commit
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2 changed files with 369 additions and 0 deletions
367
include/asm-mips/mipsmtregs.h
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367
include/asm-mips/mipsmtregs.h
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/*
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* MT regs definitions, follows on from mipsregs.h
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* Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
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* Elizabeth Clarke et. al.
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*
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*/
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#ifndef _ASM_MIPSMTREGS_H
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#define _ASM_MIPSMTREGS_H
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#include <asm/war.h>
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#ifndef __ASSEMBLY__
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/*
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* C macros
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*/
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#define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
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#define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
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#define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
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#define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
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#define read_c0_vpecontrol() __read_32bit_c0_register($1, 1)
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#define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
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#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
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#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
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#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
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#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
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#define read_c0_tcbind() __read_32bit_c0_register($2, 2)
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#define read_c0_tccontext() __read_32bit_c0_register($2, 5)
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#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
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#else /* Assembly */
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/*
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* Macros for use in assembly language code
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*/
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#define CP0_MVPCONTROL $0,1
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#define CP0_MVPCONF0 $0,2
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#define CP0_MVPCONF1 $0,3
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#define CP0_VPECONTROL $1,1
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#define CP0_VPECONF0 $1,2
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#define CP0_VPECONF1 $1,3
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#define CP0_YQMASK $1,4
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#define CP0_VPESCHEDULE $1,5
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#define CP0_VPESCHEFBK $1,6
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#define CP0_TCSTATUS $2,1
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#define CP0_TCBIND $2,2
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#define CP0_TCRESTART $2,3
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#define CP0_TCHALT $2,4
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#define CP0_TCCONTEXT $2,5
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#define CP0_TCSCHEDULE $2,6
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#define CP0_TCSCHEFBK $2,7
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#define CP0_SRSCONF0 $6,1
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#define CP0_SRSCONF1 $6,2
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#define CP0_SRSCONF2 $6,3
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#define CP0_SRSCONF3 $6,4
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#define CP0_SRSCONF4 $6,5
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#endif
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/* MVPControl fields */
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#define MVPCONTROL_EVP (_ULCAST_(1))
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#define MVPCONTROL_VPC_SHIFT 1
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#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
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#define MVPCONTROL_STLB_SHIFT 2
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#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
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/* MVPConf0 fields */
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#define MVPCONF0_PTC_SHIFT 0
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#define MVPCONF0_PTC ( _ULCAST_(0xff))
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#define MVPCONF0_PVPE_SHIFT 10
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#define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
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#define MVPCONF0_TCA_SHIFT 15
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#define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
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#define MVPCONF0_PTLBE_SHIFT 16
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#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
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#define MVPCONF0_TLBS_SHIFT 29
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#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
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#define MVPCONF0_M_SHIFT 31
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#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
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/* config3 fields */
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#define CONFIG3_MT_SHIFT 2
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#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
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/* VPEControl fields (per VPE) */
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#define VPECONTROL_TARGTC (_ULCAST_(0xff))
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#define VPECONTROL_TE_SHIFT 15
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#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
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#define VPECONTROL_EXCPT_SHIFT 16
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#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
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/* Thread Exception Codes for EXCPT field */
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#define THREX_TU 0
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#define THREX_TO 1
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#define THREX_IYQ 2
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#define THREX_GSX 3
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#define THREX_YSCH 4
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#define THREX_GSSCH 5
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#define VPECONTROL_GSI_SHIFT 20
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#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
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#define VPECONTROL_YSI_SHIFT 21
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#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
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/* VPEConf0 fields (per VPE) */
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#define VPECONF0_VPA_SHIFT 0
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#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
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#define VPECONF0_MVP_SHIFT 1
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#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
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#define VPECONF0_XTC_SHIFT 21
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#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
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/* TCStatus fields (per TC) */
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#define TCSTATUS_TASID (_ULCAST_(0xff))
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#define TCSTATUS_IXMT_SHIFT 10
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#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
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#define TCSTATUS_TKSU_SHIFT 11
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#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
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#define TCSTATUS_A_SHIFT 13
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#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
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#define TCSTATUS_DA_SHIFT 15
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#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
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#define TCSTATUS_DT_SHIFT 20
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#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
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#define TCSTATUS_TDS_SHIFT 21
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#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
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#define TCSTATUS_TSST_SHIFT 22
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#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
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#define TCSTATUS_RNST_SHIFT 23
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#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
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/* Codes for RNST */
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#define TC_RUNNING 0
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#define TC_WAITING 1
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#define TC_YIELDING 2
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#define TC_GATED 3
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#define TCSTATUS_TMX_SHIFT 27
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#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
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/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
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/* TCBind */
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#define TCBIND_CURVPE_SHIFT 0
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#define TCBIND_CURVPE (_ULCAST_(0xf))
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#define TCBIND_CURTC_SHIFT 21
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#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
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/* TCHalt */
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#define TCHALT_H (_ULCAST_(1))
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#ifndef __ASSEMBLY__
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extern void mips_mt_regdump(void);
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static inline unsigned int dvpe(void)
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{
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int res = 0;
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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" .set mips32r2 \n"
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" move $1, %0 \n"
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" .word 0x41610001 # dvpe $1 \n"
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" ehb \n"
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" .set pop \n"
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: "=r" (res));
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instruction_hazard();
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return res;
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}
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static inline void __raw_evpe(void)
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{
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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" .set mips32r2 \n"
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" .word 0x41600021 # evpe \n"
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" ehb \n"
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" .set pop \n");
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}
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/* Enable multiMT if previous suggested it should be.
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EMT_ENABLE to force */
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#define EVPE_ENABLE MVPCONTROL_EVP
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static inline void evpe(int previous)
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{
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if ((previous & MVPCONTROL_EVP))
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__raw_evpe();
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}
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static inline unsigned int dmt(void)
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{
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int res;
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__asm__ __volatile__(
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" .set noreorder \n"
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" .set mips32r2 \n"
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" dmt %0 \n"
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" ehb \n"
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" .set mips0 \n"
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" .set reorder \n"
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: "=r" (res));
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instruction_hazard();
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return res;
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}
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static inline void __raw_emt(void)
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{
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__asm__ __volatile__(
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" .set noreorder \n"
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" .set mips32r2 \n"
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" emt \n"
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" ehb \n"
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" .set mips0 \n"
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" .set reorder");
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}
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/* enable multiVPE if previous suggested it should be.
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EVPE_ENABLE to force */
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#define EMT_ENABLE VPECONTROL_TE
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static inline void emt(int previous)
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{
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if ((previous & EMT_ENABLE))
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__raw_emt();
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}
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static inline void ehb(void)
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{
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__asm__ __volatile__("ehb");
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}
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#define mftc0(rt,sel) \
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({ \
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unsigned long __res; \
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\
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__asm__ __volatile__( \
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" .set noat\n\t" \
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" mftc0\t%0," #rt ", " #sel "\n\t" \
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" .set at\n\t" \
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: "=r" (__res)); \
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\
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__res; \
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})
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#define mftgpr(rt) \
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({ \
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unsigned long __res; \
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\
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__asm__ __volatile__( \
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" .set noat \n" \
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" mftgpr %0," #rt " \n" \
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" .set at \n" \
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: "=r" (__res)); \
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\
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__res; \
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})
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#define mftr(rt,u,sel) \
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({ \
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unsigned long __res; \
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\
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__asm__ __volatile__( \
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".set noat\n\t" \
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"mftr\t%0, " #rt ", " #u ", " #sel "\n\t" \
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".set at\n\t" \
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: "=r" (__res)); \
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\
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__res; \
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})
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#define mttgpr(rd,v) \
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({ \
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__asm__ __volatile__( \
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"mttgpr %0," #rd \
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: : "r" (v)); \
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})
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#define mttc0(rd,sel,v) \
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({ \
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__asm__ __volatile__( \
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"mttc0\t %0," #rd ", " #sel \
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: : "r" (v)); \
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})
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#define mttr(rd,u,sel,v) \
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({ \
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__asm__ __volatile__( \
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"mttr %0," #rd ", " #u ", " #sel \
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: : "r" (v)); \
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})
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#define settc(tc) \
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do { \
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write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
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ehb(); \
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} while (0)
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/* you *must* set the target tc (settc) before trying to use these */
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#define read_vpe_c0_vpecontrol() mftc0($1, 1)
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#define write_vpe_c0_vpecontrol(val) mttc0($1, 1, val)
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#define read_vpe_c0_vpeconf0() mftc0($1, 2)
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#define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val)
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#define read_vpe_c0_status() mftc0($12, 0)
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#define write_vpe_c0_status(val) mttc0($12, 0, val)
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#define read_vpe_c0_cause() mftc0($13, 0)
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#define write_vpe_c0_cause(val) mttc0($13, 0, val)
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#define read_vpe_c0_config() mftc0($16, 0)
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#define write_vpe_c0_config(val) mttc0($16, 0, val)
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#define read_vpe_c0_config1() mftc0($16, 1)
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#define write_vpe_c0_config1(val) mttc0($16, 1, val)
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#define read_vpe_c0_config7() mftc0($16, 7)
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#define write_vpe_c0_config7(val) mttc0($16, 7, val)
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#define read_vpe_c0_ebase() mftc0($15,1)
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#define write_vpe_c0_ebase(val) mttc0($15, 1, val)
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#define write_vpe_c0_compare(val) mttc0($11, 0, val)
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/* TC */
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#define read_tc_c0_tcstatus() mftc0($2, 1)
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#define write_tc_c0_tcstatus(val) mttc0($2,1,val)
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#define read_tc_c0_tcbind() mftc0($2, 2)
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#define write_tc_c0_tcbind(val) mttc0($2,2,val)
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#define read_tc_c0_tcrestart() mftc0($2, 3)
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#define write_tc_c0_tcrestart(val) mttc0($2,3,val)
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#define read_tc_c0_tchalt() mftc0($2, 4)
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#define write_tc_c0_tchalt(val) mttc0($2,4,val)
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#define read_tc_c0_tccontext() mftc0($2, 5)
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#define write_tc_c0_tccontext(val) mttc0($2,5,val)
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/* GPR */
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#define read_tc_gpr_sp() mftgpr($29)
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#define write_tc_gpr_sp(val) mttgpr($29, val)
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#define read_tc_gpr_gp() mftgpr($28)
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#define write_tc_gpr_gp(val) mttgpr($28, val)
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#endif /* Not __ASSEMBLY__ */
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#endif
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@ -37,6 +37,8 @@
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#define _ULCAST_ (unsigned long)
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#endif
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#include <asm/mipsmtregs.h>
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/*
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* Coprocessor 0 register names
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*/
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