hsu: add a periodic timer to check dma rx channel
A general problem for uart rx dma channel is you never know when and how much data will be received, so usually preset it a DMA descriptor with a big size, and rely on DMA RX timeout IRQ to know there is some data in rx channel. For a RX data size of multiple of MOTSR, there will be no timeout IRQ issued, thus OS will never be notified about that. This is a work around for that, current timer frequency is 5 times per second, it should vary according to the baud rate When future silicon version fix the problem, this workaround need be removed Signed-off-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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1 changed files with 48 additions and 4 deletions
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@ -64,6 +64,8 @@
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#define mfd_readl(obj, offset) readl(obj->reg + offset)
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#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
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#define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10)
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struct hsu_dma_buffer {
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u8 *buf;
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dma_addr_t dma_addr;
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@ -75,7 +77,8 @@ struct hsu_dma_chan {
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u32 id;
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u32 dirt; /* to or from device */
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struct uart_hsu_port *uport;
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void __iomem *reg;
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void __iomem *reg;
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struct timer_list rx_timer; /* only needed by RX channel */
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};
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struct uart_hsu_port {
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@ -377,6 +380,8 @@ void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf
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| (0x1 << 24) /* timeout bit, see HSU Errata 1 */
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);
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chan_writel(rxc, HSU_CH_CR, 0x3);
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mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
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}
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/* Protected by spin_lock_irqsave(port->lock) */
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@ -437,8 +442,13 @@ void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
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/* We can use 2 ways to calc the actual transfer len */
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count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
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if (!count)
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if (!count) {
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/* restart the channel before we leave */
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chan_writel(chan, HSU_CH_CR, 0x3);
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return;
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}
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del_timer(&chan->rx_timer);
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dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
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dbuf->dma_size, DMA_FROM_DEVICE);
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@ -463,9 +473,12 @@ void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
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| (0x1 << 16)
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| (0x1 << 24) /* timeout bit, see HSU Errata 1 */
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);
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chan_writel(chan, HSU_CH_CR, 0x3);
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tty_flip_buffer_push(tty);
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chan_writel(chan, HSU_CH_CR, 0x3);
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chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
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add_timer(&chan->rx_timer);
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}
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static void serial_hsu_stop_rx(struct uart_port *port)
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@ -893,6 +906,8 @@ static void serial_hsu_shutdown(struct uart_port *port)
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container_of(port, struct uart_hsu_port, port);
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unsigned long flags;
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del_timer_sync(&up->rxc->rx_timer);
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/* Disable interrupts from this port */
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up->ier = 0;
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serial_out(up, UART_IER, 0);
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@ -1348,6 +1363,28 @@ static int serial_hsu_probe(struct pci_dev *pdev,
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return ret;
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}
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static void hsu_dma_rx_timeout(unsigned long data)
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{
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struct hsu_dma_chan *chan = (void *)data;
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struct uart_hsu_port *up = chan->uport;
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struct hsu_dma_buffer *dbuf = &up->rxbuf;
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int count = 0;
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unsigned long flags;
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spin_lock_irqsave(&up->port.lock, flags);
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count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
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if (!count) {
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mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
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goto exit;
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}
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hsu_dma_rx(up, 0);
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exit:
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spin_unlock_irqrestore(&up->port.lock, flags);
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}
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static void hsu_global_init(void)
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{
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struct hsu_port *hsu;
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@ -1409,6 +1446,13 @@ static void hsu_global_init(void)
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dchan->uport = &hsu->port[i/2];
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dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
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i * HSU_DMA_CHANS_REG_LENGTH;
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/* Work around for RX */
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if (dchan->dirt == DMA_FROM_DEVICE) {
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init_timer(&dchan->rx_timer);
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dchan->rx_timer.function = hsu_dma_rx_timeout;
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dchan->rx_timer.data = (unsigned long)dchan;
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}
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dchan++;
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}
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