[PATCH] ppc-opc NULL noise removal
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Al Viro
Linus Torvalds
parent
0d3e8fe662
commit
66768eb26c
1 changed files with 60 additions and 59 deletions
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@ -20,6 +20,7 @@
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#include <linux/stddef.h>
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#include "nonstdio.h"
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#include "ppc.h"
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@ -110,12 +111,12 @@ const struct powerpc_operand powerpc_operands[] =
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/* The zero index is used to indicate the end of the list of
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operands. */
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#define UNUSED 0
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{ 0, 0, 0, 0, 0 },
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{ 0, 0, NULL, NULL, 0 },
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/* The BA field in an XL form instruction. */
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#define BA UNUSED + 1
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#define BA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_CR },
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{ 5, 16, NULL, NULL, PPC_OPERAND_CR },
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/* The BA field in an XL form instruction when it must be the same
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as the BT field in the same instruction. */
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@ -125,7 +126,7 @@ const struct powerpc_operand powerpc_operands[] =
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/* The BB field in an XL form instruction. */
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#define BB BAT + 1
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#define BB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_CR },
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{ 5, 11, NULL, NULL, PPC_OPERAND_CR },
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/* The BB field in an XL form instruction when it must be the same
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as the BA field in the same instruction. */
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@ -168,21 +169,21 @@ const struct powerpc_operand powerpc_operands[] =
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/* The BF field in an X or XL form instruction. */
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#define BF BDPA + 1
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{ 3, 23, 0, 0, PPC_OPERAND_CR },
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{ 3, 23, NULL, NULL, PPC_OPERAND_CR },
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/* An optional BF field. This is used for comparison instructions,
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in which an omitted BF field is taken as zero. */
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#define OBF BF + 1
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{ 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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{ 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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/* The BFA field in an X or XL form instruction. */
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#define BFA OBF + 1
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{ 3, 18, 0, 0, PPC_OPERAND_CR },
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{ 3, 18, NULL, NULL, PPC_OPERAND_CR },
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/* The BI field in a B form or XL form instruction. */
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#define BI BFA + 1
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#define BI_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_CR },
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{ 5, 16, NULL, NULL, PPC_OPERAND_CR },
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/* The BO field in a B form instruction. Certain values are
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illegal. */
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@ -197,36 +198,36 @@ const struct powerpc_operand powerpc_operands[] =
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/* The BT field in an X or XL form instruction. */
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#define BT BOE + 1
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{ 5, 21, 0, 0, PPC_OPERAND_CR },
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{ 5, 21, NULL, NULL, PPC_OPERAND_CR },
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/* The condition register number portion of the BI field in a B form
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or XL form instruction. This is used for the extended
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conditional branch mnemonics, which set the lower two bits of the
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BI field. This field is optional. */
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#define CR BT + 1
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{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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{ 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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/* The CRB field in an X form instruction. */
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#define CRB CR + 1
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{ 5, 6, 0, 0, 0 },
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{ 5, 6, NULL, NULL, 0 },
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/* The CRFD field in an X form instruction. */
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#define CRFD CRB + 1
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{ 3, 23, 0, 0, PPC_OPERAND_CR },
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{ 3, 23, NULL, NULL, PPC_OPERAND_CR },
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/* The CRFS field in an X form instruction. */
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#define CRFS CRFD + 1
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{ 3, 0, 0, 0, PPC_OPERAND_CR },
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{ 3, 0, NULL, NULL, PPC_OPERAND_CR },
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/* The CT field in an X form instruction. */
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#define CT CRFS + 1
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{ 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
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{ 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The D field in a D form instruction. This is a displacement off
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a register, and implies that the next operand is a register in
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parentheses. */
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#define D CT + 1
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{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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{ 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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/* The DE field in a DE form instruction. This is like D, but is 12
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bits only. */
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@ -252,40 +253,40 @@ const struct powerpc_operand powerpc_operands[] =
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/* The E field in a wrteei instruction. */
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#define E DS + 1
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{ 1, 15, 0, 0, 0 },
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{ 1, 15, NULL, NULL, 0 },
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/* The FL1 field in a POWER SC form instruction. */
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#define FL1 E + 1
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{ 4, 12, 0, 0, 0 },
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{ 4, 12, NULL, NULL, 0 },
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/* The FL2 field in a POWER SC form instruction. */
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#define FL2 FL1 + 1
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{ 3, 2, 0, 0, 0 },
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{ 3, 2, NULL, NULL, 0 },
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/* The FLM field in an XFL form instruction. */
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#define FLM FL2 + 1
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{ 8, 17, 0, 0, 0 },
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{ 8, 17, NULL, NULL, 0 },
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/* The FRA field in an X or A form instruction. */
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#define FRA FLM + 1
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#define FRA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_FPR },
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{ 5, 16, NULL, NULL, PPC_OPERAND_FPR },
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/* The FRB field in an X or A form instruction. */
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#define FRB FRA + 1
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#define FRB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_FPR },
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{ 5, 11, NULL, NULL, PPC_OPERAND_FPR },
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/* The FRC field in an A form instruction. */
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#define FRC FRB + 1
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#define FRC_MASK (0x1f << 6)
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{ 5, 6, 0, 0, PPC_OPERAND_FPR },
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{ 5, 6, NULL, NULL, PPC_OPERAND_FPR },
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/* The FRS field in an X form instruction or the FRT field in a D, X
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or A form instruction. */
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#define FRS FRC + 1
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#define FRT FRS
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{ 5, 21, 0, 0, PPC_OPERAND_FPR },
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{ 5, 21, NULL, NULL, PPC_OPERAND_FPR },
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/* The FXM field in an XFX instruction. */
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#define FXM FRS + 1
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@ -298,11 +299,11 @@ const struct powerpc_operand powerpc_operands[] =
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/* The L field in a D or X form instruction. */
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#define L FXM4 + 1
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{ 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
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{ 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The LEV field in a POWER SC form instruction. */
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#define LEV L + 1
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{ 7, 5, 0, 0, 0 },
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{ 7, 5, NULL, NULL, 0 },
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/* The LI field in an I form instruction. The lower two bits are
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forced to zero. */
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@ -316,24 +317,24 @@ const struct powerpc_operand powerpc_operands[] =
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/* The LS field in an X (sync) form instruction. */
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#define LS LIA + 1
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{ 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
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{ 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The MB field in an M form instruction. */
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#define MB LS + 1
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#define MB_MASK (0x1f << 6)
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{ 5, 6, 0, 0, 0 },
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{ 5, 6, NULL, NULL, 0 },
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/* The ME field in an M form instruction. */
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#define ME MB + 1
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#define ME_MASK (0x1f << 1)
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{ 5, 1, 0, 0, 0 },
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{ 5, 1, NULL, NULL, 0 },
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/* The MB and ME fields in an M form instruction expressed a single
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operand which is a bitmask indicating which bits to select. This
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is a two operand form using PPC_OPERAND_NEXT. See the
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description in opcode/ppc.h for what this means. */
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#define MBE ME + 1
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{ 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
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{ 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
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{ 32, 0, insert_mbe, extract_mbe, 0 },
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/* The MB or ME field in an MD or MDS form instruction. The high
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@ -345,7 +346,7 @@ const struct powerpc_operand powerpc_operands[] =
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/* The MO field in an mbar instruction. */
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#define MO MB6 + 1
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{ 5, 21, 0, 0, 0 },
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{ 5, 21, NULL, NULL, 0 },
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/* The NB field in an X form instruction. The value 32 is stored as
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0. */
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@ -361,34 +362,34 @@ const struct powerpc_operand powerpc_operands[] =
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/* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
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#define RA NSI + 1
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#define RA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_GPR },
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{ 5, 16, NULL, NULL, PPC_OPERAND_GPR },
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/* The RA field in the DQ form lq instruction, which has special
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value restrictions. */
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#define RAQ RA + 1
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{ 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
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{ 5, 16, insert_raq, NULL, PPC_OPERAND_GPR },
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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#define RAL RAQ + 1
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{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
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{ 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
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/* The RA field in an lmw instruction, which has special value
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restrictions. */
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#define RAM RAL + 1
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{ 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
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{ 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
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/* The RA field in a D or X form instruction which is an updating
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store or an updating floating point load, which means that the RA
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field may not be zero. */
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#define RAS RAM + 1
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{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
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{ 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
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/* The RB field in an X, XO, M, or MDS form instruction. */
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#define RB RAS + 1
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#define RB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_GPR },
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{ 5, 11, NULL, NULL, PPC_OPERAND_GPR },
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/* The RB field in an X form instruction when it must be the same as
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the RS field in the instruction. This is used for extended
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@ -402,22 +403,22 @@ const struct powerpc_operand powerpc_operands[] =
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#define RS RBS + 1
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#define RT RS
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#define RT_MASK (0x1f << 21)
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{ 5, 21, 0, 0, PPC_OPERAND_GPR },
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{ 5, 21, NULL, NULL, PPC_OPERAND_GPR },
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/* The RS field of the DS form stq instruction, which has special
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value restrictions. */
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#define RSQ RS + 1
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{ 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
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{ 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR },
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/* The RT field of the DQ form lq instruction, which has special
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value restrictions. */
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#define RTQ RSQ + 1
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{ 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
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{ 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR },
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/* The SH field in an X or M form instruction. */
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#define SH RTQ + 1
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#define SH_MASK (0x1f << 11)
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{ 5, 11, 0, 0, 0 },
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{ 5, 11, NULL, NULL, 0 },
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/* The SH field in an MD form instruction. This is split. */
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#define SH6 SH + 1
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@ -426,12 +427,12 @@ const struct powerpc_operand powerpc_operands[] =
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/* The SI field in a D form instruction. */
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#define SI SH6 + 1
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED },
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{ 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
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/* The SI field in a D form instruction when we accept a wide range
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of positive values. */
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#define SISIGNOPT SI + 1
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{ 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
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{ 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
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/* The SPR field in an XFX form instruction. This is flipped--the
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lower 5 bits are stored in the upper 5 and vice- versa. */
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@ -443,25 +444,25 @@ const struct powerpc_operand powerpc_operands[] =
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/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
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#define SPRBAT SPR + 1
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#define SPRBAT_MASK (0x3 << 17)
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{ 2, 17, 0, 0, 0 },
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{ 2, 17, NULL, NULL, 0 },
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/* The SPRG register number in an XFX form m[ft]sprg instruction. */
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#define SPRG SPRBAT + 1
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#define SPRG_MASK (0x3 << 16)
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{ 2, 16, 0, 0, 0 },
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{ 2, 16, NULL, NULL, 0 },
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/* The SR field in an X form instruction. */
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#define SR SPRG + 1
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{ 4, 16, 0, 0, 0 },
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{ 4, 16, NULL, NULL, 0 },
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/* The STRM field in an X AltiVec form instruction. */
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#define STRM SR + 1
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#define STRM_MASK (0x3 << 21)
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{ 2, 21, 0, 0, 0 },
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{ 2, 21, NULL, NULL, 0 },
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/* The SV field in a POWER SC form instruction. */
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#define SV STRM + 1
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{ 14, 2, 0, 0, 0 },
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{ 14, 2, NULL, NULL, 0 },
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/* The TBR field in an XFX form instruction. This is like the SPR
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field, but it is optional. */
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@ -471,52 +472,52 @@ const struct powerpc_operand powerpc_operands[] =
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/* The TO field in a D or X form instruction. */
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#define TO TBR + 1
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#define TO_MASK (0x1f << 21)
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{ 5, 21, 0, 0, 0 },
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{ 5, 21, NULL, NULL, 0 },
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/* The U field in an X form instruction. */
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#define U TO + 1
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{ 4, 12, 0, 0, 0 },
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{ 4, 12, NULL, NULL, 0 },
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/* The UI field in a D form instruction. */
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#define UI U + 1
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{ 16, 0, 0, 0, 0 },
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{ 16, 0, NULL, NULL, 0 },
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/* The VA field in a VA, VX or VXR form instruction. */
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#define VA UI + 1
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#define VA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_VR },
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{ 5, 16, NULL, NULL, PPC_OPERAND_VR },
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/* The VB field in a VA, VX or VXR form instruction. */
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#define VB VA + 1
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#define VB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_VR },
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{ 5, 11, NULL, NULL, PPC_OPERAND_VR },
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/* The VC field in a VA form instruction. */
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#define VC VB + 1
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#define VC_MASK (0x1f << 6)
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{ 5, 6, 0, 0, PPC_OPERAND_VR },
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{ 5, 6, NULL, NULL, PPC_OPERAND_VR },
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/* The VD or VS field in a VA, VX, VXR or X form instruction. */
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#define VD VC + 1
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#define VS VD
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#define VD_MASK (0x1f << 21)
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{ 5, 21, 0, 0, PPC_OPERAND_VR },
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{ 5, 21, NULL, NULL, PPC_OPERAND_VR },
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/* The SIMM field in a VX form instruction. */
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#define SIMM VD + 1
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{ 5, 16, 0, 0, PPC_OPERAND_SIGNED},
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{ 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
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/* The UIMM field in a VX form instruction. */
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#define UIMM SIMM + 1
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{ 5, 16, 0, 0, 0 },
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{ 5, 16, NULL, NULL, 0 },
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/* The SHB field in a VA form instruction. */
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#define SHB UIMM + 1
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{ 4, 6, 0, 0, 0 },
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{ 4, 6, NULL, NULL, 0 },
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/* The other UIMM field in a EVX form instruction. */
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#define EVUIMM SHB + 1
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{ 5, 11, 0, 0, 0 },
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{ 5, 11, NULL, NULL, 0 },
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/* The other UIMM field in a half word EVX form instruction. */
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#define EVUIMM_2 EVUIMM + 1
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@ -533,11 +534,11 @@ const struct powerpc_operand powerpc_operands[] =
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/* The WS field. */
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#define WS EVUIMM_8 + 1
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#define WS_MASK (0x7 << 11)
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{ 3, 11, 0, 0, 0 },
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{ 3, 11, NULL, NULL, 0 },
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/* The L field in an mtmsrd instruction */
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#define MTMSRD_L WS + 1
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{ 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
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{ 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
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};
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