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Switch SiByte drivers back to __raw_*() functions.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki 2005-02-22 21:51:30 +00:00 committed by Ralf Baechle
parent 4912ba72d6
commit 65bda1a95d
11 changed files with 221 additions and 210 deletions
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28
arch/mips/mm/pg-sb1.c
View file

@ -214,12 +214,12 @@ void sb1_dma_init(void)
int cpu = smp_processor_id();
u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1);
bus_writeq(base_val,
(void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
bus_writeq(base_val | M_DM_DSCR_BASE_RESET,
(void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
bus_writeq(base_val | M_DM_DSCR_BASE_ENABL,
(void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
__raw_writeq(base_val,
IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
__raw_writeq(base_val | M_DM_DSCR_BASE_RESET,
IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
__raw_writeq(base_val | M_DM_DSCR_BASE_ENABL,
IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
}
void clear_page(void *page)
@ -232,16 +232,16 @@ void clear_page(void *page)
page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
/*
* Don't really want to do it this way, but there's no
* reliable way to delay completion detection.
*/
while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) &
M_DM_DSCR_BASE_INTERRUPT))))
while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
M_DM_DSCR_BASE_INTERRUPT)))
;
bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
}
void copy_page(void *to, void *from)
@ -257,16 +257,16 @@ void copy_page(void *to, void *from)
page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
/*
* Don't really want to do it this way, but there's no
* reliable way to delay completion detection.
*/
while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) &
M_DM_DSCR_BASE_INTERRUPT))))
while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) &
M_DM_DSCR_BASE_INTERRUPT)))
;
bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
}
#else /* !CONFIG_SIBYTE_DMA_PAGEOPS */

130
arch/mips/sibyte/sb1250/bcm1250_tbprof.c
View file

@ -65,24 +65,25 @@ static void arm_tb(void)
u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
/* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
trigger start of trace. XXX vary sampling period */
bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
__raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
/* Unfortunately, in Pass 2 we must clear all counters to knock down
a previous interrupt request. This means that bus profiling
requires ALL of the SCD perf counters. */
bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is
M_SPC_CFG_ENABLE | // enable counting
M_SPC_CFG_CLEAR | // clear all counters
V_SPC_CFG_SRC1(1), // counter 1 counts cycles
IOADDR(A_SCD_PERF_CNT_CFG));
bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
__raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
// keep counters 0,2,3 as is
M_SPC_CFG_ENABLE | // enable counting
M_SPC_CFG_CLEAR | // clear all counters
V_SPC_CFG_SRC1(1), // counter 1 counts cycles
IOADDR(A_SCD_PERF_CNT_CFG));
__raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
/* Reset the trace buffer */
bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
__raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
/* XXXKW may want to expose control to the data-collector */
tb_options |= M_SCD_TRACE_CFG_FORCECNT;
#endif
bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
__raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
sbp.tb_armed = 1;
}
@ -94,23 +95,30 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
/* XXX should use XKPHYS to make writes bypass L2 */
u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
/* Read out trace */
bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
__raw_writeq(M_SCD_TRACE_CFG_START_READ,
IOADDR(A_SCD_TRACE_CFG));
__asm__ __volatile__ ("sync" : : : "memory");
/* Loop runs backwards because bundles are read out in reverse order */
for (i = 256 * 6; i > 0; i -= 6) {
// Subscripts decrease to put bundle in the order
// t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi
p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo
p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi
p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo
p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi
p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo
p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
// read t2 hi
p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
// read t2 lo
p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
// read t1 hi
p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
// read t1 lo
p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
// read t0 hi
p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
// read t0 lo
}
if (!sbp.tb_enable) {
DBG(printk(DEVNAME ": tb_intr shutdown\n"));
bus_writeq(M_SCD_TRACE_CFG_RESET,
IOADDR(A_SCD_TRACE_CFG));
__raw_writeq(M_SCD_TRACE_CFG_RESET,
IOADDR(A_SCD_TRACE_CFG));
sbp.tb_armed = 0;
wake_up(&sbp.tb_sync);
} else {
@ -119,7 +127,7 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
} else {
/* No more trace buffer samples */
DBG(printk(DEVNAME ": tb_intr full\n"));
bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
__raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
sbp.tb_armed = 0;
if (!sbp.tb_enable) {
wake_up(&sbp.tb_sync);
@ -153,13 +161,11 @@ int sbprof_zbprof_start(struct file *filp)
return -EBUSY;
}
/* Make sure there isn't a perf-cnt interrupt waiting */
scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
/* Disable and clear counters, override SRC_1 */
bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
M_SPC_CFG_ENABLE |
M_SPC_CFG_CLEAR |
V_SPC_CFG_SRC1(1),
IOADDR(A_SCD_PERF_CNT_CFG));
__raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
IOADDR(A_SCD_PERF_CNT_CFG));
/* We grab this interrupt to prevent others from trying to use
it, even though we don't want to service the interrupts
@ -173,55 +179,55 @@ int sbprof_zbprof_start(struct file *filp)
/* I need the core to mask these, but the interrupt mapper to
pass them through. I am exploiting my knowledge that
cp0_status masks out IP[5]. krw */
bus_writeq(K_INT_MAP_I3,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_PERF_CNT << 3)));
__raw_writeq(K_INT_MAP_I3,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_PERF_CNT << 3)));
/* Initialize address traps */
bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
__raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
/* Initialize Trace Event 0-7 */
// when interrupt
bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
__raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
__raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
/* Initialize Trace Sequence 0-7 */
// Start on event 0 (interrupt)
bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
IOADDR(A_SCD_TRACE_SEQUENCE_0));
__raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
IOADDR(A_SCD_TRACE_SEQUENCE_0));
// dsamp when d used | asamp when a used
bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
K_SCD_TRSEQ_TRIGGER_ALL,
IOADDR(A_SCD_TRACE_SEQUENCE_1));
bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
__raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
K_SCD_TRSEQ_TRIGGER_ALL,
IOADDR(A_SCD_TRACE_SEQUENCE_1));
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
/* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
bus_writeq((1ULL << K_INT_PERF_CNT),
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
__raw_writeq(1ULL << K_INT_PERF_CNT,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
arm_tb();

2
arch/mips/sibyte/sb1250/bus_watcher.c
View file

@ -189,7 +189,7 @@ static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs)
for (i=0; i<256*6; i++)
printk("%016llx\n",
(unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ)));
(long long)__raw_readq(IOADDR(A_SCD_TRACE_READ)));
csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));

88
arch/mips/sibyte/sb1250/irq.c
View file

@ -96,11 +96,11 @@ void sb1250_mask_irq(int cpu, int irq)
u64 cur_ints;
spin_lock_irqsave(&sb1250_imr_lock, flags);
cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints |= (((u64) 1) << irq);
__bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}
@ -110,11 +110,11 @@ void sb1250_unmask_irq(int cpu, int irq)
u64 cur_ints;
spin_lock_irqsave(&sb1250_imr_lock, flags);
cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints &= ~(((u64) 1) << irq);
__bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}
@ -149,23 +149,23 @@ static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
/* Swizzle each CPU's IMR (but leave the IP selection alone) */
old_cpu = sb1250_irq_owner[irq];
cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
R_IMR_INTERRUPT_MASK));
int_on = !(cur_ints & (((u64) 1) << irq));
if (int_on) {
/* If it was on, mask it */
cur_ints |= (((u64) 1) << irq);
__bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
R_IMR_INTERRUPT_MASK));
____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
R_IMR_INTERRUPT_MASK));
}
sb1250_irq_owner[irq] = cpu;
if (int_on) {
/* unmask for the new CPU */
cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints &= ~(((u64) 1) << irq);
__bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
}
spin_unlock(&sb1250_imr_lock);
spin_unlock_irqrestore(&desc->lock, flags);
@ -208,8 +208,8 @@ static void ack_sb1250_irq(unsigned int irq)
* deliver the interrupts to all CPUs (which makes affinity
* changing easier for us)
*/
pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
R_IMR_LDT_INTERRUPT)));
pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
R_IMR_LDT_INTERRUPT)));
pending &= ((u64)1 << (irq));
if (pending) {
int i;
@ -224,8 +224,8 @@ static void ack_sb1250_irq(unsigned int irq)
* Clear for all CPUs so an affinity switch
* doesn't find an old status
*/
bus_writeq(pending,
IOADDR(A_IMR_REGISTER(cpu,
__raw_writeq(pending,
IOADDR(A_IMR_REGISTER(cpu,
R_IMR_LDT_INTERRUPT_CLR)));
}
@ -340,12 +340,14 @@ void __init arch_init_irq(void)
/* Default everything to IP2 */
for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
bus_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
bus_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
}
init_sb1250_irqs();
@ -355,23 +357,23 @@ void __init arch_init_irq(void)
* inter-cpu messages
*/
/* Was I1 */
bus_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
bus_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
/* Clear the mailboxes. The firmware may leave them dirty */
bus_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
bus_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
sb1250_steal_irq(K_INT_MBOX_0);
@ -396,12 +398,14 @@ void __init arch_init_irq(void)
sb1250_duart_present[kgdb_port] = 0;
#endif
/* Setup uart 1 settings, mapper */
bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
__raw_writeq(M_DUART_IMR_BRK,
IOADDR(A_DUART_IMRREG(kgdb_port)));
sb1250_steal_irq(kgdb_irq);
bus_writeq(IMR_IP6_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(kgdb_irq<<3)));
__raw_writeq(IMR_IP6_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(kgdb_irq << 3)));
sb1250_unmask_irq(0, kgdb_irq);
}
#endif

4
arch/mips/sibyte/sb1250/setup.c
View file

@ -153,7 +153,7 @@ void sb1250_setup(void)
int bad_config = 0;
sb1_pass = read_c0_prid() & 0xff;
sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION));
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
soc_type = SYS_SOC_TYPE(sys_rev);
soc_pass = G_SYS_REVISION(sys_rev);
@ -162,7 +162,7 @@ void sb1250_setup(void)
machine_restart(NULL);
}
plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG)));
plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",

18
arch/mips/sibyte/sb1250/smp.c
View file

@ -29,18 +29,18 @@
#include <asm/sibyte/sb1250_int.h>
static void *mailbox_set_regs[] = {
(void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
(void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
};
static void *mailbox_clear_regs[] = {
(void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
(void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
};
static void *mailbox_regs[] = {
(void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
(void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
};
/*
@ -73,7 +73,7 @@ void sb1250_smp_finish(void)
*/
void core_send_ipi(int cpu, unsigned int action)
{
bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
__raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
}
void sb1250_mailbox_interrupt(struct pt_regs *regs)
@ -83,10 +83,10 @@ void sb1250_mailbox_interrupt(struct pt_regs *regs)
kstat_this_cpu.irqs[K_INT_MBOX_0]++;
/* Load the mailbox register to figure out what we're supposed to do */
action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
/* Clear the mailbox to clear the interrupt */
__bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
/*
* Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the

26
arch/mips/sibyte/sb1250/time.c
View file

@ -67,24 +67,24 @@ void sb1250_time_init(void)
sb1250_mask_irq(cpu, irq);
/* Map the timer interrupt to ip[4] of this cpu */
bus_writeq(IMR_IP4_VAL,
IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
(irq << 3)));
__raw_writeq(IMR_IP4_VAL,
IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
(irq << 3)));
/* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
/* Disable the timer and set up the count */
bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
#ifdef CONFIG_SIMULATION
bus_writeq(50000 / HZ,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
__raw_writeq(50000 / HZ,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#else
bus_writeq(1000000/HZ,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
__raw_writeq(1000000 / HZ,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#endif
/* Set the timer running */
bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
sb1250_unmask_irq(cpu, irq);
sb1250_steal_irq(irq);
@ -105,8 +105,8 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
int irq = K_INT_TIMER_0 + cpu;
/* Reset the timer */
__bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
/*
* CPU 0 handles the global timer interrupt job
@ -130,7 +130,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
unsigned long sb1250_gettimeoffset(void)
{
unsigned long count =
bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
return 1000000/HZ - count;
}

47
arch/mips/sibyte/swarm/rtc_m41t81.c
View file

@ -82,59 +82,60 @@
#define M41T81REG_SQW 0x13 /* square wave register */
#define M41T81_CCR_ADDRESS 0x68
#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
static int m41t81_read(uint8_t addr)
{
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE),
SMB_CSR(R_SMB_START));
__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
SMB_CSR(R_SMB_START));
__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
}
return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
}
static int m41t81_write(uint8_t addr, int b)
{
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD));
bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA));
bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
SMB_CSR(R_SMB_START));
__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
__raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
}
/* read the same byte again to make sure it is written */
bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
SMB_CSR(R_SMB_START));
__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
return 0;

42
arch/mips/sibyte/swarm/rtc_xicor1241.c
View file

@ -57,52 +57,52 @@
#define X1241_CCR_ADDRESS 0x6F
#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
static int xicor_read(uint8_t addr)
{
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
SMB_CSR(R_SMB_START));
__raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
SMB_CSR(R_SMB_START));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
}
return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
}
static int xicor_write(uint8_t addr, int b)
{
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq(addr, SMB_CSR(R_SMB_CMD));
bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
SMB_CSR(R_SMB_START));
__raw_writeq(addr, SMB_CSR(R_SMB_CMD));
__raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
} else {
return 0;

44
arch/mips/sibyte/swarm/time.c
View file

@ -79,48 +79,48 @@ static unsigned int usec_bias = 0;
static int xicor_read(uint8_t addr)
{
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
SMB_CSR(R_SMB_START));
__raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
SMB_CSR(R_SMB_START));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
}
return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
}
static int xicor_write(uint8_t addr, int b)
{
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
bus_writeq(addr, SMB_CSR(R_SMB_CMD));
bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
SMB_CSR(R_SMB_START));
__raw_writeq(addr, SMB_CSR(R_SMB_CMD));
__raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
__raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
SMB_CSR(R_SMB_START));
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
} else {
return 0;
@ -228,8 +228,8 @@ void __init swarm_time_init(void)
/* Establish communication with the Xicor 1241 RTC */
/* XXXKW how do I share the SMBus with the I2C subsystem? */
bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
bus_writeq(0, SMB_CSR(R_SMB_CONTROL));
__raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
__raw_writeq(0, SMB_CSR(R_SMB_CONTROL));
if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
printk("x1241: couldn't detect on SWARM SMBus 1\n");

2
include/asm-mips/sibyte/sb1250.h
View file

@ -58,6 +58,6 @@ extern void prom_printf(char *fmt, ...);
#endif
#define IOADDR(a) (IO_BASE + (a))
#define IOADDR(a) ((void *)(IO_BASE + (a)))
#endif