net: sh_eth: Add support SH7724
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yoshihiro Shimoda
David S. Miller
parent
380af9e390
commit
65ac885149
3 changed files with 111 additions and 6 deletions
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@ -516,15 +516,16 @@ config STNIC
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config SH_ETH
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tristate "Renesas SuperH Ethernet support"
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depends on SUPERH && \
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(CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763 || \
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CPU_SUBTYPE_SH7619)
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(CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || \
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CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7619 || \
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CPU_SUBTYPE_SH7724)
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select CRC32
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select MII
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select MDIO_BITBANG
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select PHYLIB
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help
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Renesas SuperH Ethernet device driver.
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This driver support SH7710, SH7712, SH7763 and SH7619.
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This driver support SH7710, SH7712, SH7763, SH7619, and SH7724.
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config SUNLANCE
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tristate "Sun LANCE support"
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@ -34,7 +34,57 @@
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#include "sh_eth.h"
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/* There is CPU dependent code */
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#if defined(CONFIG_CPU_SUBTYPE_SH7763)
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#if defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define SH_ETH_RESET_DEFAULT 1
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static void sh_eth_set_duplex(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u32 ioaddr = ndev->base_addr;
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if (mdp->duplex) /* Full */
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ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
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else /* Half */
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ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
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}
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static void sh_eth_set_rate(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u32 ioaddr = ndev->base_addr;
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switch (mdp->speed) {
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case 10: /* 10BASE */
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ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
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break;
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case 100:/* 100BASE */
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ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
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break;
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default:
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break;
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}
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}
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/* SH7724 */
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static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
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.set_duplex = sh_eth_set_duplex,
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.set_rate = sh_eth_set_rate,
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.ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
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.ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
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.eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
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.tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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.eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
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EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
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.tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
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.apr = 1,
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.mpr = 1,
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.tpauser = 1,
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.hw_swap = 1,
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};
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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#define SH_ETH_HAS_TSU 1
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static void sh_eth_chip_reset(struct net_device *ndev)
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{
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@ -40,6 +40,8 @@
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#define PKT_BUF_SZ 1538
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#if defined(CONFIG_CPU_SUBTYPE_SH7763)
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/* This CPU register maps is very difference by other SH4 CPU */
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/* Chip Base Address */
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# define SH_TSU_ADDR 0xFEE01800
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# define ARSTR SH_TSU_ADDR
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@ -141,7 +143,59 @@
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# define FWNLCR1 0xB0
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# define FWALCR1 0x40
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#else /* #elif defined(CONFIG_CPU_SUBTYPE_SH7763) */
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#elif defined(CONFIG_CPU_SH4) /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */
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/* EtherC */
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#define ECMR 0x100
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#define RFLR 0x108
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#define ECSR 0x110
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#define ECSIPR 0x118
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#define PIR 0x120
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#define PSR 0x128
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#define RDMLR 0x140
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#define IPGR 0x150
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#define APR 0x154
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#define MPR 0x158
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#define TPAUSER 0x164
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#define RFCF 0x160
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#define TPAUSECR 0x168
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#define BCFRR 0x16c
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#define MAHR 0x1c0
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#define MALR 0x1c8
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#define TROCR 0x1d0
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#define CDCR 0x1d4
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#define LCCR 0x1d8
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#define CNDCR 0x1dc
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#define CEFCR 0x1e4
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#define FRECR 0x1e8
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#define TSFRCR 0x1ec
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#define TLFRCR 0x1f0
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#define RFCR 0x1f4
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#define MAFCR 0x1f8
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#define RTRATE 0x1fc
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/* E-DMAC */
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#define EDMR 0x000
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#define EDTRR 0x008
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#define EDRRR 0x010
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#define TDLAR 0x018
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#define RDLAR 0x020
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#define EESR 0x028
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#define EESIPR 0x030
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#define TRSCER 0x038
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#define RMFCR 0x040
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#define TFTR 0x048
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#define FDR 0x050
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#define RMCR 0x058
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#define TFUCR 0x064
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#define RFOCR 0x068
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#define FCFTR 0x070
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#define RPADIR 0x078
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#define TRIMD 0x07c
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#define RBWAR 0x0c8
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#define RDFAR 0x0cc
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#define TBRAR 0x0d4
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#define TDFAR 0x0d8
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#else /* #elif defined(CONFIG_CPU_SH4) */
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/* This section is SH3 or SH2 */
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#ifndef CONFIG_CPU_SUBTYPE_SH7619
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/* Chip base address */
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@ -426,7 +480,7 @@ enum FELIC_MODE_BIT {
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ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
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ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
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ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
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ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
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ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
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ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
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};
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