[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
424b28ba4d
commit
641e97f318
11 changed files with 54 additions and 577 deletions
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@ -746,14 +746,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
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{
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decode_configs(c);
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/*
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* For historical reasons the SB1 comes with it's own variant of
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* cache code which eventually will be folded into c-r4k.c. Until
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* then we pretend it's got it's own cache architecture.
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*/
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c->options &= ~MIPS_CPU_4K_CACHE;
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c->options |= MIPS_CPU_SB1_CACHE;
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_SB1:
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c->cputype = CPU_SB1;
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@ -1435,6 +1435,9 @@ void __init set_handler (unsigned long offset, void *addr, unsigned long size)
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flush_icache_range(ebase + offset, ebase + offset + size);
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}
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static char panic_null_cerr[] __initdata =
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"Trying to set NULL cache error exception handler";
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/* Install uncached CPU exception handler */
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void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
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{
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@ -1445,6 +1448,9 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
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unsigned long uncached_ebase = TO_UNCAC(ebase);
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#endif
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if (!addr)
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panic(panic_null_cerr);
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memcpy((void *)(uncached_ebase + offset), addr, size);
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}
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@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o
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obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \
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obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o pg-sb1.o \
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tlb-r4k.o
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obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o
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obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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@ -9,6 +9,7 @@
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/linkage.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/bitops.h>
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@ -948,12 +949,16 @@ static void __init probe_pcache(void)
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switch (c->cputype) {
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case CPU_20KC:
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case CPU_25KF:
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case CPU_SB1:
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case CPU_SB1A:
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c->dcache.flags |= MIPS_CACHE_PINDEX;
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break;
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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case CPU_SB1:
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break;
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case CPU_24K:
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case CPU_34K:
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case CPU_74K:
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@ -1235,11 +1240,20 @@ void __init r4k_cache_init(void)
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{
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extern void build_clear_page(void);
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extern void build_copy_page(void);
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extern char except_vec2_generic;
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extern char __weak except_vec2_generic;
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extern char __weak except_vec2_sb1;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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/* Default cache error handler for R4000 and R5000 family */
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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switch (c->cputype) {
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case CPU_SB1:
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case CPU_SB1A:
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set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
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break;
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default:
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set_uncached_handler(0x100, &except_vec2_generic, 0x80);
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break;
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}
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probe_pcache();
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setup_scache();
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@ -1,535 +0,0 @@
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/*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
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* Copyright (C) 2004 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/init.h>
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#include <linux/hardirq.h>
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#include <asm/asm.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/uaccess.h>
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extern void sb1_dma_init(void);
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/* These are probed at ld_mmu time */
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static unsigned long icache_size;
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static unsigned long dcache_size;
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static unsigned short icache_line_size;
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static unsigned short dcache_line_size;
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static unsigned int icache_index_mask;
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static unsigned int dcache_index_mask;
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static unsigned short icache_assoc;
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static unsigned short dcache_assoc;
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static unsigned short icache_sets;
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static unsigned short dcache_sets;
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static unsigned int icache_range_cutoff;
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static unsigned int dcache_range_cutoff;
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static inline void sb1_on_each_cpu(void (*func) (void *info), void *info,
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int retry, int wait)
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{
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preempt_disable();
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smp_call_function(func, info, retry, wait);
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func(info);
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preempt_enable();
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}
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/*
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* The dcache is fully coherent to the system, with one
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* big caveat: the instruction stream. In other words,
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* if we miss in the icache, and have dirty data in the
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* L1 dcache, then we'll go out to memory (or the L2) and
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* get the not-as-recent data.
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*
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* So the only time we have to flush the dcache is when
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* we're flushing the icache. Since the L2 is fully
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* coherent to everything, including I/O, we never have
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* to flush it
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*/
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#define cache_set_op(op, addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips64\n\t \n" \
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" cache %0, (0<<13)(%1) \n" \
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" cache %0, (1<<13)(%1) \n" \
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" cache %0, (2<<13)(%1) \n" \
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" cache %0, (3<<13)(%1) \n" \
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" .set mips0 \n" \
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" .set reorder" \
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: \
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: "i" (op), "r" (addr))
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#define sync() \
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__asm__ __volatile( \
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" .set mips64\n\t \n" \
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" sync \n" \
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" .set mips0")
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#define mispredict() \
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__asm__ __volatile__( \
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" bnezl $0, 1f \n" /* Force mispredict */ \
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"1: \n");
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/*
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* Writeback and invalidate the entire dcache
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*/
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static inline void __sb1_writeback_inv_dcache_all(void)
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{
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unsigned long addr = 0;
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while (addr < dcache_line_size * dcache_sets) {
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cache_set_op(Index_Writeback_Inv_D, addr);
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addr += dcache_line_size;
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}
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}
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/*
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* Writeback and invalidate a range of the dcache. The addresses are
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* virtual, and since we're using index ops and bit 12 is part of both
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* the virtual frame and physical index, we have to clear both sets
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* (bit 12 set and cleared).
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*/
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static inline void __sb1_writeback_inv_dcache_range(unsigned long start,
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unsigned long end)
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{
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unsigned long index;
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start &= ~(dcache_line_size - 1);
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end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
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while (start != end) {
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index = start & dcache_index_mask;
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cache_set_op(Index_Writeback_Inv_D, index);
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cache_set_op(Index_Writeback_Inv_D, index ^ (1<<12));
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start += dcache_line_size;
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}
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sync();
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}
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/*
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* Writeback and invalidate a range of the dcache. With physical
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* addresseses, we don't have to worry about possible bit 12 aliasing.
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* XXXKW is it worth turning on KX and using hit ops with xkphys?
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*/
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static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start,
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unsigned long end)
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{
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start &= ~(dcache_line_size - 1);
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end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
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while (start != end) {
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cache_set_op(Index_Writeback_Inv_D, start & dcache_index_mask);
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start += dcache_line_size;
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}
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sync();
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}
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/*
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* Invalidate the entire icache
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*/
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static inline void __sb1_flush_icache_all(void)
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{
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unsigned long addr = 0;
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while (addr < icache_line_size * icache_sets) {
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cache_set_op(Index_Invalidate_I, addr);
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addr += icache_line_size;
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}
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}
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/*
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* Invalidate a range of the icache. The addresses are virtual, and
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* the cache is virtually indexed and tagged. However, we don't
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* necessarily have the right ASID context, so use index ops instead
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* of hit ops.
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*/
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static inline void __sb1_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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start &= ~(icache_line_size - 1);
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end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
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while (start != end) {
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cache_set_op(Index_Invalidate_I, start & icache_index_mask);
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start += icache_line_size;
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}
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mispredict();
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sync();
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}
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/*
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* Flush the icache for a given physical page. Need to writeback the
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* dcache first, then invalidate the icache. If the page isn't
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* executable, nothing is required.
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*/
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static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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{
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int cpu = smp_processor_id();
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#ifndef CONFIG_SMP
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if (!(vma->vm_flags & VM_EXEC))
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return;
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#endif
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__sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
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/*
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* Bumping the ASID is probably cheaper than the flush ...
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*/
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if (vma->vm_mm == current->active_mm) {
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if (cpu_context(cpu, vma->vm_mm) != 0)
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drop_mmu_context(vma->vm_mm, cpu);
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} else
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__sb1_flush_icache_range(addr, addr + PAGE_SIZE);
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}
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#ifdef CONFIG_SMP
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struct flush_cache_page_args {
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struct vm_area_struct *vma;
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unsigned long addr;
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unsigned long pfn;
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};
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static void sb1_flush_cache_page_ipi(void *info)
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{
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struct flush_cache_page_args *args = info;
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local_sb1_flush_cache_page(args->vma, args->addr, args->pfn);
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}
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/* Dirty dcache could be on another CPU, so do the IPIs */
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static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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{
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struct flush_cache_page_args args;
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if (!(vma->vm_flags & VM_EXEC))
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return;
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addr &= PAGE_MASK;
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args.vma = vma;
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args.addr = addr;
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args.pfn = pfn;
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sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
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}
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#else
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void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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__attribute__((alias("local_sb1_flush_cache_page")));
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#endif
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#ifdef CONFIG_SMP
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static void sb1_flush_cache_data_page_ipi(void *info)
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{
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unsigned long start = (unsigned long)info;
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__sb1_writeback_inv_dcache_range(start, start + PAGE_SIZE);
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}
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static void sb1_flush_cache_data_page(unsigned long addr)
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{
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if (in_atomic())
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__sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
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else
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on_each_cpu(sb1_flush_cache_data_page_ipi, (void *) addr, 1, 1);
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}
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#else
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static void local_sb1_flush_cache_data_page(unsigned long addr)
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{
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__sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
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}
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void sb1_flush_cache_data_page(unsigned long)
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__attribute__((alias("local_sb1_flush_cache_data_page")));
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#endif
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/*
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* Invalidate all caches on this CPU
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*/
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static void __used local_sb1___flush_cache_all(void)
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{
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__sb1_writeback_inv_dcache_all();
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__sb1_flush_icache_all();
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}
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#ifdef CONFIG_SMP
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void sb1___flush_cache_all_ipi(void *ignored)
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__attribute__((alias("local_sb1___flush_cache_all")));
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static void sb1___flush_cache_all(void)
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{
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sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
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}
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#else
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void sb1___flush_cache_all(void)
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__attribute__((alias("local_sb1___flush_cache_all")));
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#endif
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/*
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* When flushing a range in the icache, we have to first writeback
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* the dcache for the same range, so new ifetches will see any
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* data that was dirty in the dcache.
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*
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* The start/end arguments are Kseg addresses (possibly mapped Kseg).
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*/
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static void local_sb1_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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/* Just wb-inv the whole dcache if the range is big enough */
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if ((end - start) > dcache_range_cutoff)
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__sb1_writeback_inv_dcache_all();
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else
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__sb1_writeback_inv_dcache_range(start, end);
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/* Just flush the whole icache if the range is big enough */
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if ((end - start) > icache_range_cutoff)
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__sb1_flush_icache_all();
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else
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__sb1_flush_icache_range(start, end);
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}
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#ifdef CONFIG_SMP
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struct flush_icache_range_args {
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unsigned long start;
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unsigned long end;
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};
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static void sb1_flush_icache_range_ipi(void *info)
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{
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struct flush_icache_range_args *args = info;
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local_sb1_flush_icache_range(args->start, args->end);
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}
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void sb1_flush_icache_range(unsigned long start, unsigned long end)
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{
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struct flush_icache_range_args args;
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args.start = start;
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args.end = end;
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sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
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}
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#else
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void sb1_flush_icache_range(unsigned long start, unsigned long end)
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__attribute__((alias("local_sb1_flush_icache_range")));
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#endif
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/*
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* A signal trampoline must fit into a single cacheline.
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*/
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static void local_sb1_flush_cache_sigtramp(unsigned long addr)
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{
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cache_set_op(Index_Writeback_Inv_D, addr & dcache_index_mask);
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cache_set_op(Index_Writeback_Inv_D, (addr ^ (1<<12)) & dcache_index_mask);
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cache_set_op(Index_Invalidate_I, addr & icache_index_mask);
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mispredict();
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}
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|
||||
#ifdef CONFIG_SMP
|
||||
static void sb1_flush_cache_sigtramp_ipi(void *info)
|
||||
{
|
||||
unsigned long iaddr = (unsigned long) info;
|
||||
local_sb1_flush_cache_sigtramp(iaddr);
|
||||
}
|
||||
|
||||
static void sb1_flush_cache_sigtramp(unsigned long addr)
|
||||
{
|
||||
sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
|
||||
}
|
||||
#else
|
||||
void sb1_flush_cache_sigtramp(unsigned long addr)
|
||||
__attribute__((alias("local_sb1_flush_cache_sigtramp")));
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Anything that just flushes dcache state can be ignored, as we're always
|
||||
* coherent in dcache space. This is just a dummy function that all the
|
||||
* nop'ed routines point to
|
||||
*/
|
||||
static void sb1_nop(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Cache set values (from the mips64 spec)
|
||||
* 0 - 64
|
||||
* 1 - 128
|
||||
* 2 - 256
|
||||
* 3 - 512
|
||||
* 4 - 1024
|
||||
* 5 - 2048
|
||||
* 6 - 4096
|
||||
* 7 - Reserved
|
||||
*/
|
||||
|
||||
static unsigned int decode_cache_sets(unsigned int config_field)
|
||||
{
|
||||
if (config_field == 7) {
|
||||
/* JDCXXX - Find a graceful way to abort. */
|
||||
return 0;
|
||||
}
|
||||
return (1<<(config_field + 6));
|
||||
}
|
||||
|
||||
/*
|
||||
* Cache line size values (from the mips64 spec)
|
||||
* 0 - No cache present.
|
||||
* 1 - 4 bytes
|
||||
* 2 - 8 bytes
|
||||
* 3 - 16 bytes
|
||||
* 4 - 32 bytes
|
||||
* 5 - 64 bytes
|
||||
* 6 - 128 bytes
|
||||
* 7 - Reserved
|
||||
*/
|
||||
|
||||
static unsigned int decode_cache_line_size(unsigned int config_field)
|
||||
{
|
||||
if (config_field == 0) {
|
||||
return 0;
|
||||
} else if (config_field == 7) {
|
||||
/* JDCXXX - Find a graceful way to abort. */
|
||||
return 0;
|
||||
}
|
||||
return (1<<(config_field + 1));
|
||||
}
|
||||
|
||||
/*
|
||||
* Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs)
|
||||
*
|
||||
* 24:22 Icache sets per way
|
||||
* 21:19 Icache line size
|
||||
* 18:16 Icache Associativity
|
||||
* 15:13 Dcache sets per way
|
||||
* 12:10 Dcache line size
|
||||
* 9:7 Dcache Associativity
|
||||
*/
|
||||
|
||||
static char *way_string[] = {
|
||||
"direct mapped", "2-way", "3-way", "4-way",
|
||||
"5-way", "6-way", "7-way", "8-way",
|
||||
};
|
||||
|
||||
static __init void probe_cache_sizes(void)
|
||||
{
|
||||
u32 config1;
|
||||
|
||||
config1 = read_c0_config1();
|
||||
icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7);
|
||||
dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7);
|
||||
icache_sets = decode_cache_sets((config1 >> 22) & 0x7);
|
||||
dcache_sets = decode_cache_sets((config1 >> 13) & 0x7);
|
||||
icache_assoc = ((config1 >> 16) & 0x7) + 1;
|
||||
dcache_assoc = ((config1 >> 7) & 0x7) + 1;
|
||||
icache_size = icache_line_size * icache_sets * icache_assoc;
|
||||
dcache_size = dcache_line_size * dcache_sets * dcache_assoc;
|
||||
/* Need to remove non-index bits for index ops */
|
||||
icache_index_mask = (icache_sets - 1) * icache_line_size;
|
||||
dcache_index_mask = (dcache_sets - 1) * dcache_line_size;
|
||||
/*
|
||||
* These are for choosing range (index ops) versus all.
|
||||
* icache flushes all ways for each set, so drop icache_assoc.
|
||||
* dcache flushes all ways and each setting of bit 12 for each
|
||||
* index, so drop dcache_assoc and halve the dcache_sets.
|
||||
*/
|
||||
icache_range_cutoff = icache_sets * icache_line_size;
|
||||
dcache_range_cutoff = (dcache_sets / 2) * icache_line_size;
|
||||
|
||||
printk("Primary instruction cache %ldkB, %s, linesize %d bytes.\n",
|
||||
icache_size >> 10, way_string[icache_assoc - 1],
|
||||
icache_line_size);
|
||||
printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
|
||||
dcache_size >> 10, way_string[dcache_assoc - 1],
|
||||
dcache_line_size);
|
||||
}
|
||||
|
||||
/*
|
||||
* This is called from cache.c. We have to set up all the
|
||||
* memory management function pointers, as well as initialize
|
||||
* the caches and tlbs
|
||||
*/
|
||||
void __init sb1_cache_init(void)
|
||||
{
|
||||
extern char except_vec2_sb1;
|
||||
|
||||
/* Special cache error handler for SB1 */
|
||||
set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
|
||||
|
||||
probe_cache_sizes();
|
||||
|
||||
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
|
||||
sb1_dma_init();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* None of these are needed for the SB1 - the Dcache is
|
||||
* physically indexed and tagged, so no virtual aliasing can
|
||||
* occur
|
||||
*/
|
||||
flush_cache_range = (void *) sb1_nop;
|
||||
flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop;
|
||||
flush_cache_all = sb1_nop;
|
||||
|
||||
/* These routines are for Icache coherence with the Dcache */
|
||||
flush_icache_range = sb1_flush_icache_range;
|
||||
flush_icache_all = __sb1_flush_icache_all; /* local only */
|
||||
|
||||
/* This implies an Icache flush too, so can't be nop'ed */
|
||||
flush_cache_page = sb1_flush_cache_page;
|
||||
|
||||
flush_cache_sigtramp = sb1_flush_cache_sigtramp;
|
||||
local_flush_data_cache_page = (void *) sb1_nop;
|
||||
flush_data_cache_page = sb1_flush_cache_data_page;
|
||||
|
||||
/* Full flush */
|
||||
__flush_cache_all = sb1___flush_cache_all;
|
||||
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
||||
|
||||
/*
|
||||
* This is the only way to force the update of K0 to complete
|
||||
* before subsequent instruction fetch.
|
||||
*/
|
||||
__asm__ __volatile__(
|
||||
".set push \n"
|
||||
" .set noat \n"
|
||||
" .set noreorder \n"
|
||||
" .set mips3 \n"
|
||||
" " STR(PTR_LA) " $1, 1f \n"
|
||||
" " STR(MTC0) " $1, $14 \n"
|
||||
" eret \n"
|
||||
"1: .set pop"
|
||||
:
|
||||
:
|
||||
: "memory");
|
||||
|
||||
local_sb1___flush_cache_all();
|
||||
}
|
||||
|
|
@ -3,13 +3,14 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (C) 2007 MIPS Technologies, Inc.
|
||||
*/
|
||||
#include <linux/fs.h>
|
||||
#include <linux/fcntl.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
|
|
@ -157,12 +158,6 @@ void __init cpu_cache_init(void)
|
|||
tx39_cache_init();
|
||||
return;
|
||||
}
|
||||
if (cpu_has_sb1_cache) {
|
||||
extern void __weak sb1_cache_init(void);
|
||||
|
||||
sb1_cache_init();
|
||||
return;
|
||||
}
|
||||
|
||||
panic(cache_panic);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -292,3 +292,11 @@ void copy_page(void *to, void *from)
|
|||
|
||||
EXPORT_SYMBOL(clear_page);
|
||||
EXPORT_SYMBOL(copy_page);
|
||||
|
||||
void __init build_clear_page(void)
|
||||
{
|
||||
}
|
||||
|
||||
void __init build_copy_page(void)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,9 +35,6 @@
|
|||
#ifndef cpu_has_tx39_cache
|
||||
#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
|
||||
#endif
|
||||
#ifndef cpu_has_sb1_cache
|
||||
#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
|
||||
#endif
|
||||
#ifndef cpu_has_fpu
|
||||
#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
|
||||
#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
|
||||
|
|
|
|||
|
|
@ -255,24 +255,23 @@
|
|||
#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
|
||||
#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
|
||||
#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
|
||||
#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */
|
||||
#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */
|
||||
#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */
|
||||
#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */
|
||||
#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */
|
||||
#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */
|
||||
#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */
|
||||
#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */
|
||||
#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */
|
||||
#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */
|
||||
#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
|
||||
#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
|
||||
#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
|
||||
#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */
|
||||
#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
|
||||
#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
|
||||
#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
|
||||
#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */
|
||||
#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
|
||||
#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
|
||||
#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
|
||||
#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
|
||||
#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
|
||||
#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
|
||||
#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
|
||||
#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
|
||||
#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
|
||||
#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
|
||||
#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
|
||||
#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
|
||||
#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
|
||||
#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
|
||||
#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
|
||||
#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
|
||||
#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
|
||||
|
||||
/*
|
||||
* CPU ASE encodings
|
||||
|
|
|
|||
|
|
@ -5,4 +5,6 @@
|
|||
#include <asm/asm.h>
|
||||
#endif
|
||||
|
||||
#define __weak __attribute__((weak))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#define cpu_has_3k_cache 0
|
||||
#define cpu_has_4k_cache 1
|
||||
#define cpu_has_tx39_cache 0
|
||||
#define cpu_has_sb1_cache 0
|
||||
#define cpu_has_fpu 1
|
||||
#define cpu_has_32fpr 1
|
||||
#define cpu_has_counter 1
|
||||
|
|
|
|||
Loading…
Reference in a new issue