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clocksource: sun4i: Fix the next event code

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The next_event logic was setting the next interval to fire in the
current timer value instead of the interval value register, which is
obviously wrong.

Plus, the logic to set the actual value was wrong as well: the interval
register can only be modified when the timer is disabled, and then
enable it back, otherwise, it'll have no effect. Fix this logic as well
since that code couldn't possibly work.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Maxime Ripard 2013-07-16 16:45:38 +02:00 committed by Daniel Lezcano
parent 8c31bec28b
commit 63d88f1ac7
1 changed files with 22 additions and 3 deletions
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25
drivers/clocksource/sun4i_timer.c
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@ -38,6 +38,20 @@
static void __iomem *timer_base;
/*
* When we disable a timer, we need to wait at least for 2 cycles of
* the timer source clock. We will use for that the clocksource timer
* that is already setup and runs at the same frequency than the other
* timers, and we never will be disabled.
*/
static void sun4i_clkevt_sync(void)
{
u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
cpu_relax();
}
static void sun4i_clkevt_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
@ -63,9 +77,14 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
static int sun4i_clkevt_next_event(unsigned long evt,
struct clock_event_device *unused)
{
u32 u = readl(timer_base + TIMER_CTL_REG(0));
writel(evt, timer_base + TIMER_CNTVAL_REG(0));
writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
u32 val = readl(timer_base + TIMER_CTL_REG(0));
writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
sun4i_clkevt_sync();
writel(evt, timer_base + TIMER_INTVAL_REG(0));
val = readl(timer_base + TIMER_CTL_REG(0));
writel(val | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
timer_base + TIMER_CTL_REG(0));
return 0;