tg3 / broadcom: Add PHY_BRCM_CLEAR_RGMII_MODE flag
Broadcom 50610M parts changed the default definitions of the RGMII mode shadow register. The 5785 needs the RGMII mode selection bits [4:3] cleared. The default value of the remaining bits in this register are zero. Rather than unnecessarily burn an extra bit in the dev_flags member in an attempt to enumerate all possible combinations, this patch take a more course grained approach and labels the option as "clear all bits". Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3 changed files with 8 additions and 0 deletions
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@ -105,6 +105,7 @@
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#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
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/* LED1 / ~LINKSPD[1] selector */
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#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
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#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
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#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
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#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
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#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
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@ -330,6 +331,11 @@ static int bcm54xx_config_init(struct phy_device *phydev)
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if (err < 0)
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return err;
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if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
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(phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
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bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
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bcm54xx_phydsp_config(phydev);
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return 0;
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@ -1100,6 +1100,7 @@ static int tg3_mdio_init(struct tg3 *tp)
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break;
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case TG3_PHY_ID_BCM50610:
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case TG3_PHY_ID_BCM50610M:
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phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
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phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
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@ -8,4 +8,5 @@
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#define PHY_BRCM_STD_IBND_DISABLE 0x00000800
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#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
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#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
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#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
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#define PHY_BCM_FLAGS_VALID 0x80000000
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