drm/i915: ensure lru ordering of fence_list
The fence_list should be lru ordered for otherwise we might try to steal a fence reg from an active object even though there are fences from inactive objects available. lru ordering was obeyed for gpu access everywhere save when moving dirty objects from flushing_list to active_list. Fixing this cause the code to indent way to much, so I've extracted the flushing_list processing logic into its on function. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
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1 changed files with 34 additions and 23 deletions
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@ -1558,6 +1558,38 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
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i915_verify_inactive(dev, __FILE__, __LINE__);
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}
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static void
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i915_gem_process_flushing_list(struct drm_device *dev,
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uint32_t flush_domains, uint32_t seqno)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj_priv, *next;
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list_for_each_entry_safe(obj_priv, next,
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&dev_priv->mm.gpu_write_list,
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gpu_write_list) {
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struct drm_gem_object *obj = obj_priv->obj;
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if ((obj->write_domain & flush_domains) ==
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obj->write_domain) {
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uint32_t old_write_domain = obj->write_domain;
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obj->write_domain = 0;
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list_del_init(&obj_priv->gpu_write_list);
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i915_gem_object_move_to_active(obj, seqno);
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/* update the fence lru list */
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if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
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list_move_tail(&obj_priv->fence_list,
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&dev_priv->mm.fence_list);
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trace_i915_gem_object_change_domain(obj,
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obj->read_domains,
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old_write_domain);
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}
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}
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}
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/**
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* Creates a new sequence number, emitting a write of it to the status page
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* plus an interrupt, which will trigger i915_user_interrupt_handler.
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@ -1616,29 +1648,8 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
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/* Associate any objects on the flushing list matching the write
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* domain we're flushing with our flush.
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*/
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if (flush_domains != 0) {
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struct drm_i915_gem_object *obj_priv, *next;
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list_for_each_entry_safe(obj_priv, next,
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&dev_priv->mm.gpu_write_list,
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gpu_write_list) {
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struct drm_gem_object *obj = obj_priv->obj;
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if ((obj->write_domain & flush_domains) ==
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obj->write_domain) {
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uint32_t old_write_domain = obj->write_domain;
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obj->write_domain = 0;
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list_del_init(&obj_priv->gpu_write_list);
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i915_gem_object_move_to_active(obj, seqno);
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trace_i915_gem_object_change_domain(obj,
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obj->read_domains,
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old_write_domain);
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}
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}
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}
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if (flush_domains != 0)
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i915_gem_process_flushing_list(dev, flush_domains, seqno);
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if (!dev_priv->mm.suspended) {
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mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
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