[PATCH] powerpc: Merged ppc_asm.h
Merged ppc_asm.h between ppc32 & ppc64. The majority of the file is common between the two architectures excluding how a single GPR is saved/restored and which GPRs are non-volatile. Additionally, moved the ASM_CONST macro used on ppc64 into ppc_asm.h. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Kumar Gala
Paul Mackerras
parent
0a1e1222b7
commit
5f7c690728
7 changed files with 158 additions and 318 deletions
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@ -804,7 +804,7 @@ load_up_altivec:
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beq 1f
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add r4,r4,r6
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addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
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SAVE_32VR(0,r10,r4)
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SAVE_32VRS(0,r10,r4)
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mfvscr vr0
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li r10,THREAD_VSCR
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stvx vr0,r10,r4
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@ -824,7 +824,7 @@ load_up_altivec:
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stw r4,THREAD_USED_VR(r5)
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lvx vr0,r10,r5
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mtvscr vr0
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REST_32VR(0,r10,r5)
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REST_32VRS(0,r10,r5)
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#ifndef CONFIG_SMP
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subi r4,r5,THREAD
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sub r4,r4,r6
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@ -870,7 +870,7 @@ giveup_altivec:
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addi r3,r3,THREAD /* want THREAD of task */
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lwz r5,PT_REGS(r3)
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cmpwi 0,r5,0
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SAVE_32VR(0, r4, r3)
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SAVE_32VRS(0, r4, r3)
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mfvscr vr0
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li r4,THREAD_VSCR
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stvx vr0,r4,r3
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@ -853,7 +853,7 @@ load_up_spe:
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cmpi 0,r4,0
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beq 1f
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addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
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SAVE_32EVR(0,r10,r4)
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SAVE_32EVRS(0,r10,r4)
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evxor evr10, evr10, evr10 /* clear out evr10 */
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evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
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li r5,THREAD_ACC
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@ -873,7 +873,7 @@ load_up_spe:
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stw r4,THREAD_USED_SPE(r5)
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evlddx evr4,r10,r5
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evmra evr4,evr4
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REST_32EVR(0,r10,r5)
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REST_32EVRS(0,r10,r5)
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#ifndef CONFIG_SMP
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subi r4,r5,THREAD
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stw r4,last_task_used_spe@l(r3)
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@ -963,7 +963,7 @@ _GLOBAL(giveup_spe)
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addi r3,r3,THREAD /* want THREAD of task */
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lwz r5,PT_REGS(r3)
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cmpi 0,r5,0
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SAVE_32EVR(0, r4, r3)
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SAVE_32EVRS(0, r4, r3)
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evxor evr6, evr6, evr6 /* clear out evr6 */
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evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
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li r4,THREAD_ACC
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@ -1,37 +1,39 @@
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/*
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* include/asm-ppc/ppc_asm.h
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*
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* Definitions used by various bits of low-level assembly code on PowerPC.
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*
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#ifndef _ASM_POWERPC_PPC_ASM_H
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#define _ASM_POWERPC_PPC_ASM_H
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#ifdef __ASSEMBLY__
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/*
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* Macros for storing registers into and loading registers from
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* exception frames.
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*/
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#ifdef __powerpc64__
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#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
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#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
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#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
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#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
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#else
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#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
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#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
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#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
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#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
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#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
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#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
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#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
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#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
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#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
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SAVE_10GPRS(22, base)
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#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
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REST_10GPRS(22, base)
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#endif
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
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#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
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#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
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#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
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#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
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#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
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#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
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#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
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#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
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@ -47,32 +49,80 @@
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#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
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#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
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#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
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#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
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#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
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#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
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#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
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#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
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#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
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#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
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#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
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#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
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#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
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#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
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#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base)
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#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base)
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#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base)
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#define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base)
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#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
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#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
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#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
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#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
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#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
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#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
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#define SAVE_2EVR(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
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#define SAVE_4EVR(n,s,base) SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
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#define SAVE_8EVR(n,s,base) SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
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#define SAVE_16EVR(n,s,base) SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
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#define SAVE_32EVR(n,s,base) SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)
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#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
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#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
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#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
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#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
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#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
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#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
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#define REST_2EVR(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
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#define REST_4EVR(n,s,base) REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
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#define REST_8EVR(n,s,base) REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
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#define REST_16EVR(n,s,base) REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
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#define REST_32EVR(n,s,base) REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)
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#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
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#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
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#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
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#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
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#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
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/* Macros to adjust thread priority for Iseries hardware multithreading */
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#define HMT_LOW or 1,1,1
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#define HMT_MEDIUM or 2,2,2
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#define HMT_HIGH or 3,3,3
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/* handle instructions that older assemblers may not know */
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#define RFCI .long 0x4c000066 /* rfci instruction */
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#define RFDI .long 0x4c00004e /* rfdi instruction */
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#define RFMCI .long 0x4c00004c /* rfmci instruction */
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/*
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* LOADADDR( rn, name )
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* loads the address of 'name' into 'rn'
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*
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* LOADBASE( rn, name )
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* loads the address (less the low 16 bits) of 'name' into 'rn'
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* suitable for base+disp addressing
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*/
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#ifdef __powerpc64__
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#define LOADADDR(rn,name) \
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lis rn,name##@highest; \
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ori rn,rn,name##@higher; \
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rldicr rn,rn,32,31; \
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oris rn,rn,name##@h; \
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ori rn,rn,name##@l
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#define LOADBASE(rn,name) \
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lis rn,name@highest; \
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ori rn,rn,name@higher; \
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rldicr rn,rn,32,31; \
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oris rn,rn,name@ha
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#define SET_REG_TO_CONST(reg, value) \
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lis reg,(((value)>>48)&0xFFFF); \
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ori reg,reg,(((value)>>32)&0xFFFF); \
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rldicr reg,reg,32,31; \
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oris reg,reg,(((value)>>16)&0xFFFF); \
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ori reg,reg,((value)&0xFFFF);
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#define SET_REG_TO_LABEL(reg, label) \
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lis reg,(label)@highest; \
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ori reg,reg,(label)@higher; \
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rldicr reg,reg,32,31; \
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oris reg,reg,(label)@h; \
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ori reg,reg,(label)@l;
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#endif
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/* various errata or part fixups */
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#ifdef CONFIG_PPC601_SYNC_FIX
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#define SYNC \
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BEGIN_FTR_SECTION \
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@ -93,6 +143,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
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#define ISYNC_601
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#endif
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#ifndef CONFIG_SMP
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#define TLBSYNC
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#else /* CONFIG_SMP */
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@ -104,6 +155,7 @@ BEGIN_FTR_SECTION \
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END_FTR_SECTION_IFCLR(CPU_FTR_601)
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#endif
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/*
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* This instruction is not implemented on the PPC 603 or 601; however, on
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* the 403GCX and 405GP tlbia IS defined and tlbie is not.
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@ -121,14 +173,44 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
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bdnz 0b
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#endif
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#ifdef CONFIG_BOOKE
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#ifdef CONFIG_IBM405_ERR77
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#define PPC405_ERR77(ra,rb) dcbt ra, rb;
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#define PPC405_ERR77_SYNC sync;
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#else
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#define PPC405_ERR77(ra,rb)
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#define PPC405_ERR77_SYNC
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#endif
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#ifdef CONFIG_IBM440EP_ERR42
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#define PPC440EP_ERR42 isync
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#else
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#define PPC440EP_ERR42
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#endif
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#if defined(CONFIG_BOOKE)
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#define tophys(rd,rs) \
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addis rd,rs,0
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#define tovirt(rd,rs) \
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addis rd,rs,0
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#else /* CONFIG_BOOKE */
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#elif defined(CONFIG_PPC64)
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/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
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* Then we can easily do this with one asm insn. -Peter
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*/
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#define tophys(rd,rs) \
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lis rd,((KERNELBASE>>48)&0xFFFF); \
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rldicr rd,rd,32,31; \
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sub rd,rs,rd
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#define tovirt(rd,rs) \
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lis rd,((KERNELBASE>>48)&0xFFFF); \
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rldicr rd,rd,32,31; \
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add rd,rs,rd
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#else
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/*
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* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
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* physical base address of RAM at compile time.
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@ -146,14 +228,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
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.align 1; \
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.long 0b; \
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.previous
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#endif /* CONFIG_BOOKE */
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#endif
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/*
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* On 64-bit cpus, we use the rfid instruction instead of rfi, but
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* we then have to make sure we preserve the top 32 bits except for
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* the 64-bit mode bit, which we clear.
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*/
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#ifdef CONFIG_PPC64BRIDGE
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#if defined(CONFIG_PPC64BRIDGE)
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#define FIX_SRR1(ra, rb) \
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mr rb,ra; \
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mfmsr ra; \
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@ -162,6 +244,17 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
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#define RFI .long 0x4c000024 /* rfid instruction */
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#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
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#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
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#elif defined(CONFIG_PPC64)
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/* Insert the high 32 bits of the MSR into what will be the new
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MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
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bits. */
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#define FIX_SRR1(ra, rb) \
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mr rb,ra; \
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mfmsr ra; \
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rldimi ra,rb,0,32
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#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
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#else
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#define FIX_SRR1(ra, rb)
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@ -172,24 +265,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
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#endif
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#define MTMSRD(r) mtmsr r
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#define CLR_TOP32(r)
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#endif /* CONFIG_PPC64BRIDGE */
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|
||||
#define RFCI .long 0x4c000066 /* rfci instruction */
|
||||
#define RFDI .long 0x4c00004e /* rfdi instruction */
|
||||
#define RFMCI .long 0x4c00004c /* rfmci instruction */
|
||||
|
||||
#ifdef CONFIG_IBM405_ERR77
|
||||
#define PPC405_ERR77(ra,rb) dcbt ra, rb;
|
||||
#define PPC405_ERR77_SYNC sync;
|
||||
#else
|
||||
#define PPC405_ERR77(ra,rb)
|
||||
#define PPC405_ERR77_SYNC
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IBM440EP_ERR42
|
||||
#define PPC440EP_ERR42 isync
|
||||
#else
|
||||
#define PPC440EP_ERR42
|
||||
#endif
|
||||
|
||||
/* The boring bits... */
|
||||
|
|
@ -277,6 +352,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
|
|||
#define fr30 30
|
||||
#define fr31 31
|
||||
|
||||
/* AltiVec Registers (VPRs) */
|
||||
|
||||
#define vr0 0
|
||||
#define vr1 1
|
||||
#define vr2 2
|
||||
|
|
@ -310,6 +387,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
|
|||
#define vr30 30
|
||||
#define vr31 31
|
||||
|
||||
/* SPE Registers (EVPRs) */
|
||||
|
||||
#define evr0 0
|
||||
#define evr1 1
|
||||
#define evr2 2
|
||||
|
|
@ -348,3 +427,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
|
|||
#define N_RSYM 64
|
||||
#define N_SLINE 68
|
||||
#define N_SO 100
|
||||
|
||||
#define ASM_CONST(x) x
|
||||
#else
|
||||
#define __ASM_CONST(x) x##UL
|
||||
#define ASM_CONST(x) __ASM_CONST(x)
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_POWERPC_PPC_ASM_H */
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
#define __ASM_PPC_CPUTABLE_H
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <asm/page.h> /* for ASM_CONST */
|
||||
#include <asm/ppc_asm.h> /* for ASM_CONST */
|
||||
|
||||
/* Exposed to userland CPU features - Must match ppc32 definitions */
|
||||
#define PPC_FEATURE_32 0x80000000
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#define _PPC64_MMU_H_
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <asm/ppc_asm.h> /* for ASM_CONST */
|
||||
#include <asm/page.h>
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -11,13 +11,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define ASM_CONST(x) x
|
||||
#else
|
||||
#define __ASM_CONST(x) x##UL
|
||||
#define ASM_CONST(x) __ASM_CONST(x)
|
||||
#endif
|
||||
#include <asm/ppc_asm.h> /* for ASM_CONST */
|
||||
|
||||
/* PAGE_SHIFT determines the page size */
|
||||
#define PAGE_SHIFT 12
|
||||
|
|
|
|||
|
|
@ -1,242 +0,0 @@
|
|||
/*
|
||||
* arch/ppc64/kernel/ppc_asm.h
|
||||
*
|
||||
* Definitions used by various bits of low-level assembly code on PowerPC.
|
||||
*
|
||||
* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _PPC64_PPC_ASM_H
|
||||
#define _PPC64_PPC_ASM_H
|
||||
/*
|
||||
* Macros for storing registers into and loading registers from
|
||||
* exception frames.
|
||||
*/
|
||||
#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
|
||||
#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
|
||||
#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
|
||||
#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
|
||||
#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
|
||||
#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
|
||||
#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
|
||||
#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
|
||||
#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
|
||||
#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
|
||||
|
||||
#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
|
||||
#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
|
||||
|
||||
#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
|
||||
#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
|
||||
#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
|
||||
#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
|
||||
#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
|
||||
#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
|
||||
#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
|
||||
#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
|
||||
#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
|
||||
#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
|
||||
#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
|
||||
#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
|
||||
|
||||
#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
|
||||
#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
|
||||
#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
|
||||
#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
|
||||
#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
|
||||
#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
|
||||
#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
|
||||
#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
|
||||
#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
|
||||
#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
|
||||
#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
|
||||
#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
|
||||
|
||||
/* Macros to adjust thread priority for Iseries hardware multithreading */
|
||||
#define HMT_LOW or 1,1,1
|
||||
#define HMT_MEDIUM or 2,2,2
|
||||
#define HMT_HIGH or 3,3,3
|
||||
|
||||
/* Insert the high 32 bits of the MSR into what will be the new
|
||||
MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
|
||||
bits. */
|
||||
|
||||
#define FIX_SRR1(ra, rb) \
|
||||
mr rb,ra; \
|
||||
mfmsr ra; \
|
||||
rldimi ra,rb,0,32
|
||||
|
||||
#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
|
||||
|
||||
/*
|
||||
* LOADADDR( rn, name )
|
||||
* loads the address of 'name' into 'rn'
|
||||
*
|
||||
* LOADBASE( rn, name )
|
||||
* loads the address (less the low 16 bits) of 'name' into 'rn'
|
||||
* suitable for base+disp addressing
|
||||
*/
|
||||
#define LOADADDR(rn,name) \
|
||||
lis rn,name##@highest; \
|
||||
ori rn,rn,name##@higher; \
|
||||
rldicr rn,rn,32,31; \
|
||||
oris rn,rn,name##@h; \
|
||||
ori rn,rn,name##@l
|
||||
|
||||
#define LOADBASE(rn,name) \
|
||||
lis rn,name@highest; \
|
||||
ori rn,rn,name@higher; \
|
||||
rldicr rn,rn,32,31; \
|
||||
oris rn,rn,name@ha
|
||||
|
||||
|
||||
#define SET_REG_TO_CONST(reg, value) \
|
||||
lis reg,(((value)>>48)&0xFFFF); \
|
||||
ori reg,reg,(((value)>>32)&0xFFFF); \
|
||||
rldicr reg,reg,32,31; \
|
||||
oris reg,reg,(((value)>>16)&0xFFFF); \
|
||||
ori reg,reg,((value)&0xFFFF);
|
||||
|
||||
#define SET_REG_TO_LABEL(reg, label) \
|
||||
lis reg,(label)@highest; \
|
||||
ori reg,reg,(label)@higher; \
|
||||
rldicr reg,reg,32,31; \
|
||||
oris reg,reg,(label)@h; \
|
||||
ori reg,reg,(label)@l;
|
||||
|
||||
|
||||
/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
|
||||
* Then we can easily do this with one asm insn. -Peter
|
||||
*/
|
||||
#define tophys(rd,rs) \
|
||||
lis rd,((KERNELBASE>>48)&0xFFFF); \
|
||||
rldicr rd,rd,32,31; \
|
||||
sub rd,rs,rd
|
||||
|
||||
#define tovirt(rd,rs) \
|
||||
lis rd,((KERNELBASE>>48)&0xFFFF); \
|
||||
rldicr rd,rd,32,31; \
|
||||
add rd,rs,rd
|
||||
|
||||
/* Condition Register Bit Fields */
|
||||
|
||||
#define cr0 0
|
||||
#define cr1 1
|
||||
#define cr2 2
|
||||
#define cr3 3
|
||||
#define cr4 4
|
||||
#define cr5 5
|
||||
#define cr6 6
|
||||
#define cr7 7
|
||||
|
||||
|
||||
/* General Purpose Registers (GPRs) */
|
||||
|
||||
#define r0 0
|
||||
#define r1 1
|
||||
#define r2 2
|
||||
#define r3 3
|
||||
#define r4 4
|
||||
#define r5 5
|
||||
#define r6 6
|
||||
#define r7 7
|
||||
#define r8 8
|
||||
#define r9 9
|
||||
#define r10 10
|
||||
#define r11 11
|
||||
#define r12 12
|
||||
#define r13 13
|
||||
#define r14 14
|
||||
#define r15 15
|
||||
#define r16 16
|
||||
#define r17 17
|
||||
#define r18 18
|
||||
#define r19 19
|
||||
#define r20 20
|
||||
#define r21 21
|
||||
#define r22 22
|
||||
#define r23 23
|
||||
#define r24 24
|
||||
#define r25 25
|
||||
#define r26 26
|
||||
#define r27 27
|
||||
#define r28 28
|
||||
#define r29 29
|
||||
#define r30 30
|
||||
#define r31 31
|
||||
|
||||
|
||||
/* Floating Point Registers (FPRs) */
|
||||
|
||||
#define fr0 0
|
||||
#define fr1 1
|
||||
#define fr2 2
|
||||
#define fr3 3
|
||||
#define fr4 4
|
||||
#define fr5 5
|
||||
#define fr6 6
|
||||
#define fr7 7
|
||||
#define fr8 8
|
||||
#define fr9 9
|
||||
#define fr10 10
|
||||
#define fr11 11
|
||||
#define fr12 12
|
||||
#define fr13 13
|
||||
#define fr14 14
|
||||
#define fr15 15
|
||||
#define fr16 16
|
||||
#define fr17 17
|
||||
#define fr18 18
|
||||
#define fr19 19
|
||||
#define fr20 20
|
||||
#define fr21 21
|
||||
#define fr22 22
|
||||
#define fr23 23
|
||||
#define fr24 24
|
||||
#define fr25 25
|
||||
#define fr26 26
|
||||
#define fr27 27
|
||||
#define fr28 28
|
||||
#define fr29 29
|
||||
#define fr30 30
|
||||
#define fr31 31
|
||||
|
||||
#define vr0 0
|
||||
#define vr1 1
|
||||
#define vr2 2
|
||||
#define vr3 3
|
||||
#define vr4 4
|
||||
#define vr5 5
|
||||
#define vr6 6
|
||||
#define vr7 7
|
||||
#define vr8 8
|
||||
#define vr9 9
|
||||
#define vr10 10
|
||||
#define vr11 11
|
||||
#define vr12 12
|
||||
#define vr13 13
|
||||
#define vr14 14
|
||||
#define vr15 15
|
||||
#define vr16 16
|
||||
#define vr17 17
|
||||
#define vr18 18
|
||||
#define vr19 19
|
||||
#define vr20 20
|
||||
#define vr21 21
|
||||
#define vr22 22
|
||||
#define vr23 23
|
||||
#define vr24 24
|
||||
#define vr25 25
|
||||
#define vr26 26
|
||||
#define vr27 27
|
||||
#define vr28 28
|
||||
#define vr29 29
|
||||
#define vr30 30
|
||||
#define vr31 31
|
||||
|
||||
#endif /* _PPC64_PPC_ASM_H */
|
||||
Loading…
Reference in a new issue