drm/i915: Use macros to switch between equivalent pipe registers
The purpose is to make the code much easier to read and therefore reduce the possibility for bugs. A side effect is that it also makes it much easier for the compiler, reducing the object size by 4k -- from just a few functions! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
4ed765f966
commit
5eddb70ba2
5 changed files with 508 additions and 547 deletions
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@ -191,12 +191,7 @@ static int
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i915_pipe_enabled(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
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if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
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return 1;
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return 0;
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return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
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}
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/* Called from drm generic code, passed a 'crtc', which
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@ -207,10 +202,7 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long high_frame;
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unsigned long low_frame;
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u32 high1, high2, low, count;
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high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
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low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
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u32 high1, high2, low;
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if (!i915_pipe_enabled(dev, pipe)) {
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DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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@ -218,23 +210,23 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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return 0;
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}
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high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
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low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
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/*
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* High & low register fields aren't synchronized, so make sure
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* we get a low value that's stable across two reads of the high
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* register.
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*/
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do {
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high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
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PIPE_FRAME_HIGH_SHIFT);
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low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
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PIPE_FRAME_LOW_SHIFT);
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high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
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PIPE_FRAME_HIGH_SHIFT);
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high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
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high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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} while (high1 != high2);
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count = (high1 << 8) | low;
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return count;
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high1 >>= PIPE_FRAME_HIGH_SHIFT;
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low >>= PIPE_FRAME_LOW_SHIFT;
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return (high1 << 8) | low;
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}
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u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
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@ -1207,11 +1199,8 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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u32 pipeconf;
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pipeconf = I915_READ(pipeconf_reg);
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if (!(pipeconf & PIPEACONF_ENABLE))
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if (!i915_pipe_enabled(dev, pipe))
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return -EINVAL;
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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@ -25,6 +25,8 @@
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#ifndef _I915_REG_H_
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#define _I915_REG_H_
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#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
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/*
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* The Bridge device's PCI config space has information about the
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* fb aperture size and the amount of pre-reserved memory.
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@ -605,6 +607,7 @@
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#define VGA1_PD_P1_MASK (0x1f << 8)
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#define DPLL_A 0x06014
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#define DPLL_B 0x06018
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#define DPLL(pipe) _PIPE(pipe, DPLL_A, DPLL_B)
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#define DPLL_VCO_ENABLE (1 << 31)
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#define DPLL_DVO_HIGH_SPEED (1 << 30)
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#define DPLL_SYNCLOCK_ENABLE (1 << 29)
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@ -738,10 +741,13 @@
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#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
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#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
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#define DPLL_B_MD 0x06020 /* 965+ only */
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#define DPLL_MD(pipe) _PIPE(pipe, DPLL_A_MD, DPLL_B_MD)
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#define FPA0 0x06040
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#define FPA1 0x06044
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#define FPB0 0x06048
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#define FPB1 0x0604c
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#define FP0(pipe) _PIPE(pipe, FPA0, FPB0)
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#define FP1(pipe) _PIPE(pipe, FPA1, FPB1)
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#define FP_N_DIV_MASK 0x003f0000
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#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
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#define FP_N_DIV_SHIFT 16
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@ -1156,6 +1162,15 @@
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#define PIPEBSRC 0x6101c
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#define BCLRPAT_B 0x61020
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#define HTOTAL(pipe) _PIPE(pipe, HTOTAL_A, HTOTAL_B)
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#define HBLANK(pipe) _PIPE(pipe, HBLANK_A, HBLANK_B)
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#define HSYNC(pipe) _PIPE(pipe, HSYNC_A, HSYNC_B)
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#define VTOTAL(pipe) _PIPE(pipe, VTOTAL_A, VTOTAL_B)
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#define VBLANK(pipe) _PIPE(pipe, VBLANK_A, VBLANK_B)
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#define VSYNC(pipe) _PIPE(pipe, VSYNC_A, VSYNC_B)
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#define PIPESRC(pipe) _PIPE(pipe, PIPEASRC, PIPEBSRC)
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#define BCLRPAT(pipe) _PIPE(pipe, BCLRPAT_A, BCLRPAT_B)
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/* VGA port control */
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#define ADPA 0x61100
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#define ADPA_DAC_ENABLE (1<<31)
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@ -2086,15 +2101,15 @@
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#define PIPEADSL 0x70000
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#define DSL_LINEMASK 0x00000fff
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#define PIPEACONF 0x70008
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#define PIPEACONF_ENABLE (1<<31)
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#define PIPEACONF_DISABLE 0
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#define PIPEACONF_DOUBLE_WIDE (1<<30)
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#define PIPECONF_ENABLE (1<<31)
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#define PIPECONF_DISABLE 0
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#define PIPECONF_DOUBLE_WIDE (1<<30)
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#define I965_PIPECONF_ACTIVE (1<<30)
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#define PIPEACONF_SINGLE_WIDE 0
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#define PIPEACONF_PIPE_UNLOCKED 0
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#define PIPEACONF_PIPE_LOCKED (1<<25)
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#define PIPEACONF_PALETTE 0
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#define PIPEACONF_GAMMA (1<<24)
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#define PIPECONF_SINGLE_WIDE 0
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#define PIPECONF_PIPE_UNLOCKED 0
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#define PIPECONF_PIPE_LOCKED (1<<25)
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#define PIPECONF_PALETTE 0
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#define PIPECONF_GAMMA (1<<24)
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#define PIPECONF_FORCE_BORDER (1<<25)
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#define PIPECONF_PROGRESSIVE (0 << 21)
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#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
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@ -2147,6 +2162,8 @@
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#define PIPE_6BPC (2 << 5)
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#define PIPE_12BPC (3 << 5)
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#define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF)
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#define DSPARB 0x70030
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#define DSPARB_CSTART_MASK (0x7f << 7)
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#define DSPARB_CSTART_SHIFT 7
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@ -2346,6 +2363,14 @@
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#define DSPASURF 0x7019C /* 965+ only */
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#define DSPATILEOFF 0x701A4 /* 965+ only */
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#define DSPCNTR(plane) _PIPE(plane, DSPACNTR, DSPBCNTR)
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#define DSPADDR(plane) _PIPE(plane, DSPAADDR, DSPBADDR)
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#define DSPSTRIDE(plane) _PIPE(plane, DSPASTRIDE, DSPBSTRIDE)
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#define DSPPOS(plane) _PIPE(plane, DSPAPOS, DSPBPOS)
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#define DSPSIZE(plane) _PIPE(plane, DSPASIZE, DSPBSIZE)
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#define DSPSURF(plane) _PIPE(plane, DSPASURF, DSPBSURF)
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#define DSPTILEOFF(plane) _PIPE(plane, DSPATILEOFF, DSPBTILEOFF)
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/* VBIOS flags */
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#define SWF00 0x71410
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#define SWF01 0x71414
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@ -2434,46 +2459,47 @@
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#define PIPEA_DATA_M1 0x60030
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#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
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#define TU_SIZE_MASK 0x7e000000
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#define PIPEA_DATA_M1_OFFSET 0
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#define PIPE_DATA_M1_OFFSET 0
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#define PIPEA_DATA_N1 0x60034
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#define PIPEA_DATA_N1_OFFSET 0
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#define PIPE_DATA_N1_OFFSET 0
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#define PIPEA_DATA_M2 0x60038
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#define PIPEA_DATA_M2_OFFSET 0
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#define PIPE_DATA_M2_OFFSET 0
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#define PIPEA_DATA_N2 0x6003c
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#define PIPEA_DATA_N2_OFFSET 0
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#define PIPE_DATA_N2_OFFSET 0
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#define PIPEA_LINK_M1 0x60040
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#define PIPEA_LINK_M1_OFFSET 0
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#define PIPE_LINK_M1_OFFSET 0
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#define PIPEA_LINK_N1 0x60044
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#define PIPEA_LINK_N1_OFFSET 0
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#define PIPE_LINK_N1_OFFSET 0
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#define PIPEA_LINK_M2 0x60048
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#define PIPEA_LINK_M2_OFFSET 0
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#define PIPE_LINK_M2_OFFSET 0
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#define PIPEA_LINK_N2 0x6004c
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#define PIPEA_LINK_N2_OFFSET 0
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#define PIPE_LINK_N2_OFFSET 0
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/* PIPEB timing regs are same start from 0x61000 */
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#define PIPEB_DATA_M1 0x61030
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#define PIPEB_DATA_M1_OFFSET 0
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#define PIPEB_DATA_N1 0x61034
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#define PIPEB_DATA_N1_OFFSET 0
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#define PIPEB_DATA_M2 0x61038
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#define PIPEB_DATA_M2_OFFSET 0
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#define PIPEB_DATA_N2 0x6103c
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#define PIPEB_DATA_N2_OFFSET 0
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#define PIPEB_LINK_M1 0x61040
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#define PIPEB_LINK_M1_OFFSET 0
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#define PIPEB_LINK_N1 0x61044
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#define PIPEB_LINK_N1_OFFSET 0
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#define PIPEB_LINK_M2 0x61048
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#define PIPEB_LINK_M2_OFFSET 0
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#define PIPEB_LINK_N2 0x6104c
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#define PIPEB_LINK_N2_OFFSET 0
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#define PIPE_DATA_M1(pipe) _PIPE(pipe, PIPEA_DATA_M1, PIPEB_DATA_M1)
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#define PIPE_DATA_N1(pipe) _PIPE(pipe, PIPEA_DATA_N1, PIPEB_DATA_N1)
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#define PIPE_DATA_M2(pipe) _PIPE(pipe, PIPEA_DATA_M2, PIPEB_DATA_M2)
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#define PIPE_DATA_N2(pipe) _PIPE(pipe, PIPEA_DATA_N2, PIPEB_DATA_N2)
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#define PIPE_LINK_M1(pipe) _PIPE(pipe, PIPEA_LINK_M1, PIPEB_LINK_M1)
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#define PIPE_LINK_N1(pipe) _PIPE(pipe, PIPEA_LINK_N1, PIPEB_LINK_N1)
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#define PIPE_LINK_M2(pipe) _PIPE(pipe, PIPEA_LINK_M2, PIPEB_LINK_M2)
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#define PIPE_LINK_N2(pipe) _PIPE(pipe, PIPEA_LINK_N2, PIPEB_LINK_N2)
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/* CPU panel fitter */
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#define PFA_CTL_1 0x68080
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@ -2614,11 +2640,14 @@
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#define PCH_DPLL_A 0xc6014
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#define PCH_DPLL_B 0xc6018
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#define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B)
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#define PCH_FPA0 0xc6040
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#define PCH_FPA1 0xc6044
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#define PCH_FPB0 0xc6048
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#define PCH_FPB1 0xc604c
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#define PCH_FP0(pipe) _PIPE(pipe, PCH_FPA0, PCH_FPB0)
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#define PCH_FP1(pipe) _PIPE(pipe, PCH_FPA1, PCH_FPB1)
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#define PCH_DPLL_TEST 0xc606c
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@ -2704,6 +2733,13 @@
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#define TRANS_VBLANK_B 0xe1010
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#define TRANS_VSYNC_B 0xe1014
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#define TRANS_HTOTAL(pipe) _PIPE(pipe, TRANS_HTOTAL_A, TRANS_HTOTAL_B)
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#define TRANS_HBLANK(pipe) _PIPE(pipe, TRANS_HBLANK_A, TRANS_HBLANK_B)
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#define TRANS_HSYNC(pipe) _PIPE(pipe, TRANS_HSYNC_A, TRANS_HSYNC_B)
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#define TRANS_VTOTAL(pipe) _PIPE(pipe, TRANS_VTOTAL_A, TRANS_VTOTAL_B)
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#define TRANS_VBLANK(pipe) _PIPE(pipe, TRANS_VBLANK_A, TRANS_VBLANK_B)
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#define TRANS_VSYNC(pipe) _PIPE(pipe, TRANS_VSYNC_A, TRANS_VSYNC_B)
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#define TRANSB_DATA_M1 0xe1030
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#define TRANSB_DATA_N1 0xe1034
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#define TRANSB_DATA_M2 0xe1038
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@ -2715,6 +2751,7 @@
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#define TRANSACONF 0xf0008
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#define TRANSBCONF 0xf1008
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#define TRANSCONF(plane) _PIPE(plane, TRANSACONF, TRANSBCONF)
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#define TRANS_DISABLE (0<<31)
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#define TRANS_ENABLE (1<<31)
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#define TRANS_STATE_MASK (1<<30)
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@ -2739,6 +2776,7 @@
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/* CPU: FDI_TX */
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#define FDI_TXA_CTL 0x60100
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#define FDI_TXB_CTL 0x61100
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#define FDI_TX_CTL(pipe) _PIPE(pipe, FDI_TXA_CTL, FDI_TXB_CTL)
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#define FDI_TX_DISABLE (0<<31)
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#define FDI_TX_ENABLE (1<<31)
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#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
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@ -2780,8 +2818,8 @@
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/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
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#define FDI_RXA_CTL 0xf000c
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#define FDI_RXB_CTL 0xf100c
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#define FDI_RX_CTL(pipe) _PIPE(pipe, FDI_RXA_CTL, FDI_RXB_CTL)
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#define FDI_RX_ENABLE (1<<31)
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#define FDI_RX_DISABLE (0<<31)
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/* train, dp width same as FDI_TX */
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#define FDI_DP_PORT_WIDTH_X8 (7<<19)
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#define FDI_8BPC (0<<16)
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@ -2796,8 +2834,7 @@
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#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
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#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
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#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
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#define FDI_SEL_RAWCLK (0<<4)
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#define FDI_SEL_PCDCLK (1<<4)
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#define FDI_PCDCLK (1<<4)
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/* CPT */
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#define FDI_AUTO_TRAINING (1<<10)
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#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
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@ -2812,6 +2849,9 @@
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#define FDI_RXA_TUSIZE2 0xf0038
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#define FDI_RXB_TUSIZE1 0xf1030
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#define FDI_RXB_TUSIZE2 0xf1038
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#define FDI_RX_MISC(pipe) _PIPE(pipe, FDI_RXA_MISC, FDI_RXB_MISC)
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#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, FDI_RXA_TUSIZE1, FDI_RXB_TUSIZE1)
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#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, FDI_RXA_TUSIZE2, FDI_RXB_TUSIZE2)
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/* FDI_RX interrupt register format */
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#define FDI_RX_INTER_LANE_ALIGN (1<<10)
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@ -2830,6 +2870,8 @@
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#define FDI_RXA_IMR 0xf0018
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#define FDI_RXB_IIR 0xf1014
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#define FDI_RXB_IMR 0xf1018
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#define FDI_RX_IIR(pipe) _PIPE(pipe, FDI_RXA_IIR, FDI_RXB_IIR)
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#define FDI_RX_IMR(pipe) _PIPE(pipe, FDI_RXA_IMR, FDI_RXB_IMR)
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#define FDI_PLL_CTL_1 0xfe000
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#define FDI_PLL_CTL_2 0xfe004
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@ -2949,6 +2991,7 @@
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#define TRANS_DP_CTL_A 0xe0300
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#define TRANS_DP_CTL_B 0xe1300
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#define TRANS_DP_CTL_C 0xe2300
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#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
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#define TRANS_DP_OUTPUT_ENABLE (1<<31)
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#define TRANS_DP_PORT_SEL_B (0<<29)
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#define TRANS_DP_PORT_SEL_C (1<<29)
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File diff suppressed because it is too large
Load diff
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@ -255,7 +255,7 @@ i830_activate_pipe_a(struct drm_device *dev)
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return 0;
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/* most i8xx have pipe a forced on, so don't trust dpms mode */
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if (I915_READ(PIPEACONF) & PIPEACONF_ENABLE)
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if (I915_READ(PIPEACONF) & PIPECONF_ENABLE)
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return 0;
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crtc_funcs = crtc->base.helper_private;
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@ -876,15 +876,14 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
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{
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drm_i915_private_t *dev_priv = overlay->dev->dev_private;
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u32 pipeconf;
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int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
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if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
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return -EINVAL;
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pipeconf = I915_READ(pipeconf_reg);
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pipeconf = I915_READ(PIPECONF(crtc->pipe));
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/* can't use the overlay with double wide pipe */
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if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
|
||||
if (!IS_I965G(overlay->dev) && pipeconf & PIPECONF_DOUBLE_WIDE)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1168,7 +1168,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
|
|||
if (!IS_I9XX(dev))
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
|
||||
I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE);
|
||||
I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
|
||||
/* Wait for vblank for the disable to take effect. */
|
||||
intel_wait_for_vblank_off(dev, intel_crtc->pipe);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue