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Blackfin arch: Fix BUG -- BF533 + 0.5 silicon + MPU + UART PIO -> crash

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Apply ANOMALY_05000283 & ANOMALY_05000315
Workaround also to the EXCEPTION path.

Cover evt_ivhw also with ANOMALY_05000315
The Workaround needs to be prior to accesses (either read or write) to
any system MMR.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich 2008-10-09 12:31:03 +08:00 committed by Bryan Wu
parent 49f7253cc9
commit 5e9e7687cb
2 changed files with 19 additions and 1 deletions
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18
arch/blackfin/mach-common/entry.S
View file

@ -484,6 +484,15 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
[--sp] = ASTAT; [--sp] = ASTAT;
[--sp] = (R7:6,P5:4); [--sp] = (R7:6,P5:4);
#if ANOMALY_05000283 || ANOMALY_05000315
cc = r7 == r7;
p5.h = HI(CHIPID);
p5.l = LO(CHIPID);
if cc jump 1f;
r7.l = W[p5];
1:
#endif
#ifdef CONFIG_DEBUG_DOUBLEFAULT #ifdef CONFIG_DEBUG_DOUBLEFAULT
/* /*
* Save these registers, as they are only valid in exception context * Save these registers, as they are only valid in exception context
@ -1020,6 +1029,15 @@ ENTRY(_early_trap)
SAVE_ALL_SYS SAVE_ALL_SYS
trace_buffer_stop(p0,r0); trace_buffer_stop(p0,r0);
#if ANOMALY_05000283 || ANOMALY_05000315
cc = r5 == r5;
p4.h = HI(CHIPID);
p4.l = LO(CHIPID);
if cc jump 1f;
r5.l = W[p4];
1:
#endif
/* Turn caches off, to ensure we don't get double exceptions */ /* Turn caches off, to ensure we don't get double exceptions */
P4.L = LO(IMEM_CONTROL); P4.L = LO(IMEM_CONTROL);

2
arch/blackfin/mach-common/interrupt.S
View file

@ -143,7 +143,7 @@ ENTRY(_evt_ivhw)
fp = 0; fp = 0;
#endif #endif
#if ANOMALY_05000283 #if ANOMALY_05000283 || ANOMALY_05000315
cc = r7 == r7; cc = r7 == r7;
p5.h = HI(CHIPID); p5.h = HI(CHIPID);
p5.l = LO(CHIPID); p5.l = LO(CHIPID);