mvebu cache-l2x0 for v3.8

- Add support for l2x0 cache on mvebu boards
 
  - Depends on mvebu/everything
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.19 (GNU/Linux)
 
 iQEcBAABAgAGBQJQtOFbAAoJEAi3KVZQDZAeRbkH/3IWYaAFXi6wnM4yHdYJbp5A
 X1375b4Tkjd2Q05gujtNZLDS1gR4O65gJ9nxoV4OuYtqt1WnFUTDU4WozaYFdj8G
 1hojkI6qKUddV+EZdMkx1/0YXORsNbGx8PHFPzsLfMHL/qEWjdMgOf4UW+9AogVt
 hOwQwIs7SuhDnu0QR0dUH65iU848n5dYSczr/j71l2fqooJ/+KaU1hKKYf/rFvX2
 3f9TaDydeglgAUGs7FUL1EbuLQiygIGy1wDhxyVK+g7inAzdQGzVZ7faK8M3NScM
 YixWH+uy35ZAS8LlPCpY7DFts4pMtB/5fFvWiMYaBXv53mClgqSaymQDZLObJi8=
 =rcOU
 -----END PGP SIGNATURE-----

Merge tag 'mvebu_cache_l2x0_for_3.8' of git://git.infradead.org/users/jcooper/linux into late/mvebu

From Jason Cooper:
mvebu cache-l2x0 for v3.8

 - Add support for l2x0 cache on mvebu boards

 - Depends on mvebu/everything

* tag 'mvebu_cache_l2x0_for_3.8' of git://git.infradead.org/users/jcooper/linux:
  arm: l2x0: add aurora related properties to OF binding
  arm: mvebu: add Aurora L2 Cache Controller to the DT
  arm: mvebu: add L2 cache support

Documentation/devicetree/bindings/arm/l2cc.txt

@@ -10,6 +10,12 @@ Required properties:
 	"arm,pl310-cache"
 	"arm,l220-cache"
 	"arm,l210-cache"
+	"marvell,aurora-system-cache": Marvell Controller designed to be
+     compatible with the ARM one, with system cache mode (meaning
+     maintenance operations on L1 are broadcasted to the L2 and L2
+     performs the same operation).
+	"marvell,"aurora-outer-cache: Marvell Controller designed to be
+	 compatible with the ARM one with outer cache mode.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties:
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
 - interrupts : 1 combined interrupt.
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
 
 Example:
 

arch/arm/boot/dts/armada-370.dtsi

@@ -20,6 +20,12 @@
 / {
 	model = "Marvell Armada 370 family SoC";
 	compatible = "marvell,armada370", "marvell,armada-370-xp";
+	L2: l2-cache {
+		compatible = "marvell,aurora-outer-cache";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
 
 	aliases {
 		gpio0 = &gpio0;

arch/arm/boot/dts/armada-xp.dtsi

@@ -22,6 +22,13 @@
 	model = "Marvell Armada XP family SoC";
 	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+	L2: l2-cache {
+		compatible = "marvell,aurora-system-cache";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
+
 	mpic: interrupt-controller@d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
 		    <0xd0021070 0x58>;

arch/arm/mach-mvebu/Kconfig

@@ -22,6 +22,7 @@ config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
 	select HAVE_SMP
+	select CACHE_L2X0
 	select CPU_PJ4B
 
 config MACH_ARMADA_370

arch/arm/mach-mvebu/irq-armada-370-xp.c

@@ -25,6 +25,7 @@
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
 #include <asm/smp_plat.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -210,4 +211,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
 void __init armada_370_xp_init_irq(void)
 {
 	of_irq_init(mpic_of_match);
+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
 }