cciss: add performant mode support for Stars/Sirius
Add a mode of controller operation called Performant Mode. Even though cciss has been deprecated in favor of hpsa there are new controllers due out next year that HP must support in older vendor distros. Vendors require all fixes/features be upstream. These new controllers support only 16 commands in simple mode but support up to 1024 in performant mode. This requires us to add this support at this late date. The performant mode transport minimizes host PCI accesses by performinf many completions per read. PCI writes are posted so the host can write then immediately get off the bus not waiting for the writwe to complete to the target. In the context of performant mode the host read out to a controller pulls all posted writes into host memory ensuring the reply queue is coherent. Signed-off-by: Mike Miller <mike.miller@hp.com> Cc: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jens Axboe <jaxboe@fusionio.com>
This commit is contained in:
Mike Miller
Jens Axboe
parent
1d1414419f
commit
5e216153c3
4 changed files with 353 additions and 63 deletions
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@ -206,6 +206,11 @@ static void cciss_device_release(struct device *dev);
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static void cciss_free_gendisk(ctlr_info_t *h, int drv_index);
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static void cciss_free_drive_info(ctlr_info_t *h, int drv_index);
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/* performant mode helper functions */
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static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,
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int *bucket_map);
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static void cciss_put_controller_into_performant_mode(ctlr_info_t *h);
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#ifdef CONFIG_PROC_FS
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static void cciss_procinit(int i);
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#else
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@ -231,6 +236,16 @@ static const struct block_device_operations cciss_fops = {
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.revalidate_disk = cciss_revalidate,
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};
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/* set_performant_mode: Modify the tag for cciss performant
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* set bit 0 for pull model, bits 3-1 for block fetch
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* register number
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*/
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static void set_performant_mode(ctlr_info_t *h, CommandList_struct *c)
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{
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if (likely(h->transMethod == CFGTBL_Trans_Performant))
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c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
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}
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/*
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* Enqueuing and dequeuing functions for cmdlists.
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*/
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@ -261,6 +276,7 @@ static void enqueue_cmd_and_start_io(ctlr_info_t *h,
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CommandList_struct *c)
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{
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unsigned long flags;
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set_performant_mode(h, c);
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spin_lock_irqsave(&h->lock, flags);
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addQ(&h->reqQ, c);
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h->Qdepth++;
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@ -350,6 +366,28 @@ static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
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#ifdef CONFIG_PROC_FS
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static inline u32 next_command(ctlr_info_t *h)
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{
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u32 a;
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if (unlikely(h->transMethod != CFGTBL_Trans_Performant))
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return h->access.command_completed(h);
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if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
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a = *(h->reply_pool_head); /* Next cmd in ring buffer */
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(h->reply_pool_head)++;
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h->commands_outstanding--;
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} else {
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a = FIFO_EMPTY;
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}
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/* Check for wraparound */
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if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
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h->reply_pool_head = h->reply_pool;
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h->reply_pool_wraparound ^= 1;
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}
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return a;
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}
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/*
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* Report information about this controller.
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*/
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@ -377,7 +415,7 @@ static void cciss_seq_show_header(struct seq_file *seq)
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h->product_name,
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(unsigned long)h->board_id,
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h->firm_ver[0], h->firm_ver[1], h->firm_ver[2],
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h->firm_ver[3], (unsigned int)h->intr[SIMPLE_MODE_INT],
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h->firm_ver[3], (unsigned int)h->intr[PERF_MODE_INT],
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h->num_luns,
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h->Qdepth, h->commands_outstanding,
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h->maxQsinceinit, h->max_outstanding, h->maxSG);
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@ -3126,13 +3164,13 @@ static inline void complete_command(ctlr_info_t *h, CommandList_struct *cmd,
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static inline u32 cciss_tag_contains_index(u32 tag)
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{
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#define DIRECT_LOOKUP_BIT 0x04
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#define DIRECT_LOOKUP_BIT 0x10
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return tag & DIRECT_LOOKUP_BIT;
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}
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static inline u32 cciss_tag_to_index(u32 tag)
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{
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#define DIRECT_LOOKUP_SHIFT 3
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#define DIRECT_LOOKUP_SHIFT 5
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return tag >> DIRECT_LOOKUP_SHIFT;
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}
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@ -3262,9 +3300,12 @@ static void do_cciss_request(struct request_queue *q)
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blk_rq_sectors(creq), seg, chained);
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#endif /* CCISS_DEBUG */
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c->Header.SGList = c->Header.SGTotal = seg + chained;
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if (seg > h->max_cmd_sgentries)
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c->Header.SGTotal = seg + chained;
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if (seg <= h->max_cmd_sgentries)
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c->Header.SGList = c->Header.SGTotal;
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else
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c->Header.SGList = h->max_cmd_sgentries;
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set_performant_mode(h, c);
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if (likely(blk_fs_request(creq))) {
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if(h->cciss_read == CCISS_READ_10) {
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@ -3370,10 +3411,10 @@ static inline u32 process_indexed_cmd(ctlr_info_t *h, u32 raw_tag)
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tag_index = cciss_tag_to_index(raw_tag);
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if (bad_tag(h, tag_index, raw_tag))
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return get_next_completion(h);
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return next_command(h);
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c = h->cmd_pool + tag_index;
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finish_cmd(h, c, raw_tag);
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return get_next_completion(h);
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return next_command(h);
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}
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/* process completion of a non-indexed command */
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@ -3390,11 +3431,11 @@ static inline u32 process_nonindexed_cmd(ctlr_info_t *h, u32 raw_tag)
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tag_masked = cciss_tag_discard_error_bits(tag);
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if (busaddr_masked == tag_masked) {
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finish_cmd(h, c, raw_tag);
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return get_next_completion(h);
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return next_command(h);
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}
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}
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bad_tag(h, h->nr_cmds + 1, raw_tag);
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return get_next_completion(h);
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return next_command(h);
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}
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static irqreturn_t do_cciss_intx(int irq, void *dev_id)
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@ -3700,6 +3741,155 @@ static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
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return -1;
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}
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/* Fill in bucket_map[], given nsgs (the max number of
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* scatter gather elements supported) and bucket[],
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* which is an array of 8 integers. The bucket[] array
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* contains 8 different DMA transfer sizes (in 16
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* byte increments) which the controller uses to fetch
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* commands. This function fills in bucket_map[], which
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* maps a given number of scatter gather elements to one of
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* the 8 DMA transfer sizes. The point of it is to allow the
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* controller to only do as much DMA as needed to fetch the
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* command, with the DMA transfer size encoded in the lower
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* bits of the command address.
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*/
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static void calc_bucket_map(int bucket[], int num_buckets,
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int nsgs, int *bucket_map)
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{
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int i, j, b, size;
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/* even a command with 0 SGs requires 4 blocks */
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#define MINIMUM_TRANSFER_BLOCKS 4
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#define NUM_BUCKETS 8
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/* Note, bucket_map must have nsgs+1 entries. */
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for (i = 0; i <= nsgs; i++) {
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/* Compute size of a command with i SG entries */
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size = i + MINIMUM_TRANSFER_BLOCKS;
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b = num_buckets; /* Assume the biggest bucket */
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/* Find the bucket that is just big enough */
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for (j = 0; j < 8; j++) {
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if (bucket[j] >= size) {
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b = j;
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break;
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}
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}
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/* for a command with i SG entries, use bucket b. */
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bucket_map[i] = b;
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}
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}
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static void
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cciss_put_controller_into_performant_mode(ctlr_info_t *h)
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{
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int l = 0;
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__u32 trans_support;
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__u32 trans_offset;
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/*
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* 5 = 1 s/g entry or 4k
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* 6 = 2 s/g entry or 8k
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* 8 = 4 s/g entry or 16k
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* 10 = 6 s/g entry or 24k
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*/
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int bft[8] = { 5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
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unsigned long register_value;
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BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
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/* Attempt to put controller into performant mode if supported */
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/* Does board support performant mode? */
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trans_support = readl(&(h->cfgtable->TransportSupport));
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if (!(trans_support & PERFORMANT_MODE))
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return;
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printk(KERN_WARNING "cciss%d: Placing controller into "
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"performant mode\n", h->ctlr);
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/* Performant mode demands commands on a 32 byte boundary
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* pci_alloc_consistent aligns on page boundarys already.
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* Just need to check if divisible by 32
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*/
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if ((sizeof(CommandList_struct) % 32) != 0) {
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printk(KERN_WARNING "%s %d %s\n",
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"cciss info: command size[",
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(int)sizeof(CommandList_struct),
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"] not divisible by 32, no performant mode..\n");
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return;
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}
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/* Performant mode ring buffer and supporting data structures */
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h->reply_pool = (__u64 *)pci_alloc_consistent(
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h->pdev, h->max_commands * sizeof(__u64),
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&(h->reply_pool_dhandle));
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/* Need a block fetch table for performant mode */
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h->blockFetchTable = kmalloc(((h->maxsgentries+1) *
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sizeof(__u32)), GFP_KERNEL);
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if ((h->reply_pool == NULL) || (h->blockFetchTable == NULL))
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goto clean_up;
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h->reply_pool_wraparound = 1; /* spec: init to 1 */
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/* Controller spec: zero out this buffer. */
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memset(h->reply_pool, 0, h->max_commands * sizeof(__u64));
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h->reply_pool_head = h->reply_pool;
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trans_offset = readl(&(h->cfgtable->TransMethodOffset));
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calc_bucket_map(bft, ARRAY_SIZE(bft), h->maxsgentries,
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h->blockFetchTable);
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writel(bft[0], &h->transtable->BlockFetch0);
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writel(bft[1], &h->transtable->BlockFetch1);
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writel(bft[2], &h->transtable->BlockFetch2);
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writel(bft[3], &h->transtable->BlockFetch3);
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writel(bft[4], &h->transtable->BlockFetch4);
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writel(bft[5], &h->transtable->BlockFetch5);
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writel(bft[6], &h->transtable->BlockFetch6);
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writel(bft[7], &h->transtable->BlockFetch7);
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/* size of controller ring buffer */
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writel(h->max_commands, &h->transtable->RepQSize);
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writel(1, &h->transtable->RepQCount);
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writel(0, &h->transtable->RepQCtrAddrLow32);
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writel(0, &h->transtable->RepQCtrAddrHigh32);
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writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
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writel(0, &h->transtable->RepQAddr0High32);
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writel(CFGTBL_Trans_Performant,
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&(h->cfgtable->HostWrite.TransportRequest));
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h->transMethod = CFGTBL_Trans_Performant;
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writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
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/* under certain very rare conditions, this can take awhile.
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* (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
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* as we enter this code.) */
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for (l = 0; l < MAX_CONFIG_WAIT; l++) {
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register_value = readl(h->vaddr + SA5_DOORBELL);
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if (!(register_value & CFGTBL_ChangeReq))
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break;
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/* delay and try again */
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set_current_state(TASK_INTERRUPTIBLE);
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schedule_timeout(10);
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}
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register_value = readl(&(h->cfgtable->TransportActive));
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if (!(register_value & CFGTBL_Trans_Performant)) {
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printk(KERN_WARNING "cciss: unable to get board into"
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" performant mode\n");
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return;
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}
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/* Change the access methods to the performant access methods */
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h->access = SA5_performant_access;
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return;
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clean_up:
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kfree(h->blockFetchTable);
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if (h->reply_pool)
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pci_free_consistent(h->pdev,
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h->max_commands * sizeof(__u64),
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h->reply_pool,
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h->reply_pool_dhandle);
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return;
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} /* cciss_put_controller_into_performant_mode */
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/* If MSI/MSI-X is supported by the kernel we will try to enable it on
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* controllers that are capable. If not, we use IO-APIC mode.
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*/
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@ -3749,7 +3939,7 @@ static void __devinit cciss_interrupt_mode(ctlr_info_t *c,
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default_int_mode:
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#endif /* CONFIG_PCI_MSI */
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/* if we get here we're going to use the default interrupt mode */
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c->intr[SIMPLE_MODE_INT] = pdev->irq;
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c->intr[PERF_MODE_INT] = pdev->irq;
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return;
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}
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@ -3761,6 +3951,7 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
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__u32 cfg_base_addr;
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__u64 cfg_base_addr_index;
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int i, prod_index, err;
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__u32 trans_offset;
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subsystem_vendor_id = pdev->subsystem_vendor;
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subsystem_device_id = pdev->subsystem_device;
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@ -3874,11 +4065,16 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
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c->cfgtable = remap_pci_mem(pci_resource_start(pdev,
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cfg_base_addr_index) +
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cfg_offset, sizeof(CfgTable_struct));
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/* Find performant mode table. */
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trans_offset = readl(&(c->cfgtable->TransMethodOffset));
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c->transtable = remap_pci_mem(pci_resource_start(pdev,
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cfg_base_addr_index) + cfg_offset+trans_offset,
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sizeof(*c->transtable));
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c->board_id = board_id;
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#ifdef CCISS_DEBUG
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print_cfg_table(c->cfgtable);
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#endif /* CCISS_DEBUG */
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#ifdef CCISS_DEBUG
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print_cfg_table(c->cfgtable);
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#endif /* CCISS_DEBUG */
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/* Some controllers support Zero Memory Raid (ZMR).
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* When configured in ZMR mode the number of supported
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@ -3888,7 +4084,7 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
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* are supported on the controller then subtract 4 to
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* leave a little room for ioctl calls.
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*/
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c->max_commands = readl(&(c->cfgtable->CmdsOutMax));
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c->max_commands = readl(&(c->cfgtable->MaxPerformantModeCommands));
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c->maxsgentries = readl(&(c->cfgtable->MaxSGElements));
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/*
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@ -3933,7 +4129,7 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
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* kernels revealed a bug in the refetch if dom0 resides on a P600.
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*/
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if(board_id == 0x3225103C) {
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__u32 dma_prefetch;
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__u32 dma_prefetch;
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__u32 dma_refetch;
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dma_prefetch = readl(c->vaddr + I2O_DMA1_CFG);
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dma_prefetch |= 0x8000;
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@ -3944,38 +4140,8 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
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}
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#ifdef CCISS_DEBUG
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printk("Trying to put board into Simple mode\n");
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printk(KERN_WARNING "Trying to put board into Performant mode\n");
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#endif /* CCISS_DEBUG */
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c->max_commands = readl(&(c->cfgtable->CmdsOutMax));
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/* Update the field, and then ring the doorbell */
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writel(CFGTBL_Trans_Simple, &(c->cfgtable->HostWrite.TransportRequest));
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writel(CFGTBL_ChangeReq, c->vaddr + SA5_DOORBELL);
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/* under certain very rare conditions, this can take awhile.
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* (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
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* as we enter this code.) */
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for (i = 0; i < MAX_CONFIG_WAIT; i++) {
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if (!(readl(c->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
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break;
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/* delay and try again */
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set_current_state(TASK_INTERRUPTIBLE);
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schedule_timeout(msecs_to_jiffies(1));
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}
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#ifdef CCISS_DEBUG
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printk(KERN_DEBUG "I counter got to %d %x\n", i,
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readl(c->vaddr + SA5_DOORBELL));
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#endif /* CCISS_DEBUG */
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#ifdef CCISS_DEBUG
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print_cfg_table(c->cfgtable);
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#endif /* CCISS_DEBUG */
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if (!(readl(&(c->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
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printk(KERN_WARNING "cciss: unable to get board into"
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" simple mode\n");
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err = -ENODEV;
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goto err_out_free_res;
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}
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return 0;
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err_out_free_res:
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@ -3984,6 +4150,7 @@ static int __devinit cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
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* Smart Array controllers that pci_enable_device does not undo
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*/
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pci_release_regions(pdev);
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cciss_put_controller_into_performant_mode(c);
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return err;
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}
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@ -4260,7 +4427,6 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
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i = alloc_cciss_hba();
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if (i < 0)
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return -1;
|
||||
|
||||
hba[i]->busy_initializing = 1;
|
||||
INIT_HLIST_HEAD(&hba[i]->cmpQ);
|
||||
INIT_HLIST_HEAD(&hba[i]->reqQ);
|
||||
|
|
@ -4327,7 +4493,7 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
|
|||
|
||||
printk(KERN_INFO "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
|
||||
hba[i]->devname, pdev->device, pci_name(pdev),
|
||||
hba[i]->intr[SIMPLE_MODE_INT], dac ? "" : " not");
|
||||
hba[i]->intr[PERF_MODE_INT], dac ? "" : " not");
|
||||
|
||||
hba[i]->cmd_pool_bits =
|
||||
kmalloc(DIV_ROUND_UP(hba[i]->nr_cmds, BITS_PER_LONG)
|
||||
|
|
@ -4433,7 +4599,7 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
|
|||
hba[i]->nr_cmds * sizeof(ErrorInfo_struct),
|
||||
hba[i]->errinfo_pool,
|
||||
hba[i]->errinfo_pool_dhandle);
|
||||
free_irq(hba[i]->intr[SIMPLE_MODE_INT], hba[i]);
|
||||
free_irq(hba[i]->intr[PERF_MODE_INT], hba[i]);
|
||||
clean2:
|
||||
unregister_blkdev(hba[i]->major, hba[i]->devname);
|
||||
clean1:
|
||||
|
|
@ -4475,7 +4641,7 @@ static void cciss_shutdown(struct pci_dev *pdev)
|
|||
printk(KERN_WARNING "cciss%d: Error flushing cache\n",
|
||||
h->ctlr);
|
||||
h->access.set_intr_mask(h, CCISS_INTR_OFF);
|
||||
free_irq(h->intr[2], h);
|
||||
free_irq(h->intr[PERF_MODE_INT], h);
|
||||
}
|
||||
|
||||
static void __devexit cciss_remove_one(struct pci_dev *pdev)
|
||||
|
|
@ -4575,7 +4741,6 @@ static int __init cciss_init(void)
|
|||
* array of them, the size must be a multiple of 8 bytes.
|
||||
*/
|
||||
BUILD_BUG_ON(sizeof(CommandList_struct) % COMMANDLIST_ALIGNMENT);
|
||||
|
||||
printk(KERN_INFO DRIVER_NAME "\n");
|
||||
|
||||
err = bus_register(&cciss_bus_type);
|
||||
|
|
|
|||
|
|
@ -85,8 +85,8 @@ struct ctlr_info
|
|||
int max_cmd_sgentries;
|
||||
SGDescriptor_struct **cmd_sg_list;
|
||||
|
||||
# define DOORBELL_INT 0
|
||||
# define PERF_MODE_INT 1
|
||||
# define PERF_MODE_INT 0
|
||||
# define DOORBELL_INT 1
|
||||
# define SIMPLE_MODE_INT 2
|
||||
# define MEMQ_MODE_INT 3
|
||||
unsigned int intr[4];
|
||||
|
|
@ -137,10 +137,27 @@ struct ctlr_info
|
|||
struct list_head scan_list;
|
||||
struct completion scan_wait;
|
||||
struct device dev;
|
||||
/*
|
||||
* Performant mode tables.
|
||||
*/
|
||||
u32 trans_support;
|
||||
u32 trans_offset;
|
||||
struct TransTable_struct *transtable;
|
||||
unsigned long transMethod;
|
||||
|
||||
/*
|
||||
* Performant mode completion buffer
|
||||
*/
|
||||
u64 *reply_pool;
|
||||
dma_addr_t reply_pool_dhandle;
|
||||
u64 *reply_pool_head;
|
||||
size_t reply_pool_size;
|
||||
unsigned char reply_pool_wraparound;
|
||||
u32 *blockFetchTable;
|
||||
};
|
||||
|
||||
/* Defining the diffent access_menthods */
|
||||
/*
|
||||
/* Defining the diffent access_methods
|
||||
*
|
||||
* Memory mapped FIFO interface (SMART 53xx cards)
|
||||
*/
|
||||
#define SA5_DOORBELL 0x20
|
||||
|
|
@ -159,6 +176,15 @@ struct ctlr_info
|
|||
#define SA5B_INTR_PENDING 0x04
|
||||
#define FIFO_EMPTY 0xffffffff
|
||||
#define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
|
||||
/* Perf. mode flags */
|
||||
#define SA5_PERF_INTR_PENDING 0x04
|
||||
#define SA5_PERF_INTR_OFF 0x05
|
||||
#define SA5_OUTDB_STATUS_PERF_BIT 0x01
|
||||
#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
|
||||
#define SA5_OUTDB_CLEAR 0xA0
|
||||
#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
|
||||
#define SA5_OUTDB_STATUS 0x9C
|
||||
|
||||
|
||||
#define CISS_ERROR_BIT 0x02
|
||||
|
||||
|
|
@ -170,8 +196,9 @@ struct ctlr_info
|
|||
static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
|
||||
{
|
||||
#ifdef CCISS_DEBUG
|
||||
printk("Sending %x - down to controller\n", c->busaddr );
|
||||
#endif /* CCISS_DEBUG */
|
||||
printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
|
||||
h->ctlr, c->busaddr);
|
||||
#endif /* CCISS_DEBUG */
|
||||
writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
|
||||
h->commands_outstanding++;
|
||||
if ( h->commands_outstanding > h->max_outstanding)
|
||||
|
|
@ -214,6 +241,20 @@ static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
|
|||
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
/* Performant mode intr_mask */
|
||||
static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
|
||||
{
|
||||
if (val) { /* turn on interrupts */
|
||||
h->interrupts_enabled = 1;
|
||||
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
|
||||
} else {
|
||||
h->interrupts_enabled = 0;
|
||||
writel(SA5_PERF_INTR_OFF,
|
||||
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns true if fifo is full.
|
||||
*
|
||||
|
|
@ -250,6 +291,40 @@ static unsigned long SA5_completed(ctlr_info_t *h)
|
|||
return ( register_value);
|
||||
|
||||
}
|
||||
|
||||
/* Performant mode command completed */
|
||||
static unsigned long SA5_performant_completed(ctlr_info_t *h)
|
||||
{
|
||||
unsigned long register_value = FIFO_EMPTY;
|
||||
|
||||
/* flush the controller write of the reply queue by reading
|
||||
* outbound doorbell status register.
|
||||
*/
|
||||
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
||||
/* msi auto clears the interrupt pending bit. */
|
||||
if (!(h->msi_vector || h->msix_vector)) {
|
||||
writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
|
||||
/* Do a read in order to flush the write to the controller
|
||||
* (as per spec.)
|
||||
*/
|
||||
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
||||
}
|
||||
|
||||
if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
|
||||
register_value = *(h->reply_pool_head);
|
||||
(h->reply_pool_head)++;
|
||||
h->commands_outstanding--;
|
||||
} else {
|
||||
register_value = FIFO_EMPTY;
|
||||
}
|
||||
/* Check for wraparound */
|
||||
if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
|
||||
h->reply_pool_head = h->reply_pool;
|
||||
h->reply_pool_wraparound ^= 1;
|
||||
}
|
||||
|
||||
return register_value;
|
||||
}
|
||||
/*
|
||||
* Returns true if an interrupt is pending..
|
||||
*/
|
||||
|
|
@ -280,6 +355,20 @@ static bool SA5B_intr_pending(ctlr_info_t *h)
|
|||
return 0 ;
|
||||
}
|
||||
|
||||
static bool SA5_performant_intr_pending(ctlr_info_t *h)
|
||||
{
|
||||
unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
|
||||
|
||||
if (!register_value)
|
||||
return false;
|
||||
|
||||
if (h->msi_vector || h->msix_vector)
|
||||
return true;
|
||||
|
||||
/* Read outbound doorbell to flush */
|
||||
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
||||
return register_value & SA5_OUTDB_STATUS_PERF_BIT;
|
||||
}
|
||||
|
||||
static struct access_method SA5_access = {
|
||||
SA5_submit_command,
|
||||
|
|
@ -297,6 +386,14 @@ static struct access_method SA5B_access = {
|
|||
SA5_completed,
|
||||
};
|
||||
|
||||
static struct access_method SA5_performant_access = {
|
||||
SA5_submit_command,
|
||||
SA5_performant_intr_mask,
|
||||
SA5_fifo_full,
|
||||
SA5_performant_intr_pending,
|
||||
SA5_performant_completed,
|
||||
};
|
||||
|
||||
struct board_type {
|
||||
__u32 board_id;
|
||||
char *product_name;
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@
|
|||
#define CFGTBL_AccCmds 0x00000001l
|
||||
|
||||
#define CFGTBL_Trans_Simple 0x00000002l
|
||||
#define CFGTBL_Trans_Performant 0x00000004l
|
||||
|
||||
#define CFGTBL_BusType_Ultra2 0x00000001l
|
||||
#define CFGTBL_BusType_Ultra3 0x00000002l
|
||||
|
|
@ -173,12 +174,15 @@ typedef struct _SGDescriptor_struct {
|
|||
* PAD_64 can be adjusted independently as needed for 32-bit
|
||||
* and 64-bits systems.
|
||||
*/
|
||||
#define COMMANDLIST_ALIGNMENT (8)
|
||||
#define COMMANDLIST_ALIGNMENT (32)
|
||||
#define IS_64_BIT ((sizeof(long) - 4)/4)
|
||||
#define IS_32_BIT (!IS_64_BIT)
|
||||
#define PAD_32 (0)
|
||||
#define PAD_32 (32)
|
||||
#define PAD_64 (4)
|
||||
#define PADSIZE (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
|
||||
#define DIRECT_LOOKUP_BIT 0x10
|
||||
#define DIRECT_LOOKUP_SHIFT 5
|
||||
|
||||
typedef struct _CommandList_struct {
|
||||
CommandListHeader_struct Header;
|
||||
RequestBlock_struct Request;
|
||||
|
|
@ -195,7 +199,7 @@ typedef struct _CommandList_struct {
|
|||
struct completion *waiting;
|
||||
int retry_count;
|
||||
void * scsi_cmd;
|
||||
char pad[PADSIZE];
|
||||
char pad[PADSIZE];
|
||||
} CommandList_struct;
|
||||
|
||||
/* Configuration Table Structure */
|
||||
|
|
@ -209,12 +213,15 @@ typedef struct _HostWrite_struct {
|
|||
typedef struct _CfgTable_struct {
|
||||
BYTE Signature[4];
|
||||
DWORD SpecValence;
|
||||
#define SIMPLE_MODE 0x02
|
||||
#define PERFORMANT_MODE 0x04
|
||||
#define MEMQ_MODE 0x08
|
||||
DWORD TransportSupport;
|
||||
DWORD TransportActive;
|
||||
HostWrite_struct HostWrite;
|
||||
DWORD CmdsOutMax;
|
||||
DWORD BusTypes;
|
||||
DWORD Reserved;
|
||||
DWORD TransMethodOffset;
|
||||
BYTE ServerName[16];
|
||||
DWORD HeartBeat;
|
||||
DWORD SCSI_Prefetch;
|
||||
|
|
@ -222,6 +229,25 @@ typedef struct _CfgTable_struct {
|
|||
DWORD MaxLogicalUnits;
|
||||
DWORD MaxPhysicalDrives;
|
||||
DWORD MaxPhysicalDrivesPerLogicalUnit;
|
||||
DWORD MaxPerformantModeCommands;
|
||||
} CfgTable_struct;
|
||||
|
||||
struct TransTable_struct {
|
||||
u32 BlockFetch0;
|
||||
u32 BlockFetch1;
|
||||
u32 BlockFetch2;
|
||||
u32 BlockFetch3;
|
||||
u32 BlockFetch4;
|
||||
u32 BlockFetch5;
|
||||
u32 BlockFetch6;
|
||||
u32 BlockFetch7;
|
||||
u32 RepQSize;
|
||||
u32 RepQCount;
|
||||
u32 RepQCtrAddrLow32;
|
||||
u32 RepQCtrAddrHigh32;
|
||||
u32 RepQAddr0Low32;
|
||||
u32 RepQAddr0High32;
|
||||
};
|
||||
|
||||
#pragma pack()
|
||||
#endif /* CCISS_CMD_H */
|
||||
|
|
|
|||
|
|
@ -93,8 +93,8 @@ static struct scsi_host_template cciss_driver_template = {
|
|||
|
||||
#pragma pack(1)
|
||||
|
||||
#define SCSI_PAD_32 0
|
||||
#define SCSI_PAD_64 0
|
||||
#define SCSI_PAD_32 8
|
||||
#define SCSI_PAD_64 8
|
||||
|
||||
struct cciss_scsi_cmd_stack_elem_t {
|
||||
CommandList_struct cmd;
|
||||
|
|
@ -213,6 +213,8 @@ scsi_cmd_stack_setup(int ctlr, struct cciss_scsi_adapter_data_t *sa)
|
|||
|
||||
/* Check alignment, see cciss_cmd.h near CommandList_struct def. */
|
||||
BUILD_BUG_ON((sizeof(*stk->pool) % COMMANDLIST_ALIGNMENT) != 0);
|
||||
/* printk(KERN_WARNING "cciss_scsi.c: 0x%08x 0x%08x 0x%08x\n",
|
||||
0xdeadbeef, sizeof(*stk->pool), 0xbeefdead); */
|
||||
/* pci_alloc_consistent guarantees 32-bit DMA address will be used */
|
||||
stk->pool = (struct cciss_scsi_cmd_stack_elem_t *)
|
||||
pci_alloc_consistent(hba[ctlr]->pdev, size, &stk->cmd_pool_handle);
|
||||
|
|
|
|||
Loading…
Reference in a new issue