Merge branches 'pm-cpuidle', 'pm-devfreq' and 'pm-clk'
* pm-cpuidle: cpuidle/coupled: Remove redundant 'dev' argument of cpuidle_state_is_coupled() cpuidle/coupled: Remove cpuidle_device::safe_state_index intel_idle: Skylake Client Support intel_idle: allow idle states to be freeze-mode specific * pm-devfreq: PM / devfreq: exynos-ppmu: Update documentation to support PPMUv2 PM / devfreq: exynos-ppmu: Add the support of PPMUv2 for Exynos5433 PM / devfreq: event: Remove incorrect property in exynos-ppmu DT binding * pm-clk: PM / clk: don't return int on __pm_clk_enable()
This commit is contained in:
Rafael J. Wysocki
commit
5cf896b3c7
9 changed files with 353 additions and 26 deletions
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@ -11,15 +11,14 @@ to various devfreq devices. The devfreq devices would use the event data when
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derterming the current state of each IP.
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Required properties:
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- compatible: Should be "samsung,exynos-ppmu".
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- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
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- reg: physical base address of each PPMU and length of memory mapped region.
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Optional properties:
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- clock-names : the name of clock used by the PPMU, "ppmu"
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- clocks : phandles for clock specified in "clock-names" property
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- #clock-cells: should be 1.
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Example1 : PPMU nodes in exynos3250.dtsi are listed below.
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Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
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ppmu_dmc0: ppmu_dmc0@106a0000 {
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compatible = "samsung,exynos-ppmu";
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@ -108,3 +107,41 @@ Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
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};
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};
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};
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Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
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ppmu_d0_cpu: ppmu_d0_cpu@10480000 {
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compatible = "samsung,exynos-ppmu-v2";
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reg = <0x10480000 0x2000>;
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status = "disabled";
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};
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ppmu_d0_general: ppmu_d0_general@10490000 {
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compatible = "samsung,exynos-ppmu-v2";
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reg = <0x10490000 0x2000>;
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status = "disabled";
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};
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ppmu_d0_rt: ppmu_d0_rt@104a0000 {
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compatible = "samsung,exynos-ppmu-v2";
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reg = <0x104a0000 0x2000>;
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status = "disabled";
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};
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ppmu_d1_cpu: ppmu_d1_cpu@104b0000 {
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compatible = "samsung,exynos-ppmu-v2";
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reg = <0x104b0000 0x2000>;
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status = "disabled";
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};
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ppmu_d1_general: ppmu_d1_general@104c0000 {
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compatible = "samsung,exynos-ppmu-v2";
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reg = <0x104c0000 0x2000>;
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status = "disabled";
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};
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ppmu_d1_rt: ppmu_d1_rt@104d0000 {
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compatible = "samsung,exynos-ppmu-v2";
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reg = <0x104d0000 0x2000>;
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status = "disabled";
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};
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@ -38,7 +38,7 @@ struct pm_clock_entry {
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* @dev: The device for the given clock
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* @ce: PM clock entry corresponding to the clock.
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*/
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static inline int __pm_clk_enable(struct device *dev, struct pm_clock_entry *ce)
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static inline void __pm_clk_enable(struct device *dev, struct pm_clock_entry *ce)
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{
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int ret;
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@ -50,8 +50,6 @@ static inline int __pm_clk_enable(struct device *dev, struct pm_clock_entry *ce)
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dev_err(dev, "%s: failed to enable clk %p, error %d\n",
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__func__, ce->clk, ret);
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}
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return ret;
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}
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/**
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@ -176,14 +176,12 @@ void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a)
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/**
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* cpuidle_state_is_coupled - check if a state is part of a coupled set
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* @dev: struct cpuidle_device for the current cpu
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* @drv: struct cpuidle_driver for the platform
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* @state: index of the target state in drv->states
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*
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* Returns true if the target state is coupled with cpus besides this one
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*/
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bool cpuidle_state_is_coupled(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int state)
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bool cpuidle_state_is_coupled(struct cpuidle_driver *drv, int state)
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{
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return drv->states[state].flags & CPUIDLE_FLAG_COUPLED;
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}
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@ -473,7 +471,7 @@ int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
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return entered_state;
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}
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entered_state = cpuidle_enter_state(dev, drv,
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dev->safe_state_index);
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drv->safe_state_index);
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local_irq_disable();
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}
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@ -521,7 +519,7 @@ int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
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}
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entered_state = cpuidle_enter_state(dev, drv,
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dev->safe_state_index);
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drv->safe_state_index);
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local_irq_disable();
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}
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@ -210,7 +210,7 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv,
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tick_broadcast_exit();
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}
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if (!cpuidle_state_is_coupled(dev, drv, entered_state))
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if (!cpuidle_state_is_coupled(drv, entered_state))
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local_irq_enable();
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diff = ktime_to_us(ktime_sub(time_end, time_start));
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@ -259,7 +259,7 @@ int cpuidle_select(struct cpuidle_driver *drv, struct cpuidle_device *dev)
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int cpuidle_enter(struct cpuidle_driver *drv, struct cpuidle_device *dev,
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int index)
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{
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if (cpuidle_state_is_coupled(dev, drv, index))
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if (cpuidle_state_is_coupled(drv, index))
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return cpuidle_enter_state_coupled(dev, drv, index);
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return cpuidle_enter_state(dev, drv, index);
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}
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@ -34,15 +34,14 @@ extern int cpuidle_add_sysfs(struct cpuidle_device *dev);
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extern void cpuidle_remove_sysfs(struct cpuidle_device *dev);
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#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
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bool cpuidle_state_is_coupled(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int state);
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bool cpuidle_state_is_coupled(struct cpuidle_driver *drv, int state);
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int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int next_state);
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int cpuidle_coupled_register_device(struct cpuidle_device *dev);
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void cpuidle_coupled_unregister_device(struct cpuidle_device *dev);
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#else
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static inline bool cpuidle_state_is_coupled(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int state)
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static inline
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bool cpuidle_state_is_coupled(struct cpuidle_driver *drv, int state)
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{
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return false;
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}
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@ -1,7 +1,7 @@
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/*
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* exynos_ppmu.c - EXYNOS PPMU (Platform Performance Monitoring Unit) support
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Copyright (c) 2014-2015 Samsung Electronics Co., Ltd.
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* Author : Chanwoo Choi <cw00.choi@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -82,6 +82,15 @@ struct __exynos_ppmu_events {
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PPMU_EVENT(mscl),
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PPMU_EVENT(fimd0x),
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PPMU_EVENT(fimd1x),
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/* Only for Exynos5433 SoCs */
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PPMU_EVENT(d0-cpu),
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PPMU_EVENT(d0-general),
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PPMU_EVENT(d0-rt),
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PPMU_EVENT(d1-cpu),
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PPMU_EVENT(d1-general),
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PPMU_EVENT(d1-rt),
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{ /* sentinel */ },
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};
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@ -96,6 +105,9 @@ static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev)
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return -EINVAL;
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}
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/*
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* The devfreq-event ops structure for PPMU v1.1
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*/
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static int exynos_ppmu_disable(struct devfreq_event_dev *edev)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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@ -200,10 +212,158 @@ static const struct devfreq_event_ops exynos_ppmu_ops = {
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.get_event = exynos_ppmu_get_event,
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};
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/*
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* The devfreq-event ops structure for PPMU v2.0
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*/
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static int exynos_ppmu_v2_disable(struct devfreq_event_dev *edev)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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u32 pmnc, clear;
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/* Disable all counters */
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clear = (PPMU_CCNT_MASK | PPMU_PMCNT0_MASK | PPMU_PMCNT1_MASK
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| PPMU_PMCNT2_MASK | PPMU_PMCNT3_MASK);
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__raw_writel(clear, info->ppmu.base + PPMU_V2_FLAG);
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__raw_writel(clear, info->ppmu.base + PPMU_V2_INTENC);
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__raw_writel(clear, info->ppmu.base + PPMU_V2_CNTENC);
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__raw_writel(clear, info->ppmu.base + PPMU_V2_CNT_RESET);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG0);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG1);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG2);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_RESULT);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CNT_AUTO);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV0_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV1_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV2_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV3_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_ID_V);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_ID_A);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_OTHERS_V);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_OTHERS_A);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_INTERRUPT_RESET);
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/* Disable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC);
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pmnc &= ~PPMU_PMNC_ENABLE_MASK;
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__raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC);
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return 0;
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}
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static int exynos_ppmu_v2_set_event(struct devfreq_event_dev *edev)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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int id = exynos_ppmu_find_ppmu_id(edev);
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u32 pmnc, cntens;
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/* Enable all counters */
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cntens = __raw_readl(info->ppmu.base + PPMU_V2_CNTENS);
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cntens |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id));
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__raw_writel(cntens, info->ppmu.base + PPMU_V2_CNTENS);
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/* Set the event of Read/Write data count */
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switch (id) {
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case PPMU_PMNCNT0:
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case PPMU_PMNCNT1:
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case PPMU_PMNCNT2:
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__raw_writel(PPMU_V2_RO_DATA_CNT | PPMU_V2_WO_DATA_CNT,
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info->ppmu.base + PPMU_V2_CH_EVx_TYPE(id));
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break;
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case PPMU_PMNCNT3:
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__raw_writel(PPMU_V2_EVT3_RW_DATA_CNT,
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info->ppmu.base + PPMU_V2_CH_EVx_TYPE(id));
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break;
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}
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/* Reset cycle counter/performance counter and enable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC);
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pmnc &= ~(PPMU_PMNC_ENABLE_MASK
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| PPMU_PMNC_COUNTER_RESET_MASK
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| PPMU_PMNC_CC_RESET_MASK
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| PPMU_PMNC_CC_DIVIDER_MASK
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| PPMU_V2_PMNC_START_MODE_MASK);
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_ENABLE_SHIFT);
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_COUNTER_RESET_SHIFT);
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_CC_RESET_SHIFT);
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pmnc |= (PPMU_V2_MODE_MANUAL << PPMU_V2_PMNC_START_MODE_SHIFT);
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__raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC);
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return 0;
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}
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static int exynos_ppmu_v2_get_event(struct devfreq_event_dev *edev,
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struct devfreq_event_data *edata)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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int id = exynos_ppmu_find_ppmu_id(edev);
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u32 pmnc, cntenc;
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u32 pmcnt_high, pmcnt_low;
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u64 load_count = 0;
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/* Disable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC);
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pmnc &= ~PPMU_PMNC_ENABLE_MASK;
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__raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC);
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/* Read cycle count and performance count */
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edata->total_count = __raw_readl(info->ppmu.base + PPMU_V2_CCNT);
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switch (id) {
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case PPMU_PMNCNT0:
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case PPMU_PMNCNT1:
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case PPMU_PMNCNT2:
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load_count = __raw_readl(info->ppmu.base + PPMU_V2_PMNCT(id));
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break;
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case PPMU_PMNCNT3:
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pmcnt_high = __raw_readl(info->ppmu.base + PPMU_V2_PMCNT3_HIGH);
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pmcnt_low = __raw_readl(info->ppmu.base + PPMU_V2_PMCNT3_LOW);
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load_count = (u64)((pmcnt_high & 0xff) << 32) + (u64)pmcnt_low;
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break;
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}
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edata->load_count = load_count;
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/* Disable all counters */
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cntenc = __raw_readl(info->ppmu.base + PPMU_V2_CNTENC);
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cntenc |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id));
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__raw_writel(cntenc, info->ppmu.base + PPMU_V2_CNTENC);
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dev_dbg(&edev->dev, "%25s (load: %ld / %ld)\n", edev->desc->name,
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edata->load_count, edata->total_count);
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return 0;
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}
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static const struct devfreq_event_ops exynos_ppmu_v2_ops = {
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.disable = exynos_ppmu_v2_disable,
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.set_event = exynos_ppmu_v2_set_event,
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.get_event = exynos_ppmu_v2_get_event,
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};
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static const struct of_device_id exynos_ppmu_id_match[] = {
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{
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.compatible = "samsung,exynos-ppmu",
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.data = (void *)&exynos_ppmu_ops,
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}, {
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.compatible = "samsung,exynos-ppmu-v2",
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.data = (void *)&exynos_ppmu_v2_ops,
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},
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{ /* sentinel */ },
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};
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static struct devfreq_event_ops *exynos_bus_get_ops(struct device_node *np)
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{
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const struct of_device_id *match;
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match = of_match_node(exynos_ppmu_id_match, np);
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return (struct devfreq_event_ops *)match->data;
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}
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static int of_get_devfreq_events(struct device_node *np,
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struct exynos_ppmu *info)
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{
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struct devfreq_event_desc *desc;
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struct devfreq_event_ops *event_ops;
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struct device *dev = info->dev;
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struct device_node *events_np, *node;
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int i, j, count;
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@ -214,6 +374,7 @@ static int of_get_devfreq_events(struct device_node *np,
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"failed to get child node of devfreq-event devices\n");
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return -EINVAL;
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}
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event_ops = exynos_bus_get_ops(np);
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count = of_get_child_count(events_np);
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desc = devm_kzalloc(dev, sizeof(*desc) * count, GFP_KERNEL);
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@ -238,7 +399,7 @@ static int of_get_devfreq_events(struct device_node *np,
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continue;
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}
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desc[j].ops = &exynos_ppmu_ops;
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desc[j].ops = event_ops;
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desc[j].driver_data = info;
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of_property_read_string(node, "event-name", &desc[j].name);
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@ -354,11 +515,6 @@ static int exynos_ppmu_remove(struct platform_device *pdev)
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return 0;
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}
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static struct of_device_id exynos_ppmu_id_match[] = {
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{ .compatible = "samsung,exynos-ppmu", },
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{ /* sentinel */ },
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};
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static struct platform_driver exynos_ppmu_driver = {
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.probe = exynos_ppmu_probe,
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.remove = exynos_ppmu_remove,
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|
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@ -26,6 +26,9 @@ enum ppmu_counter {
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PPMU_PMNCNT_MAX,
|
||||
};
|
||||
|
||||
/***
|
||||
* PPMUv1.1 Definitions
|
||||
*/
|
||||
enum ppmu_event_type {
|
||||
PPMU_RO_BUSY_CYCLE_CNT = 0x0,
|
||||
PPMU_WO_BUSY_CYCLE_CNT = 0x1,
|
||||
|
|
@ -90,4 +93,71 @@ enum ppmu_reg {
|
|||
#define PPMU_PMNCT(x) (PPMU_PMCNT0 + (0x10 * x))
|
||||
#define PPMU_BEVTxSEL(x) (PPMU_BEVT0SEL + (0x100 * x))
|
||||
|
||||
/***
|
||||
* PPMU_V2.0 definitions
|
||||
*/
|
||||
enum ppmu_v2_mode {
|
||||
PPMU_V2_MODE_MANUAL = 0,
|
||||
PPMU_V2_MODE_AUTO = 1,
|
||||
PPMU_V2_MODE_CIG = 2, /* CIG (Conditional Interrupt Generation) */
|
||||
};
|
||||
|
||||
enum ppmu_v2_event_type {
|
||||
PPMU_V2_RO_DATA_CNT = 0x4,
|
||||
PPMU_V2_WO_DATA_CNT = 0x5,
|
||||
|
||||
PPMU_V2_EVT3_RW_DATA_CNT = 0x22, /* Only for Event3 */
|
||||
};
|
||||
|
||||
enum ppmu_V2_reg {
|
||||
/* PPC control register */
|
||||
PPMU_V2_PMNC = 0x04,
|
||||
PPMU_V2_CNTENS = 0x08,
|
||||
PPMU_V2_CNTENC = 0x0c,
|
||||
PPMU_V2_INTENS = 0x10,
|
||||
PPMU_V2_INTENC = 0x14,
|
||||
PPMU_V2_FLAG = 0x18,
|
||||
|
||||
/* Cycle Counter and Performance Event Counter Register */
|
||||
PPMU_V2_CCNT = 0x48,
|
||||
PPMU_V2_PMCNT0 = 0x34,
|
||||
PPMU_V2_PMCNT1 = 0x38,
|
||||
PPMU_V2_PMCNT2 = 0x3c,
|
||||
PPMU_V2_PMCNT3_LOW = 0x40,
|
||||
PPMU_V2_PMCNT3_HIGH = 0x44,
|
||||
|
||||
/* Bus Event Generator */
|
||||
PPMU_V2_CIG_CFG0 = 0x1c,
|
||||
PPMU_V2_CIG_CFG1 = 0x20,
|
||||
PPMU_V2_CIG_CFG2 = 0x24,
|
||||
PPMU_V2_CIG_RESULT = 0x28,
|
||||
PPMU_V2_CNT_RESET = 0x2c,
|
||||
PPMU_V2_CNT_AUTO = 0x30,
|
||||
PPMU_V2_CH_EV0_TYPE = 0x200,
|
||||
PPMU_V2_CH_EV1_TYPE = 0x204,
|
||||
PPMU_V2_CH_EV2_TYPE = 0x208,
|
||||
PPMU_V2_CH_EV3_TYPE = 0x20c,
|
||||
PPMU_V2_SM_ID_V = 0x220,
|
||||
PPMU_V2_SM_ID_A = 0x224,
|
||||
PPMU_V2_SM_OTHERS_V = 0x228,
|
||||
PPMU_V2_SM_OTHERS_A = 0x22c,
|
||||
PPMU_V2_INTERRUPT_RESET = 0x260,
|
||||
};
|
||||
|
||||
/* PMNC register */
|
||||
#define PPMU_V2_PMNC_START_MODE_SHIFT 20
|
||||
#define PPMU_V2_PMNC_START_MODE_MASK (0x3 << PPMU_V2_PMNC_START_MODE_SHIFT)
|
||||
|
||||
#define PPMU_PMNC_CC_RESET_SHIFT 2
|
||||
#define PPMU_PMNC_COUNTER_RESET_SHIFT 1
|
||||
#define PPMU_PMNC_ENABLE_SHIFT 0
|
||||
#define PPMU_PMNC_START_MODE_MASK BIT(16)
|
||||
#define PPMU_PMNC_CC_DIVIDER_MASK BIT(3)
|
||||
#define PPMU_PMNC_CC_RESET_MASK BIT(2)
|
||||
#define PPMU_PMNC_COUNTER_RESET_MASK BIT(1)
|
||||
#define PPMU_PMNC_ENABLE_MASK BIT(0)
|
||||
|
||||
#define PPMU_V2_PMNCT(x) (PPMU_V2_PMCNT0 + (0x4 * x))
|
||||
#define PPMU_V2_CH_EVx_TYPE(x) (PPMU_V2_CH_EV0_TYPE + (0x4 * x))
|
||||
|
||||
#endif /* __EXYNOS_PPMU_H__ */
|
||||
|
|
|
|||
|
|
@ -591,6 +591,67 @@ static struct cpuidle_state bdw_cstates[] = {
|
|||
.enter = NULL }
|
||||
};
|
||||
|
||||
static struct cpuidle_state skl_cstates[] = {
|
||||
{
|
||||
.name = "C1-SKL",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 2,
|
||||
.target_residency = 2,
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C1E-SKL",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C3-SKL",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 70,
|
||||
.target_residency = 100,
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C6-SKL",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 75,
|
||||
.target_residency = 200,
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C7s-SKL",
|
||||
.desc = "MWAIT 0x33",
|
||||
.flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 124,
|
||||
.target_residency = 800,
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C8-SKL",
|
||||
.desc = "MWAIT 0x40",
|
||||
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 174,
|
||||
.target_residency = 800,
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.name = "C10-SKL",
|
||||
.desc = "MWAIT 0x60",
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 890,
|
||||
.target_residency = 5000,
|
||||
.enter = &intel_idle,
|
||||
.enter_freeze = intel_idle_freeze, },
|
||||
{
|
||||
.enter = NULL }
|
||||
};
|
||||
|
||||
static struct cpuidle_state atom_cstates[] = {
|
||||
{
|
||||
.name = "C1E-ATM",
|
||||
|
|
@ -810,6 +871,12 @@ static const struct idle_cpu idle_cpu_bdw = {
|
|||
.disable_promotion_to_c1e = true,
|
||||
};
|
||||
|
||||
static const struct idle_cpu idle_cpu_skl = {
|
||||
.state_table = skl_cstates,
|
||||
.disable_promotion_to_c1e = true,
|
||||
};
|
||||
|
||||
|
||||
static const struct idle_cpu idle_cpu_avn = {
|
||||
.state_table = avn_cstates,
|
||||
.disable_promotion_to_c1e = true,
|
||||
|
|
@ -844,6 +911,8 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
|
|||
ICPU(0x47, idle_cpu_bdw),
|
||||
ICPU(0x4f, idle_cpu_bdw),
|
||||
ICPU(0x56, idle_cpu_bdw),
|
||||
ICPU(0x4e, idle_cpu_skl),
|
||||
ICPU(0x5e, idle_cpu_skl),
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
|
||||
|
|
@ -965,7 +1034,8 @@ static int __init intel_idle_cpuidle_driver_init(void)
|
|||
for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
|
||||
int num_substates, mwait_hint, mwait_cstate;
|
||||
|
||||
if (cpuidle_state_table[cstate].enter == NULL)
|
||||
if ((cpuidle_state_table[cstate].enter == NULL) &&
|
||||
(cpuidle_state_table[cstate].enter_freeze == NULL))
|
||||
break;
|
||||
|
||||
if (cstate + 1 > max_cstate) {
|
||||
|
|
|
|||
|
|
@ -84,7 +84,6 @@ struct cpuidle_device {
|
|||
struct list_head device_list;
|
||||
|
||||
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
|
||||
int safe_state_index;
|
||||
cpumask_t coupled_cpus;
|
||||
struct cpuidle_coupled *coupled;
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue