spi: add SPI controller driver for UniPhier SoC
Add SPI controller driver implemented in Socionext UniPhier SoCs. UniPhier SoCs have two types SPI controllers; SCSSI supports a single channel, and MCSSI supports multiple channels. This driver supports SCSSI only. This controller has 32bit TX/RX FIFO with depth of eight entry, and supports the SPI master mode only. This commit is implemented in PIO transfer mode, not DMA transfer. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Keiji Hayashibara
Mark Brown
parent
4dcd5c2781
commit
5ba155a4d4
3 changed files with 539 additions and 0 deletions
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@ -688,6 +688,19 @@ config SPI_TXX9
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help
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SPI driver for Toshiba TXx9 MIPS SoCs
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config SPI_UNIPHIER
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tristate "Socionext UniPhier SPI Controller"
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depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
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help
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This enables a driver for the Socionext UniPhier SoC SCSSI SPI controller.
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UniPhier SoCs have SCSSI and MCSSI SPI controllers.
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Every UniPhier SoC has SCSSI which supports single channel.
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Older UniPhier Pro4/Pro5 also has MCSSI which support multiple channels.
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This driver supports SCSSI only.
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If your SoC supports SCSSI, say Y here.
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config SPI_XCOMM
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tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
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depends on I2C
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@ -101,6 +101,7 @@ spi-thunderx-objs := spi-cavium.o spi-cavium-thunderx.o
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obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
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obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
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obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
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obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
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obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
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obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
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obj-$(CONFIG_SPI_XLP) += spi-xlp.o
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525
drivers/spi/spi-uniphier.c
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525
drivers/spi/spi-uniphier.c
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@ -0,0 +1,525 @@
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// SPDX-License-Identifier: GPL-2.0
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// spi-uniphier.c - Socionext UniPhier SPI controller driver
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// Copyright 2012 Panasonic Corporation
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// Copyright 2016-2018 Socionext Inc.
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#include <linux/kernel.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <asm/unaligned.h>
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#define SSI_TIMEOUT_MS 2000
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#define SSI_MAX_CLK_DIVIDER 254
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#define SSI_MIN_CLK_DIVIDER 4
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struct uniphier_spi_priv {
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void __iomem *base;
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struct clk *clk;
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struct spi_master *master;
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struct completion xfer_done;
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int error;
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unsigned int tx_bytes;
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unsigned int rx_bytes;
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const u8 *tx_buf;
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u8 *rx_buf;
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bool is_save_param;
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u8 bits_per_word;
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u16 mode;
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u32 speed_hz;
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};
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#define SSI_CTL 0x00
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#define SSI_CTL_EN BIT(0)
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#define SSI_CKS 0x04
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#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
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#define SSI_CKS_CKPHS BIT(14)
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#define SSI_CKS_CKINIT BIT(13)
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#define SSI_CKS_CKDLY BIT(12)
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#define SSI_TXWDS 0x08
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#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
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#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
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#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
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#define SSI_RXWDS 0x0c
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#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
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#define SSI_FPS 0x10
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#define SSI_FPS_FSPOL BIT(15)
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#define SSI_FPS_FSTRT BIT(14)
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#define SSI_SR 0x14
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#define SSI_SR_RNE BIT(0)
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#define SSI_IE 0x18
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#define SSI_IE_RCIE BIT(3)
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#define SSI_IE_RORIE BIT(0)
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#define SSI_IS 0x1c
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#define SSI_IS_RXRS BIT(9)
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#define SSI_IS_RCID BIT(3)
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#define SSI_IS_RORID BIT(0)
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#define SSI_IC 0x1c
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#define SSI_IC_TCIC BIT(4)
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#define SSI_IC_RCIC BIT(3)
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#define SSI_IC_RORIC BIT(0)
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#define SSI_FC 0x20
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#define SSI_FC_TXFFL BIT(12)
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#define SSI_FC_TXFTH_MASK GENMASK(11, 8)
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#define SSI_FC_RXFFL BIT(4)
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#define SSI_FC_RXFTH_MASK GENMASK(3, 0)
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#define SSI_TXDR 0x24
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#define SSI_RXDR 0x24
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#define SSI_FIFO_DEPTH 8U
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static inline unsigned int bytes_per_word(unsigned int bits)
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{
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return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
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}
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static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val;
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val = readl(priv->base + SSI_IE);
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val |= mask;
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writel(val, priv->base + SSI_IE);
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}
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static inline void uniphier_spi_irq_disable(struct spi_device *spi, u32 mask)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val;
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val = readl(priv->base + SSI_IE);
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val &= ~mask;
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writel(val, priv->base + SSI_IE);
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}
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static void uniphier_spi_set_mode(struct spi_device *spi)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val1, val2;
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/*
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* clock setting
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* CKPHS capture timing. 0:rising edge, 1:falling edge
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* CKINIT clock initial level. 0:low, 1:high
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* CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
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* (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
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*
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* frame setting
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* FSPOL frame signal porarity. 0: low, 1: high
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* FSTRT start frame timing
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* 0: rising edge of clock, 1: falling edge of clock
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*/
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switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
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case SPI_MODE_0:
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/* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
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val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
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val2 = 0;
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break;
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case SPI_MODE_1:
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/* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
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val1 = 0;
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val2 = SSI_FPS_FSTRT;
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break;
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case SPI_MODE_2:
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/* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
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val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
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val2 = SSI_FPS_FSTRT;
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break;
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case SPI_MODE_3:
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/* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
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val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
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val2 = 0;
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break;
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}
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if (!(spi->mode & SPI_CS_HIGH))
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val2 |= SSI_FPS_FSPOL;
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writel(val1, priv->base + SSI_CKS);
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writel(val2, priv->base + SSI_FPS);
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val1 = 0;
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if (spi->mode & SPI_LSB_FIRST)
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val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
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writel(val1, priv->base + SSI_TXWDS);
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writel(val1, priv->base + SSI_RXWDS);
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}
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static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val;
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val = readl(priv->base + SSI_TXWDS);
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val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
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val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
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val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
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writel(val, priv->base + SSI_TXWDS);
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val = readl(priv->base + SSI_RXWDS);
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val &= ~SSI_RXWDS_DTLEN_MASK;
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val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
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writel(val, priv->base + SSI_RXWDS);
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}
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static void uniphier_spi_set_baudrate(struct spi_device *spi,
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unsigned int speed)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val, ckdiv;
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/*
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* the supported rates are even numbers from 4 to 254. (4,6,8...254)
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* round up as we look for equal or less speed
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*/
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ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
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ckdiv = round_up(ckdiv, 2);
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val = readl(priv->base + SSI_CKS);
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val &= ~SSI_CKS_CKRAT_MASK;
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val |= ckdiv & SSI_CKS_CKRAT_MASK;
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writel(val, priv->base + SSI_CKS);
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}
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static void uniphier_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val;
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priv->error = 0;
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priv->tx_buf = t->tx_buf;
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priv->rx_buf = t->rx_buf;
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priv->tx_bytes = priv->rx_bytes = t->len;
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if (!priv->is_save_param || priv->mode != spi->mode) {
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uniphier_spi_set_mode(spi);
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priv->mode = spi->mode;
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}
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if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
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uniphier_spi_set_transfer_size(spi, t->bits_per_word);
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priv->bits_per_word = t->bits_per_word;
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}
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if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
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uniphier_spi_set_baudrate(spi, t->speed_hz);
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priv->speed_hz = t->speed_hz;
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}
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if (!priv->is_save_param)
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priv->is_save_param = true;
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/* reset FIFOs */
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val = SSI_FC_TXFFL | SSI_FC_RXFFL;
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writel(val, priv->base + SSI_FC);
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}
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static void uniphier_spi_send(struct uniphier_spi_priv *priv)
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{
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int wsize;
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u32 val = 0;
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wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
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priv->tx_bytes -= wsize;
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if (priv->tx_buf) {
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switch (wsize) {
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case 1:
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val = *priv->tx_buf;
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break;
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case 2:
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val = get_unaligned_le16(priv->tx_buf);
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break;
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case 4:
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val = get_unaligned_le32(priv->tx_buf);
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break;
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}
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priv->tx_buf += wsize;
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}
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writel(val, priv->base + SSI_TXDR);
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}
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static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
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{
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int rsize;
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u32 val;
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rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
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priv->rx_bytes -= rsize;
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val = readl(priv->base + SSI_RXDR);
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if (priv->rx_buf) {
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switch (rsize) {
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case 1:
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*priv->rx_buf = val;
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break;
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case 2:
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put_unaligned_le16(val, priv->rx_buf);
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break;
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case 4:
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put_unaligned_le32(val, priv->rx_buf);
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break;
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}
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priv->rx_buf += rsize;
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}
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}
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static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
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{
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unsigned int tx_count;
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u32 val;
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tx_count = DIV_ROUND_UP(priv->tx_bytes,
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bytes_per_word(priv->bits_per_word));
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tx_count = min(tx_count, SSI_FIFO_DEPTH);
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/* set fifo threshold */
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val = readl(priv->base + SSI_FC);
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val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
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val |= FIELD_PREP(SSI_FC_TXFTH_MASK, tx_count);
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val |= FIELD_PREP(SSI_FC_RXFTH_MASK, tx_count);
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writel(val, priv->base + SSI_FC);
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while (tx_count--)
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uniphier_spi_send(priv);
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}
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static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val;
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val = readl(priv->base + SSI_FPS);
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if (enable)
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val |= SSI_FPS_FSPOL;
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else
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val &= ~SSI_FPS_FSPOL;
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writel(val, priv->base + SSI_FPS);
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}
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static int uniphier_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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int status;
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uniphier_spi_setup_transfer(spi, t);
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reinit_completion(&priv->xfer_done);
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uniphier_spi_fill_tx_fifo(priv);
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uniphier_spi_irq_enable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
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status = wait_for_completion_timeout(&priv->xfer_done,
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msecs_to_jiffies(SSI_TIMEOUT_MS));
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uniphier_spi_irq_disable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
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if (status < 0)
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return status;
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return priv->error;
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}
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static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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writel(SSI_CTL_EN, priv->base + SSI_CTL);
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return 0;
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}
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static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
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writel(0, priv->base + SSI_CTL);
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return 0;
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}
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static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
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{
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struct uniphier_spi_priv *priv = dev_id;
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u32 val, stat;
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stat = readl(priv->base + SSI_IS);
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val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
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writel(val, priv->base + SSI_IC);
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/* rx fifo overrun */
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if (stat & SSI_IS_RORID) {
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priv->error = -EIO;
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goto done;
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}
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/* rx complete */
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if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
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while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
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(priv->rx_bytes - priv->tx_bytes) > 0)
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uniphier_spi_recv(priv);
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if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
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(priv->rx_bytes != priv->tx_bytes)) {
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priv->error = -EIO;
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goto done;
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} else if (priv->rx_bytes == 0)
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goto done;
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/* next tx transfer */
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uniphier_spi_fill_tx_fifo(priv);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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done:
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complete(&priv->xfer_done);
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return IRQ_HANDLED;
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}
|
||||
|
||||
static int uniphier_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct uniphier_spi_priv *priv;
|
||||
struct spi_master *master;
|
||||
struct resource *res;
|
||||
unsigned long clk_rate;
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*priv));
|
||||
if (!master)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
priv = spi_master_get_devdata(master);
|
||||
priv->master = master;
|
||||
priv->is_save_param = false;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(priv->base)) {
|
||||
ret = PTR_ERR(priv->base);
|
||||
goto out_master_put;
|
||||
}
|
||||
|
||||
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(priv->clk)) {
|
||||
dev_err(&pdev->dev, "failed to get clock\n");
|
||||
ret = PTR_ERR(priv->clk);
|
||||
goto out_master_put;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(priv->clk);
|
||||
if (ret)
|
||||
goto out_master_put;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get IRQ\n");
|
||||
ret = irq;
|
||||
goto out_disable_clk;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
|
||||
0, "uniphier-spi", priv);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ\n");
|
||||
goto out_disable_clk;
|
||||
}
|
||||
|
||||
init_completion(&priv->xfer_done);
|
||||
|
||||
clk_rate = clk_get_rate(priv->clk);
|
||||
|
||||
master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
|
||||
master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->bus_num = pdev->id;
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
||||
|
||||
master->set_cs = uniphier_spi_set_cs;
|
||||
master->transfer_one = uniphier_spi_transfer_one;
|
||||
master->prepare_transfer_hardware
|
||||
= uniphier_spi_prepare_transfer_hardware;
|
||||
master->unprepare_transfer_hardware
|
||||
= uniphier_spi_unprepare_transfer_hardware;
|
||||
master->num_chipselect = 1;
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
if (ret)
|
||||
goto out_disable_clk;
|
||||
|
||||
return 0;
|
||||
|
||||
out_disable_clk:
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
out_master_put:
|
||||
spi_master_put(master);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uniphier_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uniphier_spi_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id uniphier_spi_match[] = {
|
||||
{ .compatible = "socionext,uniphier-scssi" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, uniphier_spi_match);
|
||||
|
||||
static struct platform_driver uniphier_spi_driver = {
|
||||
.probe = uniphier_spi_probe,
|
||||
.remove = uniphier_spi_remove,
|
||||
.driver = {
|
||||
.name = "uniphier-spi",
|
||||
.of_match_table = uniphier_spi_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(uniphier_spi_driver);
|
||||
|
||||
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
|
||||
MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
|
||||
MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue