V4L/DVB (7671): pxa-camera: fix DMA sg-list coalescing for more than 2 buffers
Currently the pxa-camera driver has a bug, visible when the user requests more than 2 video buffers. When the third buffer is queued, it is not appended to the DMA-descriptor list of the second buffer, but is again appended to the first buffer. Fix it. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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parent
e7c5068819
commit
5aa2110f3f
1 changed files with 15 additions and 20 deletions
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@ -102,11 +102,6 @@ struct pxa_buffer {
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enum pxa_camera_active_dma active_dma;
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};
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struct pxa_framebuffer_queue {
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dma_addr_t sg_last_dma;
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struct pxa_dma_desc *sg_last_cpu;
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};
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struct pxa_camera_dev {
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struct device *dev;
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/* PXA27x is only supposed to handle one camera on its Quick Capture
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@ -131,6 +126,7 @@ struct pxa_camera_dev {
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spinlock_t lock;
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struct pxa_buffer *active;
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struct pxa_dma_desc *sg_tail[3];
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};
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static const char *pxa_cam_driver_description = "PXA_Camera";
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@ -144,11 +140,14 @@ static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
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unsigned int *size)
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{
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struct soc_camera_device *icd = vq->priv_data;
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struct soc_camera_host *ici =
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to_soc_camera_host(icd->dev.parent);
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struct pxa_camera_dev *pcdev = ici->priv;
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dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
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/* planar capture requires Y, U and V buffers to be page aligned */
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if (icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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if (pcdev->channels == 3) {
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*size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
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*size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
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*size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
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@ -296,7 +295,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
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if (ret)
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goto fail;
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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if (pcdev->channels == 3) {
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/* FIXME the calculations should be more precise */
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sglen_y = dma->sglen / 2;
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sglen_u = sglen_v = dma->sglen / 4 + 1;
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@ -318,7 +317,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
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goto fail;
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}
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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if (pcdev->channels == 3) {
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/* init DMA for U channel */
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ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
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sglen_y, 0x30, size_u);
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@ -343,7 +342,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
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buf->inwork = 0;
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buf->active_dma = DMA_Y;
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P)
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if (pcdev->channels == 3)
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buf->active_dma |= DMA_U | DMA_V;
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return 0;
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@ -371,6 +370,7 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
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struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
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struct pxa_buffer *active;
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unsigned long flags;
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int i;
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dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
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vb, vb->baddr, vb->bsize);
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@ -383,15 +383,11 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
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if (!active) {
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CIFR |= CIFR_RESET_F;
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DDADR(pcdev->dma_chans[0]) = buf->dmas[0].sg_dma;
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DCSR(pcdev->dma_chans[0]) = DCSR_RUN;
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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DDADR(pcdev->dma_chans[1]) = buf->dmas[1].sg_dma;
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DCSR(pcdev->dma_chans[1]) = DCSR_RUN;
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DDADR(pcdev->dma_chans[2]) = buf->dmas[2].sg_dma;
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DCSR(pcdev->dma_chans[2]) = DCSR_RUN;
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for (i = 0; i < pcdev->channels; i++) {
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DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
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DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
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pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
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}
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pcdev->active = buf;
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@ -400,7 +396,6 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
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struct pxa_cam_dma *buf_dma;
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struct pxa_cam_dma *act_dma;
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int nents;
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int i;
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for (i = 0; i < pcdev->channels; i++) {
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buf_dma = &buf->dmas[i];
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@ -412,8 +407,8 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
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/* Add the descriptors we just initialized to
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the currently running chain */
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act_dma->sg_cpu[act_dma->sglen - 1].ddadr =
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buf_dma->sg_dma;
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pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
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pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
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/* Setup a dummy descriptor with the DMA engines current
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* state
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