powerpc/fsl_pci: Add MPC83xx PCI-E controller RC mode support
This patch adds support for PCI-Express controllers as found on the newer MPC83xx chips. The work is loosely based on the Tony Li's patch[1], but unlike the original patch, this patch implements sliding window for the Type 1 transactions using outbound window translations, so we don't have to ioremap the whole PCI-E configuration space. [1] http://ozlabs.org/pipermail/linuxppc-dev/2008-January/049028.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Anton Vorontsov
Kumar Gala
parent
18e352e4a7
commit
598804cd04
2 changed files with 228 additions and 24 deletions
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@ -1,12 +1,16 @@
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/*
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* MPC83xx/85xx/86xx PCI/PCIE support routing.
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*
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* Copyright 2007,2008 Freescale Semiconductor, Inc
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* Copyright 2007-2009 Freescale Semiconductor, Inc.
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* Copyright 2008-2009 MontaVista Software, Inc.
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*
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Rewrite the routing for Frescale PCI and PCI Express
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* Roy Zang <tie-fei.zang@freescale.com>
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* MPC83xx PCI-Express support:
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* Tony Li <tony.li@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -27,6 +31,29 @@
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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static int fsl_pcie_bus_fixup;
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static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
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{
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/* if we aren't a PCIe don't bother */
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if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
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return;
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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fsl_pcie_bus_fixup = 1;
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return;
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}
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static int __init fsl_pcie_check_link(struct pci_controller *hose)
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{
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u32 val;
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early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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return 0;
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}
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#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
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static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
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unsigned int index, const struct resource *res,
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@ -159,28 +186,6 @@ static void __init setup_pci_pcsrbar(struct pci_controller *hose)
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#endif
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}
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static int fsl_pcie_bus_fixup;
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static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
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{
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/* if we aren't a PCIe don't bother */
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if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
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return ;
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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fsl_pcie_bus_fixup = 1;
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return ;
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}
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static int __init fsl_pcie_check_link(struct pci_controller *hose)
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{
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u32 val;
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early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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return 0;
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}
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void fsl_pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
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@ -294,8 +299,184 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
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#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
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#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
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struct mpc83xx_pcie_priv {
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void __iomem *cfg_type0;
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void __iomem *cfg_type1;
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u32 dev_base;
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};
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/*
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* With the convention of u-boot, the PCIE outbound window 0 serves
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* as configuration transactions outbound.
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*/
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#define PEX_OUTWIN0_BAR 0xCA4
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#define PEX_OUTWIN0_TAL 0xCA8
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#define PEX_OUTWIN0_TAH 0xCAC
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static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
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{
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struct pci_controller *hose = bus->sysdata;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Workaround for the HW bug: for Type 0 configure transactions the
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* PCI-E controller does not check the device number bits and just
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* assumes that the device number bits are 0.
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*/
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if (bus->number == hose->first_busno ||
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bus->primary == hose->first_busno) {
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if (devfn & 0xf8)
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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if (ppc_md.pci_exclude_device) {
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
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unsigned int devfn, int offset)
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{
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struct pci_controller *hose = bus->sysdata;
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struct mpc83xx_pcie_priv *pcie = hose->dn->data;
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u8 bus_no = bus->number - hose->first_busno;
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u32 dev_base = bus_no << 24 | devfn << 16;
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int ret;
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ret = mpc83xx_pcie_exclude_device(bus, devfn);
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if (ret)
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return NULL;
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offset &= 0xfff;
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/* Type 0 */
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if (bus->number == hose->first_busno)
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return pcie->cfg_type0 + offset;
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if (pcie->dev_base == dev_base)
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goto mapped;
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out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
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pcie->dev_base = dev_base;
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mapped:
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return pcie->cfg_type1 + offset;
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}
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static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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void __iomem *cfg_addr;
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cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
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if (!cfg_addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (len) {
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case 1:
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*val = in_8(cfg_addr);
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break;
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case 2:
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*val = in_le16(cfg_addr);
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break;
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default:
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*val = in_le32(cfg_addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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void __iomem *cfg_addr;
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cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
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if (!cfg_addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (len) {
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case 1:
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out_8(cfg_addr, val);
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break;
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case 2:
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out_le16(cfg_addr, val);
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break;
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default:
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out_le32(cfg_addr, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops mpc83xx_pcie_ops = {
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.read = mpc83xx_pcie_read_config,
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.write = mpc83xx_pcie_write_config,
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};
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static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
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struct resource *reg)
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{
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struct mpc83xx_pcie_priv *pcie;
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u32 cfg_bar;
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int ret = -ENOMEM;
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pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return ret;
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pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
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if (!pcie->cfg_type0)
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goto err0;
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cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
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if (!cfg_bar) {
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/* PCI-E isn't configured. */
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ret = -ENODEV;
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goto err1;
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}
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pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
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if (!pcie->cfg_type1)
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goto err1;
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WARN_ON(hose->dn->data);
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hose->dn->data = pcie;
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hose->ops = &mpc83xx_pcie_ops;
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out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
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out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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return 0;
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err1:
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iounmap(pcie->cfg_type0);
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err0:
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kfree(pcie);
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return ret;
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}
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int __init mpc83xx_add_bridge(struct device_node *dev)
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{
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int ret;
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int len;
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struct pci_controller *hose;
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struct resource rsrc_reg;
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@ -303,6 +484,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
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const int *bus_range;
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int primary;
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if (!of_device_is_available(dev)) {
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pr_warning("%s: disabled by the firmware.\n",
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dev->full_name);
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return -ENODEV;
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}
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pr_debug("Adding PCI host bridge %s\n", dev->full_name);
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/* Fetch host bridge registers address */
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@ -350,7 +536,14 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 4, 0);
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if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
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ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
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if (ret)
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goto err0;
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} else {
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setup_indirect_pci(hose, rsrc_cfg.start,
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rsrc_cfg.start + 4, 0);
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}
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printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
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"Firmware bus number: %d->%d\n",
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@ -365,5 +558,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
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pci_process_bridge_OF_ranges(hose, dev, primary);
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return 0;
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err0:
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pcibios_free_controller(hose);
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return ret;
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}
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#endif /* CONFIG_PPC_83xx */
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@ -2217,6 +2217,14 @@
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#define PCI_DEVICE_ID_TDI_EHCI 0x0101
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#define PCI_VENDOR_ID_FREESCALE 0x1957
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#define PCI_DEVICE_ID_MPC8315E 0x00b4
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#define PCI_DEVICE_ID_MPC8315 0x00b5
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#define PCI_DEVICE_ID_MPC8314E 0x00b6
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#define PCI_DEVICE_ID_MPC8314 0x00b7
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#define PCI_DEVICE_ID_MPC8378E 0x00c4
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#define PCI_DEVICE_ID_MPC8378 0x00c5
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#define PCI_DEVICE_ID_MPC8377E 0x00c6
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#define PCI_DEVICE_ID_MPC8377 0x00c7
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#define PCI_DEVICE_ID_MPC8548E 0x0012
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#define PCI_DEVICE_ID_MPC8548 0x0013
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#define PCI_DEVICE_ID_MPC8543E 0x0014
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