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[POWERPC] Fix rmb to order cacheable vs. noncacheable

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lwsync is explicitly defined not to have any effect on the ordering of
accesses to device memory, so it cannot be used for rmb(). sync appears
to be the only barrier which fits the bill.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Nick Piggin 2008-05-22 00:10:56 +10:00 committed by Paul Mackerras
parent a9653cf540
commit 598056d5af
1 changed files with 1 additions and 1 deletions
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2
include/asm-powerpc/system.h
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@ -34,7 +34,7 @@
* SMP since it is only used to order updates to system memory. * SMP since it is only used to order updates to system memory.
*/ */
#define mb() __asm__ __volatile__ ("sync" : : : "memory") #define mb() __asm__ __volatile__ ("sync" : : : "memory")
#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory") #define rmb() __asm__ __volatile__ ("sync" : : : "memory")
#define wmb() __asm__ __volatile__ ("sync" : : : "memory") #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
#define read_barrier_depends() do { } while(0) #define read_barrier_depends() do { } while(0)