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CRIS v32: Add hardware dependent include files and defconfigs for ETRAX FS and ARTPEC-3 chips.

Browse source 
The header files describe the hardware registers available in both
these chips, note that most of this documentation is automatically
generated from the hardware implementation.
This commit is contained in:
Jesper Nilsson 2007-11-29 17:21:59 +01:00 • committed by Jesper Nilsson
parent 035e111f9a
commit 58d0831928
65 changed files with 19631 additions and 0 deletions
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583
arch/cris/artpec_3_defconfig Normal file
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#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.24-rc3
# Mon Dec 3 11:18:54 2007
#
CONFIG_MMU=y
CONFIG_ZONE_DMA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_IOMAP=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NO_IOPORT=y
CONFIG_NO_IOMEM=y
CONFIG_FORCE_MAX_ZONEORDER=6
CONFIG_CRIS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
#
# General setup
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
# CONFIG_ETRAX_WATCHDOG is not set
CONFIG_ETRAX_FAST_TIMER=y
# CONFIG_ETRAX_KMALLOCED_MODULES is not set
# CONFIG_OOM_REBOOT is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
#
# Hardware setup
#
# CONFIG_ETRAX100LX is not set
# CONFIG_ETRAX100LX_V2 is not set
# CONFIG_SVINTO_SIM is not set
# CONFIG_ETRAXFS is not set
CONFIG_CRIS_MACH_ARTPEC3=y
# CONFIG_ETRAX_VCS_SIM is not set
# CONFIG_ETRAX_ARCH_V10 is not set
CONFIG_ETRAX_ARCH_V32=y
CONFIG_ETRAX_DRAM_SIZE=32
CONFIG_ETRAX_VMEM_SIZE=8
CONFIG_ETRAX_FLASH_BUSWIDTH=2
CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
CONFIG_ETRAX_FLASH1_SIZE=4
CONFIG_ETRAX_DEBUG_PORT0=y
# CONFIG_ETRAX_DEBUG_PORT1 is not set
# CONFIG_ETRAX_DEBUG_PORT2 is not set
# CONFIG_ETRAX_DEBUG_PORT3 is not set
# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
CONFIG_ETRAX_SERIAL_PORTS=5
CONFIG_ETRAX_DEF_GIO_PA_OE=1c
CONFIG_ETRAX_DEF_GIO_PA_OUT=00
CONFIG_ETRAX_DEF_GIO_PB_OE=00000
CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
CONFIG_ETRAX_DEF_GIO_PC_OE=00000
CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
#
# Artpec-3 options
#
CONFIG_ETRAX_L2CACHE=y
CONFIG_ETRAX_DDR=y
CONFIG_ETRAX_DDR2_MRS=0
CONFIG_ETRAX_DDR2_TIMING=0
CONFIG_ETRAX_DDR2_CONFIG=0
CONFIG_ETRAX_PIO_CE0_CFG=0
CONFIG_ETRAX_PIO_CE1_CFG=0
CONFIG_ETRAX_PIO_CE2_CFG=0
# CONFIG_CPU_FREQ is not set
# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
CONFIG_ETRAX_NBR_LED_GRP_ONE=y
# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
CONFIG_ETRAX_LED_G_NET0="PA3"
CONFIG_ETRAX_LED_R_NET0="PA4"
CONFIG_ETRAX_V32_LED2G="PA5"
CONFIG_ETRAX_V32_LED2R="PA6"
CONFIG_ETRAX_V32_LED3G="PA7"
CONFIG_ETRAX_V32_LED3R="PA7"
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IP_VS is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
#
# Core Netfilter Configuration
#
# CONFIG_NETFILTER_NETLINK is not set
# CONFIG_NF_CONNTRACK_ENABLED is not set
# CONFIG_NF_CONNTRACK is not set
# CONFIG_NETFILTER_XTABLES is not set
#
# IP: Netfilter Configuration
#
# CONFIG_IP_NF_QUEUE is not set
# CONFIG_IP_NF_IPTABLES is not set
# CONFIG_IP_NF_ARPTABLES is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Drivers for built-in interfaces
#
CONFIG_ETRAX_ETHERNET=y
# CONFIG_ETRAX_IDE is not set
CONFIG_ETRAX_AXISFLASHMAP=y
CONFIG_ETRAX_PTABLE_SECTOR=65536
# CONFIG_ETRAX_I2C is not set
# CONFIG_ETRAX_GPIO is not set
# CONFIG_ETRAX_NO_PHY is not set
# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
# CONFIG_ETRAX_ETHERNET_GBIT is not set
# CONFIG_ETRAXFS_SERIAL is not set
# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
# CONFIG_ETRAX_NANDFLASH is not set
# CONFIG_ETRAX_CARDBUS is not set
# CONFIG_ETRAX_IOP_FW_LOAD is not set
# CONFIG_ETRAX_STREAMCOPROC is not set
# CONFIG_ETRAX_SPI_MMC is not set
# CONFIG_ETRAX_SPI_MMC_BOARD is not set
# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_RTC_CLASS is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_HW_RANDOM=y
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PROFILING is not set
# CONFIG_SYSTEM_PROFILER is not set
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SAMPLES is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_DMA=y

586
arch/cris/etraxfs_defconfig Normal file
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#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.24-rc3
# Fri Nov 30 14:24:26 2007
#
CONFIG_MMU=y
CONFIG_ZONE_DMA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_IOMAP=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NO_IOPORT=y
CONFIG_NO_IOMEM=y
CONFIG_FORCE_MAX_ZONEORDER=6
CONFIG_CRIS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
#
# General setup
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
# CONFIG_ETRAX_WATCHDOG is not set
CONFIG_ETRAX_FAST_TIMER=y
# CONFIG_ETRAX_KMALLOCED_MODULES is not set
# CONFIG_OOM_REBOOT is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
#
# Hardware setup
#
# CONFIG_ETRAX100LX is not set
# CONFIG_ETRAX100LX_V2 is not set
# CONFIG_SVINTO_SIM is not set
CONFIG_ETRAXFS=y
# CONFIG_CRIS_MACH_ARTPEC3 is not set
# CONFIG_ETRAX_VCS_SIM is not set
# CONFIG_ETRAX_ARCH_V10 is not set
CONFIG_ETRAX_ARCH_V32=y
CONFIG_ETRAX_DRAM_SIZE=32
CONFIG_ETRAX_FLASH_BUSWIDTH=2
CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
CONFIG_ETRAX_FLASH1_SIZE=4
CONFIG_ETRAX_DEBUG_PORT0=y
# CONFIG_ETRAX_DEBUG_PORT1 is not set
# CONFIG_ETRAX_DEBUG_PORT2 is not set
# CONFIG_ETRAX_DEBUG_PORT3 is not set
# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
#
# ETRAX FS options
#
CONFIG_ETRAX_SERIAL_PORTS=4
CONFIG_ETRAX_MEM_GRP1_CONFIG=4044a
CONFIG_ETRAX_MEM_GRP2_CONFIG=0
CONFIG_ETRAX_MEM_GRP3_CONFIG=0
CONFIG_ETRAX_MEM_GRP4_CONFIG=0
CONFIG_ETRAX_SDRAM_GRP0_CONFIG=336
CONFIG_ETRAX_SDRAM_GRP1_CONFIG=0
CONFIG_ETRAX_SDRAM_TIMING=104a
CONFIG_ETRAX_SDRAM_COMMAND=0
CONFIG_ETRAX_DEF_GIO_PA_OE=1c
CONFIG_ETRAX_DEF_GIO_PA_OUT=00
CONFIG_ETRAX_DEF_GIO_PB_OE=00000
CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
CONFIG_ETRAX_DEF_GIO_PC_OE=00000
CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
CONFIG_ETRAX_DEF_GIO_PD_OE=00000
CONFIG_ETRAX_DEF_GIO_PD_OUT=00000
CONFIG_ETRAX_DEF_GIO_PE_OE=00000
CONFIG_ETRAX_DEF_GIO_PE_OUT=00000
# CONFIG_CPU_FREQ is not set
# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
CONFIG_ETRAX_NBR_LED_GRP_ONE=y
# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
CONFIG_ETRAX_LED_G_NET0="PA3"
CONFIG_ETRAX_LED_R_NET0="PA4"
CONFIG_ETRAX_V32_LED2G="PA5"
CONFIG_ETRAX_V32_LED2R="PA6"
CONFIG_ETRAX_V32_LED3G="PA7"
CONFIG_ETRAX_V32_LED3R="PA7"
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IP_VS is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
#
# Core Netfilter Configuration
#
# CONFIG_NETFILTER_NETLINK is not set
# CONFIG_NF_CONNTRACK_ENABLED is not set
# CONFIG_NF_CONNTRACK is not set
# CONFIG_NETFILTER_XTABLES is not set
#
# IP: Netfilter Configuration
#
# CONFIG_IP_NF_QUEUE is not set
# CONFIG_IP_NF_IPTABLES is not set
# CONFIG_IP_NF_ARPTABLES is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Drivers for built-in interfaces
#
CONFIG_ETRAX_ETHERNET=y
# CONFIG_ETRAX_IDE is not set
CONFIG_ETRAX_AXISFLASHMAP=y
CONFIG_ETRAX_PTABLE_SECTOR=65536
# CONFIG_ETRAX_I2C is not set
# CONFIG_ETRAX_GPIO is not set
# CONFIG_ETRAX_NO_PHY is not set
# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
# CONFIG_ETRAX_ETHERNET_IFACE1 is not set
# CONFIG_ETRAXFS_SERIAL is not set
# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
# CONFIG_ETRAX_NANDFLASH is not set
# CONFIG_ETRAX_CARDBUS is not set
# CONFIG_ETRAX_IOP_FW_LOAD is not set
# CONFIG_ETRAX_STREAMCOPROC is not set
# CONFIG_ETRAX_SPI_MMC is not set
# CONFIG_ETRAX_SPI_MMC_BOARD is not set
# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_RTC_CLASS is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_HW_RANDOM=y
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PROFILING is not set
# CONFIG_SYSTEM_PROFILER is not set
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SAMPLES is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_DMA=y

34
include/asm-cris/arch-v32/mach-a3/arbiter.h Normal file
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@ -0,0 +1,34 @@
#ifndef _ASM_CRIS_ARCH_ARBITER_H
#define _ASM_CRIS_ARCH_ARBITER_H
#define EXT_REGION 0
#define INT_REGION 1
typedef void (watch_callback)(void);
enum {
arbiter_all_dmas = 0x7fe,
arbiter_cpu = 0x1800,
arbiter_all_clients = 0x7fff
};
enum {
arbiter_bar_all_clients = 0x1ff
};
enum {
arbiter_all_read = 0x55,
arbiter_all_write = 0xaa,
arbiter_all_accesses = 0xff
};
#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
int crisv32_arbiter_allocate_bandwith(int client, int region,
unsigned long bandwidth);
int crisv32_arbiter_watch(unsigned long start, unsigned long size,
unsigned long clients, unsigned long accesses,
watch_callback * cb);
int crisv32_arbiter_unwatch(int id);
#endif

31
include/asm-cris/arch-v32/mach-a3/dma.h Normal file
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@ -0,0 +1,31 @@
#ifndef _ASM_ARCH_CRIS_DMA_H
#define _ASM_ARCH_CRIS_DMA_H
/* Defines for using and allocating dma channels. */
#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
enum dma_owner {
dma_eth,
dma_ser0,
dma_ser1,
dma_ser2,
dma_ser3,
dma_ser4,
dma_iop,
dma_sser,
dma_strp,
dma_h264,
dma_jpeg
};
int crisv32_request_dma(unsigned int dmanr, const char *device_id,
unsigned options, unsigned bandwidth, enum dma_owner owner);
void crisv32_free_dma(unsigned int dmanr);
/* Masks used by crisv32_request_dma options: */
#define DMA_VERBOSE_ON_ERROR 1
#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
#define DMA_INT_MEM 4
#endif /* _ASM_ARCH_CRIS_DMA_H */

164
include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h Normal file
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@ -0,0 +1,164 @@
#ifndef __clkgen_defs_asm_h
#define __clkgen_defs_asm_h
/*
* This file is autogenerated from
* file: clkgen.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_bootsel, scope clkgen, type r */
#define reg_clkgen_r_bootsel___boot_mode___lsb 0
#define reg_clkgen_r_bootsel___boot_mode___width 5
#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
#define reg_clkgen_r_bootsel___intern_main_clk___width 1
#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
#define reg_clkgen_r_bootsel_offset 0
/* Register rw_clk_ctrl, scope clkgen, type rw */
#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
#define reg_clkgen_rw_clk_ctrl___pll___width 1
#define reg_clkgen_rw_clk_ctrl___pll___bit 0
#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
#define reg_clkgen_rw_clk_ctrl___cpu___width 1
#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
#define reg_clkgen_rw_clk_ctrl___vin___width 1
#define reg_clkgen_rw_clk_ctrl___vin___bit 3
#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
#define reg_clkgen_rw_clk_ctrl___sclr___width 1
#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
#define reg_clkgen_rw_clk_ctrl___h264___width 1
#define reg_clkgen_rw_clk_ctrl___h264___bit 5
#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
#define reg_clkgen_rw_clk_ctrl___eth___width 1
#define reg_clkgen_rw_clk_ctrl___eth___bit 8
#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
#define reg_clkgen_rw_clk_ctrl_offset 4
/* Constants */
#define regk_clkgen_eth1000_rx 0x0000000c
#define regk_clkgen_eth1000_tx 0x0000000e
#define regk_clkgen_eth100_rx 0x0000001d
#define regk_clkgen_eth100_rx_half 0x0000001c
#define regk_clkgen_eth100_tx 0x0000001f
#define regk_clkgen_eth100_tx_half 0x0000001e
#define regk_clkgen_nand_3_2 0x00000000
#define regk_clkgen_nand_3_2_0x30 0x00000002
#define regk_clkgen_nand_3_2_0x30_pll 0x00000012
#define regk_clkgen_nand_3_2_pll 0x00000010
#define regk_clkgen_nand_3_3 0x00000001
#define regk_clkgen_nand_3_3_0x30 0x00000003
#define regk_clkgen_nand_3_3_0x30_pll 0x00000013
#define regk_clkgen_nand_3_3_pll 0x00000011
#define regk_clkgen_nand_4_2 0x00000004
#define regk_clkgen_nand_4_2_0x30 0x00000006
#define regk_clkgen_nand_4_2_0x30_pll 0x00000016
#define regk_clkgen_nand_4_2_pll 0x00000014
#define regk_clkgen_nand_4_3 0x00000005
#define regk_clkgen_nand_4_3_0x30 0x00000007
#define regk_clkgen_nand_4_3_0x30_pll 0x00000017
#define regk_clkgen_nand_4_3_pll 0x00000015
#define regk_clkgen_nand_5_2 0x00000008
#define regk_clkgen_nand_5_2_0x30 0x0000000a
#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a
#define regk_clkgen_nand_5_2_pll 0x00000018
#define regk_clkgen_nand_5_3 0x00000009
#define regk_clkgen_nand_5_3_0x30 0x0000000b
#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b
#define regk_clkgen_nand_5_3_pll 0x00000019
#define regk_clkgen_no 0x00000000
#define regk_clkgen_rw_clk_ctrl_default 0x00000002
#define regk_clkgen_ser 0x0000000d
#define regk_clkgen_ser_pll 0x0000000f
#define regk_clkgen_yes 0x00000001
#endif /* __clkgen_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h Normal file
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#ifndef __ddr2_defs_asm_h
#define __ddr2_defs_asm_h
/*
* This file is autogenerated from
* file: ddr2.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope ddr2, type rw */
#define reg_ddr2_rw_cfg___col_width___lsb 0
#define reg_ddr2_rw_cfg___col_width___width 4
#define reg_ddr2_rw_cfg___nr_banks___lsb 4
#define reg_ddr2_rw_cfg___nr_banks___width 1
#define reg_ddr2_rw_cfg___nr_banks___bit 4
#define reg_ddr2_rw_cfg___bw___lsb 5
#define reg_ddr2_rw_cfg___bw___width 1
#define reg_ddr2_rw_cfg___bw___bit 5
#define reg_ddr2_rw_cfg___nr_ref___lsb 6
#define reg_ddr2_rw_cfg___nr_ref___width 4
#define reg_ddr2_rw_cfg___ref_interval___lsb 10
#define reg_ddr2_rw_cfg___ref_interval___width 11
#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
#define reg_ddr2_rw_cfg___odt_ctrl___width 2
#define reg_ddr2_rw_cfg___odt_mem___lsb 23
#define reg_ddr2_rw_cfg___odt_mem___width 1
#define reg_ddr2_rw_cfg___odt_mem___bit 23
#define reg_ddr2_rw_cfg___imp_strength___lsb 24
#define reg_ddr2_rw_cfg___imp_strength___width 1
#define reg_ddr2_rw_cfg___imp_strength___bit 24
#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
#define reg_ddr2_rw_cfg___imp_cal_override___width 1
#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
#define reg_ddr2_rw_cfg___dll_override___lsb 27
#define reg_ddr2_rw_cfg___dll_override___width 1
#define reg_ddr2_rw_cfg___dll_override___bit 27
#define reg_ddr2_rw_cfg_offset 0
/* Register rw_timing, scope ddr2, type rw */
#define reg_ddr2_rw_timing___wr___lsb 0
#define reg_ddr2_rw_timing___wr___width 3
#define reg_ddr2_rw_timing___rcd___lsb 3
#define reg_ddr2_rw_timing___rcd___width 3
#define reg_ddr2_rw_timing___rp___lsb 6
#define reg_ddr2_rw_timing___rp___width 3
#define reg_ddr2_rw_timing___ras___lsb 9
#define reg_ddr2_rw_timing___ras___width 4
#define reg_ddr2_rw_timing___rfc___lsb 13
#define reg_ddr2_rw_timing___rfc___width 7
#define reg_ddr2_rw_timing___rc___lsb 20
#define reg_ddr2_rw_timing___rc___width 5
#define reg_ddr2_rw_timing___rtp___lsb 25
#define reg_ddr2_rw_timing___rtp___width 2
#define reg_ddr2_rw_timing___rtw___lsb 27
#define reg_ddr2_rw_timing___rtw___width 3
#define reg_ddr2_rw_timing___wtr___lsb 30
#define reg_ddr2_rw_timing___wtr___width 2
#define reg_ddr2_rw_timing_offset 4
/* Register rw_latency, scope ddr2, type rw */
#define reg_ddr2_rw_latency___cas___lsb 0
#define reg_ddr2_rw_latency___cas___width 3
#define reg_ddr2_rw_latency___additive___lsb 3
#define reg_ddr2_rw_latency___additive___width 3
#define reg_ddr2_rw_latency_offset 8
/* Register rw_phy_cfg, scope ddr2, type rw */
#define reg_ddr2_rw_phy_cfg___en___lsb 0
#define reg_ddr2_rw_phy_cfg___en___width 1
#define reg_ddr2_rw_phy_cfg___en___bit 0
#define reg_ddr2_rw_phy_cfg_offset 12
/* Register rw_phy_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
#define reg_ddr2_rw_phy_ctrl___rst___width 1
#define reg_ddr2_rw_phy_ctrl___rst___bit 0
#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
#define reg_ddr2_rw_phy_ctrl_offset 16
/* Register rw_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
#define reg_ddr2_rw_ctrl___mrs_data___width 16
#define reg_ddr2_rw_ctrl___cmd___lsb 16
#define reg_ddr2_rw_ctrl___cmd___width 8
#define reg_ddr2_rw_ctrl_offset 20
/* Register rw_pwr_down, scope ddr2, type rw */
#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
#define reg_ddr2_rw_pwr_down___self_ref___width 2
#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
#define reg_ddr2_rw_pwr_down___phy_en___width 1
#define reg_ddr2_rw_pwr_down___phy_en___bit 2
#define reg_ddr2_rw_pwr_down_offset 24
/* Register r_stat, scope ddr2, type r */
#define reg_ddr2_r_stat___dll_lock___lsb 0
#define reg_ddr2_r_stat___dll_lock___width 1
#define reg_ddr2_r_stat___dll_lock___bit 0
#define reg_ddr2_r_stat___dll_delay_code___lsb 1
#define reg_ddr2_r_stat___dll_delay_code___width 7
#define reg_ddr2_r_stat___imp_cal_done___lsb 8
#define reg_ddr2_r_stat___imp_cal_done___width 1
#define reg_ddr2_r_stat___imp_cal_done___bit 8
#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
#define reg_ddr2_r_stat___imp_cal_fault___width 1
#define reg_ddr2_r_stat___imp_cal_fault___bit 9
#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
#define reg_ddr2_r_stat___cal_imp_pu___width 4
#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
#define reg_ddr2_r_stat___cal_imp_pd___width 4
#define reg_ddr2_r_stat_offset 28
/* Register rw_imp_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
#define reg_ddr2_rw_imp_ctrl_offset 32
#define STRIDE_ddr2_rw_dll_ctrl 4
/* Register rw_dll_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
#define reg_ddr2_rw_dll_ctrl___mode___width 1
#define reg_ddr2_rw_dll_ctrl___mode___bit 0
#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
#define reg_ddr2_rw_dll_ctrl_offset 36
#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
/* Constants */
#define regk_ddr2_al0 0x00000000
#define regk_ddr2_al1 0x00000008
#define regk_ddr2_al2 0x00000010
#define regk_ddr2_al3 0x00000018
#define regk_ddr2_al4 0x00000020
#define regk_ddr2_auto 0x00000003
#define regk_ddr2_bank4 0x00000000
#define regk_ddr2_bank8 0x00000001
#define regk_ddr2_bl4 0x00000002
#define regk_ddr2_bl8 0x00000003
#define regk_ddr2_bt_il 0x00000008
#define regk_ddr2_bt_seq 0x00000000
#define regk_ddr2_bw16 0x00000001
#define regk_ddr2_bw32 0x00000000
#define regk_ddr2_cas2 0x00000020
#define regk_ddr2_cas3 0x00000030
#define regk_ddr2_cas4 0x00000040
#define regk_ddr2_cas5 0x00000050
#define regk_ddr2_deselect 0x000000c0
#define regk_ddr2_dic_weak 0x00000002
#define regk_ddr2_direct 0x00000001
#define regk_ddr2_dis 0x00000000
#define regk_ddr2_dll_dis 0x00000001
#define regk_ddr2_dll_en 0x00000000
#define regk_ddr2_dll_rst 0x00000100
#define regk_ddr2_emrs 0x00000081
#define regk_ddr2_emrs2 0x00000082
#define regk_ddr2_emrs3 0x00000083
#define regk_ddr2_full 0x00000001
#define regk_ddr2_hi_ref_rate 0x00000080
#define regk_ddr2_mrs 0x00000080
#define regk_ddr2_no 0x00000000
#define regk_ddr2_nop 0x000000b8
#define regk_ddr2_ocd_adj 0x00000200
#define regk_ddr2_ocd_default 0x00000380
#define regk_ddr2_ocd_drive0 0x00000100
#define regk_ddr2_ocd_drive1 0x00000080
#define regk_ddr2_ocd_exit 0x00000000
#define regk_ddr2_odt_dis 0x00000000
#define regk_ddr2_offs 0x00000000
#define regk_ddr2_pre 0x00000090
#define regk_ddr2_pre_all 0x00000400
#define regk_ddr2_pwr_down_fast 0x00000000
#define regk_ddr2_pwr_down_slow 0x00001000
#define regk_ddr2_ref 0x00000088
#define regk_ddr2_rtt150 0x00000040
#define regk_ddr2_rtt50 0x00000044
#define regk_ddr2_rtt75 0x00000004
#define regk_ddr2_rw_cfg_default 0x00186000
#define regk_ddr2_rw_dll_ctrl_default 0x00000000
#define regk_ddr2_rw_dll_ctrl_size 0x00000004
#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000
#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004
#define regk_ddr2_rw_latency_default 0x00000000
#define regk_ddr2_rw_phy_cfg_default 0x00000000
#define regk_ddr2_rw_pwr_down_default 0x00000000
#define regk_ddr2_rw_timing_default 0x00000000
#define regk_ddr2_s1Gb 0x0000001a
#define regk_ddr2_s256Mb 0x0000000f
#define regk_ddr2_s2Gb 0x00000027
#define regk_ddr2_s4Gb 0x00000042
#define regk_ddr2_s512Mb 0x00000015
#define regk_ddr2_temp0_85 0x00000618
#define regk_ddr2_temp85_95 0x0000030c
#define regk_ddr2_term150 0x00000002
#define regk_ddr2_term50 0x00000003
#define regk_ddr2_term75 0x00000001
#define regk_ddr2_test 0x00000080
#define regk_ddr2_weak 0x00000000
#define regk_ddr2_wr2 0x00000200
#define regk_ddr2_wr3 0x00000400
#define regk_ddr2_yes 0x00000001
#endif /* __ddr2_defs_asm_h */

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#ifndef __gio_defs_asm_h
#define __gio_defs_asm_h
/*
* This file is autogenerated from
* file: gio.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_pa_din, scope gio, type r */
#define reg_gio_r_pa_din___data___lsb 0
#define reg_gio_r_pa_din___data___width 32
#define reg_gio_r_pa_din_offset 0
/* Register rw_pa_dout, scope gio, type rw */
#define reg_gio_rw_pa_dout___data___lsb 0
#define reg_gio_rw_pa_dout___data___width 32
#define reg_gio_rw_pa_dout_offset 4
/* Register rw_pa_oe, scope gio, type rw */
#define reg_gio_rw_pa_oe___oe___lsb 0
#define reg_gio_rw_pa_oe___oe___width 32
#define reg_gio_rw_pa_oe_offset 8
/* Register rw_pa_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte0_dout___data___lsb 0
#define reg_gio_rw_pa_byte0_dout___data___width 8
#define reg_gio_rw_pa_byte0_dout_offset 12
/* Register rw_pa_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
#define reg_gio_rw_pa_byte0_oe___oe___width 8
#define reg_gio_rw_pa_byte0_oe_offset 16
/* Register rw_pa_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte1_dout___data___lsb 0
#define reg_gio_rw_pa_byte1_dout___data___width 8
#define reg_gio_rw_pa_byte1_dout_offset 20
/* Register rw_pa_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
#define reg_gio_rw_pa_byte1_oe___oe___width 8
#define reg_gio_rw_pa_byte1_oe_offset 24
/* Register rw_pa_byte2_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte2_dout___data___lsb 0
#define reg_gio_rw_pa_byte2_dout___data___width 8
#define reg_gio_rw_pa_byte2_dout_offset 28
/* Register rw_pa_byte2_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
#define reg_gio_rw_pa_byte2_oe___oe___width 8
#define reg_gio_rw_pa_byte2_oe_offset 32
/* Register rw_pa_byte3_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte3_dout___data___lsb 0
#define reg_gio_rw_pa_byte3_dout___data___width 8
#define reg_gio_rw_pa_byte3_dout_offset 36
/* Register rw_pa_byte3_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
#define reg_gio_rw_pa_byte3_oe___oe___width 8
#define reg_gio_rw_pa_byte3_oe_offset 40
/* Register r_pb_din, scope gio, type r */
#define reg_gio_r_pb_din___data___lsb 0
#define reg_gio_r_pb_din___data___width 32
#define reg_gio_r_pb_din_offset 44
/* Register rw_pb_dout, scope gio, type rw */
#define reg_gio_rw_pb_dout___data___lsb 0
#define reg_gio_rw_pb_dout___data___width 32
#define reg_gio_rw_pb_dout_offset 48
/* Register rw_pb_oe, scope gio, type rw */
#define reg_gio_rw_pb_oe___oe___lsb 0
#define reg_gio_rw_pb_oe___oe___width 32
#define reg_gio_rw_pb_oe_offset 52
/* Register rw_pb_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte0_dout___data___lsb 0
#define reg_gio_rw_pb_byte0_dout___data___width 8
#define reg_gio_rw_pb_byte0_dout_offset 56
/* Register rw_pb_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
#define reg_gio_rw_pb_byte0_oe___oe___width 8
#define reg_gio_rw_pb_byte0_oe_offset 60
/* Register rw_pb_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte1_dout___data___lsb 0
#define reg_gio_rw_pb_byte1_dout___data___width 8
#define reg_gio_rw_pb_byte1_dout_offset 64
/* Register rw_pb_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
#define reg_gio_rw_pb_byte1_oe___oe___width 8
#define reg_gio_rw_pb_byte1_oe_offset 68
/* Register rw_pb_byte2_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte2_dout___data___lsb 0
#define reg_gio_rw_pb_byte2_dout___data___width 8
#define reg_gio_rw_pb_byte2_dout_offset 72
/* Register rw_pb_byte2_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
#define reg_gio_rw_pb_byte2_oe___oe___width 8
#define reg_gio_rw_pb_byte2_oe_offset 76
/* Register rw_pb_byte3_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte3_dout___data___lsb 0
#define reg_gio_rw_pb_byte3_dout___data___width 8
#define reg_gio_rw_pb_byte3_dout_offset 80
/* Register rw_pb_byte3_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
#define reg_gio_rw_pb_byte3_oe___oe___width 8
#define reg_gio_rw_pb_byte3_oe_offset 84
/* Register r_pc_din, scope gio, type r */
#define reg_gio_r_pc_din___data___lsb 0
#define reg_gio_r_pc_din___data___width 16
#define reg_gio_r_pc_din_offset 88
/* Register rw_pc_dout, scope gio, type rw */
#define reg_gio_rw_pc_dout___data___lsb 0
#define reg_gio_rw_pc_dout___data___width 16
#define reg_gio_rw_pc_dout_offset 92
/* Register rw_pc_oe, scope gio, type rw */
#define reg_gio_rw_pc_oe___oe___lsb 0
#define reg_gio_rw_pc_oe___oe___width 16
#define reg_gio_rw_pc_oe_offset 96
/* Register rw_pc_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pc_byte0_dout___data___lsb 0
#define reg_gio_rw_pc_byte0_dout___data___width 8
#define reg_gio_rw_pc_byte0_dout_offset 100
/* Register rw_pc_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
#define reg_gio_rw_pc_byte0_oe___oe___width 8
#define reg_gio_rw_pc_byte0_oe_offset 104
/* Register rw_pc_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pc_byte1_dout___data___lsb 0
#define reg_gio_rw_pc_byte1_dout___data___width 8
#define reg_gio_rw_pc_byte1_dout_offset 108
/* Register rw_pc_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
#define reg_gio_rw_pc_byte1_oe___oe___width 8
#define reg_gio_rw_pc_byte1_oe_offset 112
/* Register r_pd_din, scope gio, type r */
#define reg_gio_r_pd_din___data___lsb 0
#define reg_gio_r_pd_din___data___width 32
#define reg_gio_r_pd_din_offset 116
/* Register rw_intr_cfg, scope gio, type rw */
#define reg_gio_rw_intr_cfg___intr0___lsb 0
#define reg_gio_rw_intr_cfg___intr0___width 3
#define reg_gio_rw_intr_cfg___intr1___lsb 3
#define reg_gio_rw_intr_cfg___intr1___width 3
#define reg_gio_rw_intr_cfg___intr2___lsb 6
#define reg_gio_rw_intr_cfg___intr2___width 3
#define reg_gio_rw_intr_cfg___intr3___lsb 9
#define reg_gio_rw_intr_cfg___intr3___width 3
#define reg_gio_rw_intr_cfg___intr4___lsb 12
#define reg_gio_rw_intr_cfg___intr4___width 3
#define reg_gio_rw_intr_cfg___intr5___lsb 15
#define reg_gio_rw_intr_cfg___intr5___width 3
#define reg_gio_rw_intr_cfg___intr6___lsb 18
#define reg_gio_rw_intr_cfg___intr6___width 3
#define reg_gio_rw_intr_cfg___intr7___lsb 21
#define reg_gio_rw_intr_cfg___intr7___width 3
#define reg_gio_rw_intr_cfg_offset 120
/* Register rw_intr_pins, scope gio, type rw */
#define reg_gio_rw_intr_pins___intr0___lsb 0
#define reg_gio_rw_intr_pins___intr0___width 4
#define reg_gio_rw_intr_pins___intr1___lsb 4
#define reg_gio_rw_intr_pins___intr1___width 4
#define reg_gio_rw_intr_pins___intr2___lsb 8
#define reg_gio_rw_intr_pins___intr2___width 4
#define reg_gio_rw_intr_pins___intr3___lsb 12
#define reg_gio_rw_intr_pins___intr3___width 4
#define reg_gio_rw_intr_pins___intr4___lsb 16
#define reg_gio_rw_intr_pins___intr4___width 4
#define reg_gio_rw_intr_pins___intr5___lsb 20
#define reg_gio_rw_intr_pins___intr5___width 4
#define reg_gio_rw_intr_pins___intr6___lsb 24
#define reg_gio_rw_intr_pins___intr6___width 4
#define reg_gio_rw_intr_pins___intr7___lsb 28
#define reg_gio_rw_intr_pins___intr7___width 4
#define reg_gio_rw_intr_pins_offset 124
/* Register rw_intr_mask, scope gio, type rw */
#define reg_gio_rw_intr_mask___intr0___lsb 0
#define reg_gio_rw_intr_mask___intr0___width 1
#define reg_gio_rw_intr_mask___intr0___bit 0
#define reg_gio_rw_intr_mask___intr1___lsb 1
#define reg_gio_rw_intr_mask___intr1___width 1
#define reg_gio_rw_intr_mask___intr1___bit 1
#define reg_gio_rw_intr_mask___intr2___lsb 2
#define reg_gio_rw_intr_mask___intr2___width 1
#define reg_gio_rw_intr_mask___intr2___bit 2
#define reg_gio_rw_intr_mask___intr3___lsb 3
#define reg_gio_rw_intr_mask___intr3___width 1
#define reg_gio_rw_intr_mask___intr3___bit 3
#define reg_gio_rw_intr_mask___intr4___lsb 4
#define reg_gio_rw_intr_mask___intr4___width 1
#define reg_gio_rw_intr_mask___intr4___bit 4
#define reg_gio_rw_intr_mask___intr5___lsb 5
#define reg_gio_rw_intr_mask___intr5___width 1
#define reg_gio_rw_intr_mask___intr5___bit 5
#define reg_gio_rw_intr_mask___intr6___lsb 6
#define reg_gio_rw_intr_mask___intr6___width 1
#define reg_gio_rw_intr_mask___intr6___bit 6
#define reg_gio_rw_intr_mask___intr7___lsb 7
#define reg_gio_rw_intr_mask___intr7___width 1
#define reg_gio_rw_intr_mask___intr7___bit 7
#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
#define reg_gio_rw_intr_mask___i2c0_done___width 1
#define reg_gio_rw_intr_mask___i2c0_done___bit 8
#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
#define reg_gio_rw_intr_mask___i2c1_done___width 1
#define reg_gio_rw_intr_mask___i2c1_done___bit 9
#define reg_gio_rw_intr_mask_offset 128
/* Register rw_ack_intr, scope gio, type rw */
#define reg_gio_rw_ack_intr___intr0___lsb 0
#define reg_gio_rw_ack_intr___intr0___width 1
#define reg_gio_rw_ack_intr___intr0___bit 0
#define reg_gio_rw_ack_intr___intr1___lsb 1
#define reg_gio_rw_ack_intr___intr1___width 1
#define reg_gio_rw_ack_intr___intr1___bit 1
#define reg_gio_rw_ack_intr___intr2___lsb 2
#define reg_gio_rw_ack_intr___intr2___width 1
#define reg_gio_rw_ack_intr___intr2___bit 2
#define reg_gio_rw_ack_intr___intr3___lsb 3
#define reg_gio_rw_ack_intr___intr3___width 1
#define reg_gio_rw_ack_intr___intr3___bit 3
#define reg_gio_rw_ack_intr___intr4___lsb 4
#define reg_gio_rw_ack_intr___intr4___width 1
#define reg_gio_rw_ack_intr___intr4___bit 4
#define reg_gio_rw_ack_intr___intr5___lsb 5
#define reg_gio_rw_ack_intr___intr5___width 1
#define reg_gio_rw_ack_intr___intr5___bit 5
#define reg_gio_rw_ack_intr___intr6___lsb 6
#define reg_gio_rw_ack_intr___intr6___width 1
#define reg_gio_rw_ack_intr___intr6___bit 6
#define reg_gio_rw_ack_intr___intr7___lsb 7
#define reg_gio_rw_ack_intr___intr7___width 1
#define reg_gio_rw_ack_intr___intr7___bit 7
#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
#define reg_gio_rw_ack_intr___i2c0_done___width 1
#define reg_gio_rw_ack_intr___i2c0_done___bit 8
#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
#define reg_gio_rw_ack_intr___i2c1_done___width 1
#define reg_gio_rw_ack_intr___i2c1_done___bit 9
#define reg_gio_rw_ack_intr_offset 132
/* Register r_intr, scope gio, type r */
#define reg_gio_r_intr___intr0___lsb 0
#define reg_gio_r_intr___intr0___width 1
#define reg_gio_r_intr___intr0___bit 0
#define reg_gio_r_intr___intr1___lsb 1
#define reg_gio_r_intr___intr1___width 1
#define reg_gio_r_intr___intr1___bit 1
#define reg_gio_r_intr___intr2___lsb 2
#define reg_gio_r_intr___intr2___width 1
#define reg_gio_r_intr___intr2___bit 2
#define reg_gio_r_intr___intr3___lsb 3
#define reg_gio_r_intr___intr3___width 1
#define reg_gio_r_intr___intr3___bit 3
#define reg_gio_r_intr___intr4___lsb 4
#define reg_gio_r_intr___intr4___width 1
#define reg_gio_r_intr___intr4___bit 4
#define reg_gio_r_intr___intr5___lsb 5
#define reg_gio_r_intr___intr5___width 1
#define reg_gio_r_intr___intr5___bit 5
#define reg_gio_r_intr___intr6___lsb 6
#define reg_gio_r_intr___intr6___width 1
#define reg_gio_r_intr___intr6___bit 6
#define reg_gio_r_intr___intr7___lsb 7
#define reg_gio_r_intr___intr7___width 1
#define reg_gio_r_intr___intr7___bit 7
#define reg_gio_r_intr___i2c0_done___lsb 8
#define reg_gio_r_intr___i2c0_done___width 1
#define reg_gio_r_intr___i2c0_done___bit 8
#define reg_gio_r_intr___i2c1_done___lsb 9
#define reg_gio_r_intr___i2c1_done___width 1
#define reg_gio_r_intr___i2c1_done___bit 9
#define reg_gio_r_intr_offset 136
/* Register r_masked_intr, scope gio, type r */
#define reg_gio_r_masked_intr___intr0___lsb 0
#define reg_gio_r_masked_intr___intr0___width 1
#define reg_gio_r_masked_intr___intr0___bit 0
#define reg_gio_r_masked_intr___intr1___lsb 1
#define reg_gio_r_masked_intr___intr1___width 1
#define reg_gio_r_masked_intr___intr1___bit 1
#define reg_gio_r_masked_intr___intr2___lsb 2
#define reg_gio_r_masked_intr___intr2___width 1
#define reg_gio_r_masked_intr___intr2___bit 2
#define reg_gio_r_masked_intr___intr3___lsb 3
#define reg_gio_r_masked_intr___intr3___width 1
#define reg_gio_r_masked_intr___intr3___bit 3
#define reg_gio_r_masked_intr___intr4___lsb 4
#define reg_gio_r_masked_intr___intr4___width 1
#define reg_gio_r_masked_intr___intr4___bit 4
#define reg_gio_r_masked_intr___intr5___lsb 5
#define reg_gio_r_masked_intr___intr5___width 1
#define reg_gio_r_masked_intr___intr5___bit 5
#define reg_gio_r_masked_intr___intr6___lsb 6
#define reg_gio_r_masked_intr___intr6___width 1
#define reg_gio_r_masked_intr___intr6___bit 6
#define reg_gio_r_masked_intr___intr7___lsb 7
#define reg_gio_r_masked_intr___intr7___width 1
#define reg_gio_r_masked_intr___intr7___bit 7
#define reg_gio_r_masked_intr___i2c0_done___lsb 8
#define reg_gio_r_masked_intr___i2c0_done___width 1
#define reg_gio_r_masked_intr___i2c0_done___bit 8
#define reg_gio_r_masked_intr___i2c1_done___lsb 9
#define reg_gio_r_masked_intr___i2c1_done___width 1
#define reg_gio_r_masked_intr___i2c1_done___bit 9
#define reg_gio_r_masked_intr_offset 140
/* Register rw_i2c0_start, scope gio, type rw */
#define reg_gio_rw_i2c0_start___run___lsb 0
#define reg_gio_rw_i2c0_start___run___width 1
#define reg_gio_rw_i2c0_start___run___bit 0
#define reg_gio_rw_i2c0_start_offset 144
/* Register rw_i2c0_cfg, scope gio, type rw */
#define reg_gio_rw_i2c0_cfg___en___lsb 0
#define reg_gio_rw_i2c0_cfg___en___width 1
#define reg_gio_rw_i2c0_cfg___en___bit 0
#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
#define reg_gio_rw_i2c0_cfg___bit_order___width 1
#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
#define reg_gio_rw_i2c0_cfg___scl_io___width 1
#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
#define reg_gio_rw_i2c0_cfg___sda_io___width 1
#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
#define reg_gio_rw_i2c0_cfg_offset 148
/* Register rw_i2c0_ctrl, scope gio, type rw */
#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
#define reg_gio_rw_i2c0_ctrl___early_end___width 1
#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
#define reg_gio_rw_i2c0_ctrl___freq___width 2
#define reg_gio_rw_i2c0_ctrl_offset 152
/* Register rw_i2c0_data, scope gio, type rw */
#define reg_gio_rw_i2c0_data___data0___lsb 0
#define reg_gio_rw_i2c0_data___data0___width 8
#define reg_gio_rw_i2c0_data___data1___lsb 8
#define reg_gio_rw_i2c0_data___data1___width 8
#define reg_gio_rw_i2c0_data___data2___lsb 16
#define reg_gio_rw_i2c0_data___data2___width 8
#define reg_gio_rw_i2c0_data___data3___lsb 24
#define reg_gio_rw_i2c0_data___data3___width 8
#define reg_gio_rw_i2c0_data_offset 156
/* Register rw_i2c0_data2, scope gio, type rw */
#define reg_gio_rw_i2c0_data2___data4___lsb 0
#define reg_gio_rw_i2c0_data2___data4___width 8
#define reg_gio_rw_i2c0_data2___data5___lsb 8
#define reg_gio_rw_i2c0_data2___data5___width 8
#define reg_gio_rw_i2c0_data2___start_val___lsb 16
#define reg_gio_rw_i2c0_data2___start_val___width 6
#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
#define reg_gio_rw_i2c0_data2___ack_val___width 6
#define reg_gio_rw_i2c0_data2_offset 160
/* Register rw_i2c1_start, scope gio, type rw */
#define reg_gio_rw_i2c1_start___run___lsb 0
#define reg_gio_rw_i2c1_start___run___width 1
#define reg_gio_rw_i2c1_start___run___bit 0
#define reg_gio_rw_i2c1_start_offset 164
/* Register rw_i2c1_cfg, scope gio, type rw */
#define reg_gio_rw_i2c1_cfg___en___lsb 0
#define reg_gio_rw_i2c1_cfg___en___width 1
#define reg_gio_rw_i2c1_cfg___en___bit 0
#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
#define reg_gio_rw_i2c1_cfg___bit_order___width 1
#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
#define reg_gio_rw_i2c1_cfg___scl_io___width 1
#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
#define reg_gio_rw_i2c1_cfg_offset 168
/* Register rw_i2c1_ctrl, scope gio, type rw */
#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
#define reg_gio_rw_i2c1_ctrl___early_end___width 1
#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
#define reg_gio_rw_i2c1_ctrl___freq___width 2
#define reg_gio_rw_i2c1_ctrl_offset 172
/* Register rw_i2c1_data, scope gio, type rw */
#define reg_gio_rw_i2c1_data___data0___lsb 0
#define reg_gio_rw_i2c1_data___data0___width 8
#define reg_gio_rw_i2c1_data___data1___lsb 8
#define reg_gio_rw_i2c1_data___data1___width 8
#define reg_gio_rw_i2c1_data___data2___lsb 16
#define reg_gio_rw_i2c1_data___data2___width 8
#define reg_gio_rw_i2c1_data___data3___lsb 24
#define reg_gio_rw_i2c1_data___data3___width 8
#define reg_gio_rw_i2c1_data_offset 176
/* Register rw_i2c1_data2, scope gio, type rw */
#define reg_gio_rw_i2c1_data2___data4___lsb 0
#define reg_gio_rw_i2c1_data2___data4___width 8
#define reg_gio_rw_i2c1_data2___data5___lsb 8
#define reg_gio_rw_i2c1_data2___data5___width 8
#define reg_gio_rw_i2c1_data2___start_val___lsb 16
#define reg_gio_rw_i2c1_data2___start_val___width 6
#define reg_gio_rw_i2c1_data2___ack_val___lsb 22
#define reg_gio_rw_i2c1_data2___ack_val___width 6
#define reg_gio_rw_i2c1_data2_offset 180
/* Register r_ppwm_stat, scope gio, type r */
#define reg_gio_r_ppwm_stat___freq___lsb 0
#define reg_gio_r_ppwm_stat___freq___width 2
#define reg_gio_r_ppwm_stat_offset 184
/* Register rw_ppwm_data, scope gio, type rw */
#define reg_gio_rw_ppwm_data___data___lsb 0
#define reg_gio_rw_ppwm_data___data___width 8
#define reg_gio_rw_ppwm_data_offset 188
/* Register rw_pwm0_ctrl, scope gio, type rw */
#define reg_gio_rw_pwm0_ctrl___mode___lsb 0
#define reg_gio_rw_pwm0_ctrl___mode___width 2
#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2
#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1
#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2
#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3
#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1
#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3
#define reg_gio_rw_pwm0_ctrl_offset 192
/* Register rw_pwm0_var, scope gio, type rw */
#define reg_gio_rw_pwm0_var___lo___lsb 0
#define reg_gio_rw_pwm0_var___lo___width 13
#define reg_gio_rw_pwm0_var___hi___lsb 13
#define reg_gio_rw_pwm0_var___hi___width 13
#define reg_gio_rw_pwm0_var_offset 196
/* Register rw_pwm0_data, scope gio, type rw */
#define reg_gio_rw_pwm0_data___data___lsb 0
#define reg_gio_rw_pwm0_data___data___width 8
#define reg_gio_rw_pwm0_data_offset 200
/* Register rw_pwm1_ctrl, scope gio, type rw */
#define reg_gio_rw_pwm1_ctrl___mode___lsb 0
#define reg_gio_rw_pwm1_ctrl___mode___width 2
#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2
#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1
#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2
#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3
#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1
#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3
#define reg_gio_rw_pwm1_ctrl_offset 204
/* Register rw_pwm1_var, scope gio, type rw */
#define reg_gio_rw_pwm1_var___lo___lsb 0
#define reg_gio_rw_pwm1_var___lo___width 13
#define reg_gio_rw_pwm1_var___hi___lsb 13
#define reg_gio_rw_pwm1_var___hi___width 13
#define reg_gio_rw_pwm1_var_offset 208
/* Register rw_pwm1_data, scope gio, type rw */
#define reg_gio_rw_pwm1_data___data___lsb 0
#define reg_gio_rw_pwm1_data___data___width 8
#define reg_gio_rw_pwm1_data_offset 212
/* Register rw_pwm2_ctrl, scope gio, type rw */
#define reg_gio_rw_pwm2_ctrl___mode___lsb 0
#define reg_gio_rw_pwm2_ctrl___mode___width 2
#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2
#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1
#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2
#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3
#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1
#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3
#define reg_gio_rw_pwm2_ctrl_offset 216
/* Register rw_pwm2_var, scope gio, type rw */
#define reg_gio_rw_pwm2_var___lo___lsb 0
#define reg_gio_rw_pwm2_var___lo___width 13
#define reg_gio_rw_pwm2_var___hi___lsb 13
#define reg_gio_rw_pwm2_var___hi___width 13
#define reg_gio_rw_pwm2_var_offset 220
/* Register rw_pwm2_data, scope gio, type rw */
#define reg_gio_rw_pwm2_data___data___lsb 0
#define reg_gio_rw_pwm2_data___data___width 8
#define reg_gio_rw_pwm2_data_offset 224
/* Register rw_pwm_in_cfg, scope gio, type rw */
#define reg_gio_rw_pwm_in_cfg___pin___lsb 0
#define reg_gio_rw_pwm_in_cfg___pin___width 3
#define reg_gio_rw_pwm_in_cfg_offset 228
/* Register r_pwm_in_lo, scope gio, type r */
#define reg_gio_r_pwm_in_lo___data___lsb 0
#define reg_gio_r_pwm_in_lo___data___width 32
#define reg_gio_r_pwm_in_lo_offset 232
/* Register r_pwm_in_hi, scope gio, type r */
#define reg_gio_r_pwm_in_hi___data___lsb 0
#define reg_gio_r_pwm_in_hi___data___width 32
#define reg_gio_r_pwm_in_hi_offset 236
/* Register r_pwm_in_cnt, scope gio, type r */
#define reg_gio_r_pwm_in_cnt___data___lsb 0
#define reg_gio_r_pwm_in_cnt___data___width 32
#define reg_gio_r_pwm_in_cnt_offset 240
/* Constants */
#define regk_gio_anyedge 0x00000007
#define regk_gio_f100k 0x00000000
#define regk_gio_f1562 0x00000000
#define regk_gio_f195 0x00000003
#define regk_gio_f1m 0x00000002
#define regk_gio_f390 0x00000002
#define regk_gio_f400k 0x00000001
#define regk_gio_f5m 0x00000003
#define regk_gio_f781 0x00000001
#define regk_gio_hi 0x00000001
#define regk_gio_in 0x00000000
#define regk_gio_intr_pa0 0x00000000
#define regk_gio_intr_pa1 0x00000000
#define regk_gio_intr_pa10 0x00000001
#define regk_gio_intr_pa11 0x00000001
#define regk_gio_intr_pa12 0x00000001
#define regk_gio_intr_pa13 0x00000001
#define regk_gio_intr_pa14 0x00000001
#define regk_gio_intr_pa15 0x00000001
#define regk_gio_intr_pa16 0x00000002
#define regk_gio_intr_pa17 0x00000002
#define regk_gio_intr_pa18 0x00000002
#define regk_gio_intr_pa19 0x00000002
#define regk_gio_intr_pa2 0x00000000
#define regk_gio_intr_pa20 0x00000002
#define regk_gio_intr_pa21 0x00000002
#define regk_gio_intr_pa22 0x00000002
#define regk_gio_intr_pa23 0x00000002
#define regk_gio_intr_pa24 0x00000003
#define regk_gio_intr_pa25 0x00000003
#define regk_gio_intr_pa26 0x00000003
#define regk_gio_intr_pa27 0x00000003
#define regk_gio_intr_pa28 0x00000003
#define regk_gio_intr_pa29 0x00000003
#define regk_gio_intr_pa3 0x00000000
#define regk_gio_intr_pa30 0x00000003
#define regk_gio_intr_pa31 0x00000003
#define regk_gio_intr_pa4 0x00000000
#define regk_gio_intr_pa5 0x00000000
#define regk_gio_intr_pa6 0x00000000
#define regk_gio_intr_pa7 0x00000000
#define regk_gio_intr_pa8 0x00000001
#define regk_gio_intr_pa9 0x00000001
#define regk_gio_intr_pb0 0x00000004
#define regk_gio_intr_pb1 0x00000004
#define regk_gio_intr_pb10 0x00000005
#define regk_gio_intr_pb11 0x00000005
#define regk_gio_intr_pb12 0x00000005
#define regk_gio_intr_pb13 0x00000005
#define regk_gio_intr_pb14 0x00000005
#define regk_gio_intr_pb15 0x00000005
#define regk_gio_intr_pb16 0x00000006
#define regk_gio_intr_pb17 0x00000006
#define regk_gio_intr_pb18 0x00000006
#define regk_gio_intr_pb19 0x00000006
#define regk_gio_intr_pb2 0x00000004
#define regk_gio_intr_pb20 0x00000006
#define regk_gio_intr_pb21 0x00000006
#define regk_gio_intr_pb22 0x00000006
#define regk_gio_intr_pb23 0x00000006
#define regk_gio_intr_pb24 0x00000007
#define regk_gio_intr_pb25 0x00000007
#define regk_gio_intr_pb26 0x00000007
#define regk_gio_intr_pb27 0x00000007
#define regk_gio_intr_pb28 0x00000007
#define regk_gio_intr_pb29 0x00000007
#define regk_gio_intr_pb3 0x00000004
#define regk_gio_intr_pb30 0x00000007
#define regk_gio_intr_pb31 0x00000007
#define regk_gio_intr_pb4 0x00000004
#define regk_gio_intr_pb5 0x00000004
#define regk_gio_intr_pb6 0x00000004
#define regk_gio_intr_pb7 0x00000004
#define regk_gio_intr_pb8 0x00000005
#define regk_gio_intr_pb9 0x00000005
#define regk_gio_intr_pc0 0x00000008
#define regk_gio_intr_pc1 0x00000008
#define regk_gio_intr_pc10 0x00000009
#define regk_gio_intr_pc11 0x00000009
#define regk_gio_intr_pc12 0x00000009
#define regk_gio_intr_pc13 0x00000009
#define regk_gio_intr_pc14 0x00000009
#define regk_gio_intr_pc15 0x00000009
#define regk_gio_intr_pc2 0x00000008
#define regk_gio_intr_pc3 0x00000008
#define regk_gio_intr_pc4 0x00000008
#define regk_gio_intr_pc5 0x00000008
#define regk_gio_intr_pc6 0x00000008
#define regk_gio_intr_pc7 0x00000008
#define regk_gio_intr_pc8 0x00000009
#define regk_gio_intr_pc9 0x00000009
#define regk_gio_intr_pd0 0x0000000c
#define regk_gio_intr_pd1 0x0000000c
#define regk_gio_intr_pd10 0x0000000d
#define regk_gio_intr_pd11 0x0000000d
#define regk_gio_intr_pd12 0x0000000d
#define regk_gio_intr_pd13 0x0000000d
#define regk_gio_intr_pd14 0x0000000d
#define regk_gio_intr_pd15 0x0000000d
#define regk_gio_intr_pd16 0x0000000e
#define regk_gio_intr_pd17 0x0000000e
#define regk_gio_intr_pd18 0x0000000e
#define regk_gio_intr_pd19 0x0000000e
#define regk_gio_intr_pd2 0x0000000c
#define regk_gio_intr_pd20 0x0000000e
#define regk_gio_intr_pd21 0x0000000e
#define regk_gio_intr_pd22 0x0000000e
#define regk_gio_intr_pd23 0x0000000e
#define regk_gio_intr_pd24 0x0000000f
#define regk_gio_intr_pd25 0x0000000f
#define regk_gio_intr_pd26 0x0000000f
#define regk_gio_intr_pd27 0x0000000f
#define regk_gio_intr_pd28 0x0000000f
#define regk_gio_intr_pd29 0x0000000f
#define regk_gio_intr_pd3 0x0000000c
#define regk_gio_intr_pd30 0x0000000f
#define regk_gio_intr_pd31 0x0000000f
#define regk_gio_intr_pd4 0x0000000c
#define regk_gio_intr_pd5 0x0000000c
#define regk_gio_intr_pd6 0x0000000c
#define regk_gio_intr_pd7 0x0000000c
#define regk_gio_intr_pd8 0x0000000d
#define regk_gio_intr_pd9 0x0000000d
#define regk_gio_lo 0x00000002
#define regk_gio_lsb 0x00000000
#define regk_gio_msb 0x00000001
#define regk_gio_negedge 0x00000006
#define regk_gio_no 0x00000000
#define regk_gio_no_switch 0x0000003f
#define regk_gio_none 0x00000007
#define regk_gio_off 0x00000000
#define regk_gio_opendrain 0x00000000
#define regk_gio_out 0x00000001
#define regk_gio_posedge 0x00000005
#define regk_gio_pwm_hfp 0x00000002
#define regk_gio_pwm_pa0 0x00000001
#define regk_gio_pwm_pa19 0x00000004
#define regk_gio_pwm_pa6 0x00000002
#define regk_gio_pwm_pa7 0x00000003
#define regk_gio_pwm_pb26 0x00000005
#define regk_gio_pwm_pd23 0x00000006
#define regk_gio_pwm_pd31 0x00000007
#define regk_gio_pwm_std 0x00000001
#define regk_gio_pwm_var 0x00000003
#define regk_gio_rw_i2c0_cfg_default 0x00000020
#define regk_gio_rw_i2c0_ctrl_default 0x00010000
#define regk_gio_rw_i2c0_start_default 0x00000000
#define regk_gio_rw_i2c1_cfg_default 0x00000aa0
#define regk_gio_rw_i2c1_ctrl_default 0x00010000
#define regk_gio_rw_i2c1_start_default 0x00000000
#define regk_gio_rw_intr_cfg_default 0x00000000
#define regk_gio_rw_intr_mask_default 0x00000000
#define regk_gio_rw_pa_oe_default 0x00000000
#define regk_gio_rw_pb_oe_default 0x00000000
#define regk_gio_rw_pc_oe_default 0x00000000
#define regk_gio_rw_ppwm_data_default 0x00000000
#define regk_gio_rw_pwm0_ctrl_default 0x00000000
#define regk_gio_rw_pwm1_ctrl_default 0x00000000
#define regk_gio_rw_pwm2_ctrl_default 0x00000000
#define regk_gio_rw_pwm_in_cfg_default 0x00000000
#define regk_gio_sda0 0x00000000
#define regk_gio_sda1 0x00000001
#define regk_gio_sda2 0x00000002
#define regk_gio_sda3 0x00000003
#define regk_gio_sen 0x00000000
#define regk_gio_set 0x00000003
#define regk_gio_yes 0x00000001
#endif /* __gio_defs_asm_h */

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#ifndef __pinmux_defs_asm_h
#define __pinmux_defs_asm_h
/*
* This file is autogenerated from
* file: pinmux.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_hwprot, scope pinmux, type rw */
#define reg_pinmux_rw_hwprot___eth___lsb 0
#define reg_pinmux_rw_hwprot___eth___width 1
#define reg_pinmux_rw_hwprot___eth___bit 0
#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1
#define reg_pinmux_rw_hwprot___eth_mdio___width 1
#define reg_pinmux_rw_hwprot___eth_mdio___bit 1
#define reg_pinmux_rw_hwprot___geth___lsb 2
#define reg_pinmux_rw_hwprot___geth___width 1
#define reg_pinmux_rw_hwprot___geth___bit 2
#define reg_pinmux_rw_hwprot___tg___lsb 3
#define reg_pinmux_rw_hwprot___tg___width 1
#define reg_pinmux_rw_hwprot___tg___bit 3
#define reg_pinmux_rw_hwprot___tg_clk___lsb 4
#define reg_pinmux_rw_hwprot___tg_clk___width 1
#define reg_pinmux_rw_hwprot___tg_clk___bit 4
#define reg_pinmux_rw_hwprot___vout___lsb 5
#define reg_pinmux_rw_hwprot___vout___width 1
#define reg_pinmux_rw_hwprot___vout___bit 5
#define reg_pinmux_rw_hwprot___vout_sync___lsb 6
#define reg_pinmux_rw_hwprot___vout_sync___width 1
#define reg_pinmux_rw_hwprot___vout_sync___bit 6
#define reg_pinmux_rw_hwprot___ser1___lsb 7
#define reg_pinmux_rw_hwprot___ser1___width 1
#define reg_pinmux_rw_hwprot___ser1___bit 7
#define reg_pinmux_rw_hwprot___ser2___lsb 8
#define reg_pinmux_rw_hwprot___ser2___width 1
#define reg_pinmux_rw_hwprot___ser2___bit 8
#define reg_pinmux_rw_hwprot___ser3___lsb 9
#define reg_pinmux_rw_hwprot___ser3___width 1
#define reg_pinmux_rw_hwprot___ser3___bit 9
#define reg_pinmux_rw_hwprot___ser4___lsb 10
#define reg_pinmux_rw_hwprot___ser4___width 1
#define reg_pinmux_rw_hwprot___ser4___bit 10
#define reg_pinmux_rw_hwprot___sser___lsb 11
#define reg_pinmux_rw_hwprot___sser___width 1
#define reg_pinmux_rw_hwprot___sser___bit 11
#define reg_pinmux_rw_hwprot___pwm0___lsb 12
#define reg_pinmux_rw_hwprot___pwm0___width 1
#define reg_pinmux_rw_hwprot___pwm0___bit 12
#define reg_pinmux_rw_hwprot___pwm1___lsb 13
#define reg_pinmux_rw_hwprot___pwm1___width 1
#define reg_pinmux_rw_hwprot___pwm1___bit 13
#define reg_pinmux_rw_hwprot___pwm2___lsb 14
#define reg_pinmux_rw_hwprot___pwm2___width 1
#define reg_pinmux_rw_hwprot___pwm2___bit 14
#define reg_pinmux_rw_hwprot___timer0___lsb 15
#define reg_pinmux_rw_hwprot___timer0___width 1
#define reg_pinmux_rw_hwprot___timer0___bit 15
#define reg_pinmux_rw_hwprot___timer1___lsb 16
#define reg_pinmux_rw_hwprot___timer1___width 1
#define reg_pinmux_rw_hwprot___timer1___bit 16
#define reg_pinmux_rw_hwprot___pio___lsb 17
#define reg_pinmux_rw_hwprot___pio___width 1
#define reg_pinmux_rw_hwprot___pio___bit 17
#define reg_pinmux_rw_hwprot___i2c0___lsb 18
#define reg_pinmux_rw_hwprot___i2c0___width 1
#define reg_pinmux_rw_hwprot___i2c0___bit 18
#define reg_pinmux_rw_hwprot___i2c1___lsb 19
#define reg_pinmux_rw_hwprot___i2c1___width 1
#define reg_pinmux_rw_hwprot___i2c1___bit 19
#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20
#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1
#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20
#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21
#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1
#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21
#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22
#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1
#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22
#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23
#define reg_pinmux_rw_hwprot___i2c1_sen___width 1
#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23
#define reg_pinmux_rw_hwprot_offset 0
/* Register rw_gio_pa, scope pinmux, type rw */
#define reg_pinmux_rw_gio_pa___pa0___lsb 0
#define reg_pinmux_rw_gio_pa___pa0___width 1
#define reg_pinmux_rw_gio_pa___pa0___bit 0
#define reg_pinmux_rw_gio_pa___pa1___lsb 1
#define reg_pinmux_rw_gio_pa___pa1___width 1
#define reg_pinmux_rw_gio_pa___pa1___bit 1
#define reg_pinmux_rw_gio_pa___pa2___lsb 2
#define reg_pinmux_rw_gio_pa___pa2___width 1
#define reg_pinmux_rw_gio_pa___pa2___bit 2
#define reg_pinmux_rw_gio_pa___pa3___lsb 3
#define reg_pinmux_rw_gio_pa___pa3___width 1
#define reg_pinmux_rw_gio_pa___pa3___bit 3
#define reg_pinmux_rw_gio_pa___pa4___lsb 4
#define reg_pinmux_rw_gio_pa___pa4___width 1
#define reg_pinmux_rw_gio_pa___pa4___bit 4
#define reg_pinmux_rw_gio_pa___pa5___lsb 5
#define reg_pinmux_rw_gio_pa___pa5___width 1
#define reg_pinmux_rw_gio_pa___pa5___bit 5
#define reg_pinmux_rw_gio_pa___pa6___lsb 6
#define reg_pinmux_rw_gio_pa___pa6___width 1
#define reg_pinmux_rw_gio_pa___pa6___bit 6
#define reg_pinmux_rw_gio_pa___pa7___lsb 7
#define reg_pinmux_rw_gio_pa___pa7___width 1
#define reg_pinmux_rw_gio_pa___pa7___bit 7
#define reg_pinmux_rw_gio_pa___pa8___lsb 8
#define reg_pinmux_rw_gio_pa___pa8___width 1
#define reg_pinmux_rw_gio_pa___pa8___bit 8
#define reg_pinmux_rw_gio_pa___pa9___lsb 9
#define reg_pinmux_rw_gio_pa___pa9___width 1
#define reg_pinmux_rw_gio_pa___pa9___bit 9
#define reg_pinmux_rw_gio_pa___pa10___lsb 10
#define reg_pinmux_rw_gio_pa___pa10___width 1
#define reg_pinmux_rw_gio_pa___pa10___bit 10
#define reg_pinmux_rw_gio_pa___pa11___lsb 11
#define reg_pinmux_rw_gio_pa___pa11___width 1
#define reg_pinmux_rw_gio_pa___pa11___bit 11
#define reg_pinmux_rw_gio_pa___pa12___lsb 12
#define reg_pinmux_rw_gio_pa___pa12___width 1
#define reg_pinmux_rw_gio_pa___pa12___bit 12
#define reg_pinmux_rw_gio_pa___pa13___lsb 13
#define reg_pinmux_rw_gio_pa___pa13___width 1
#define reg_pinmux_rw_gio_pa___pa13___bit 13
#define reg_pinmux_rw_gio_pa___pa14___lsb 14
#define reg_pinmux_rw_gio_pa___pa14___width 1
#define reg_pinmux_rw_gio_pa___pa14___bit 14
#define reg_pinmux_rw_gio_pa___pa15___lsb 15
#define reg_pinmux_rw_gio_pa___pa15___width 1
#define reg_pinmux_rw_gio_pa___pa15___bit 15
#define reg_pinmux_rw_gio_pa___pa16___lsb 16
#define reg_pinmux_rw_gio_pa___pa16___width 1
#define reg_pinmux_rw_gio_pa___pa16___bit 16
#define reg_pinmux_rw_gio_pa___pa17___lsb 17
#define reg_pinmux_rw_gio_pa___pa17___width 1
#define reg_pinmux_rw_gio_pa___pa17___bit 17
#define reg_pinmux_rw_gio_pa___pa18___lsb 18
#define reg_pinmux_rw_gio_pa___pa18___width 1
#define reg_pinmux_rw_gio_pa___pa18___bit 18
#define reg_pinmux_rw_gio_pa___pa19___lsb 19
#define reg_pinmux_rw_gio_pa___pa19___width 1
#define reg_pinmux_rw_gio_pa___pa19___bit 19
#define reg_pinmux_rw_gio_pa___pa20___lsb 20
#define reg_pinmux_rw_gio_pa___pa20___width 1
#define reg_pinmux_rw_gio_pa___pa20___bit 20
#define reg_pinmux_rw_gio_pa___pa21___lsb 21
#define reg_pinmux_rw_gio_pa___pa21___width 1
#define reg_pinmux_rw_gio_pa___pa21___bit 21
#define reg_pinmux_rw_gio_pa___pa22___lsb 22
#define reg_pinmux_rw_gio_pa___pa22___width 1
#define reg_pinmux_rw_gio_pa___pa22___bit 22
#define reg_pinmux_rw_gio_pa___pa23___lsb 23
#define reg_pinmux_rw_gio_pa___pa23___width 1
#define reg_pinmux_rw_gio_pa___pa23___bit 23
#define reg_pinmux_rw_gio_pa___pa24___lsb 24
#define reg_pinmux_rw_gio_pa___pa24___width 1
#define reg_pinmux_rw_gio_pa___pa24___bit 24
#define reg_pinmux_rw_gio_pa___pa25___lsb 25
#define reg_pinmux_rw_gio_pa___pa25___width 1
#define reg_pinmux_rw_gio_pa___pa25___bit 25
#define reg_pinmux_rw_gio_pa___pa26___lsb 26
#define reg_pinmux_rw_gio_pa___pa26___width 1
#define reg_pinmux_rw_gio_pa___pa26___bit 26
#define reg_pinmux_rw_gio_pa___pa27___lsb 27
#define reg_pinmux_rw_gio_pa___pa27___width 1
#define reg_pinmux_rw_gio_pa___pa27___bit 27
#define reg_pinmux_rw_gio_pa___pa28___lsb 28
#define reg_pinmux_rw_gio_pa___pa28___width 1
#define reg_pinmux_rw_gio_pa___pa28___bit 28
#define reg_pinmux_rw_gio_pa___pa29___lsb 29
#define reg_pinmux_rw_gio_pa___pa29___width 1
#define reg_pinmux_rw_gio_pa___pa29___bit 29
#define reg_pinmux_rw_gio_pa___pa30___lsb 30
#define reg_pinmux_rw_gio_pa___pa30___width 1
#define reg_pinmux_rw_gio_pa___pa30___bit 30
#define reg_pinmux_rw_gio_pa___pa31___lsb 31
#define reg_pinmux_rw_gio_pa___pa31___width 1
#define reg_pinmux_rw_gio_pa___pa31___bit 31
#define reg_pinmux_rw_gio_pa_offset 4
/* Register rw_gio_pb, scope pinmux, type rw */
#define reg_pinmux_rw_gio_pb___pb0___lsb 0
#define reg_pinmux_rw_gio_pb___pb0___width 1
#define reg_pinmux_rw_gio_pb___pb0___bit 0
#define reg_pinmux_rw_gio_pb___pb1___lsb 1
#define reg_pinmux_rw_gio_pb___pb1___width 1
#define reg_pinmux_rw_gio_pb___pb1___bit 1
#define reg_pinmux_rw_gio_pb___pb2___lsb 2
#define reg_pinmux_rw_gio_pb___pb2___width 1
#define reg_pinmux_rw_gio_pb___pb2___bit 2
#define reg_pinmux_rw_gio_pb___pb3___lsb 3
#define reg_pinmux_rw_gio_pb___pb3___width 1
#define reg_pinmux_rw_gio_pb___pb3___bit 3
#define reg_pinmux_rw_gio_pb___pb4___lsb 4
#define reg_pinmux_rw_gio_pb___pb4___width 1
#define reg_pinmux_rw_gio_pb___pb4___bit 4
#define reg_pinmux_rw_gio_pb___pb5___lsb 5
#define reg_pinmux_rw_gio_pb___pb5___width 1
#define reg_pinmux_rw_gio_pb___pb5___bit 5
#define reg_pinmux_rw_gio_pb___pb6___lsb 6
#define reg_pinmux_rw_gio_pb___pb6___width 1
#define reg_pinmux_rw_gio_pb___pb6___bit 6
#define reg_pinmux_rw_gio_pb___pb7___lsb 7
#define reg_pinmux_rw_gio_pb___pb7___width 1
#define reg_pinmux_rw_gio_pb___pb7___bit 7
#define reg_pinmux_rw_gio_pb___pb8___lsb 8
#define reg_pinmux_rw_gio_pb___pb8___width 1
#define reg_pinmux_rw_gio_pb___pb8___bit 8
#define reg_pinmux_rw_gio_pb___pb9___lsb 9
#define reg_pinmux_rw_gio_pb___pb9___width 1
#define reg_pinmux_rw_gio_pb___pb9___bit 9
#define reg_pinmux_rw_gio_pb___pb10___lsb 10
#define reg_pinmux_rw_gio_pb___pb10___width 1
#define reg_pinmux_rw_gio_pb___pb10___bit 10
#define reg_pinmux_rw_gio_pb___pb11___lsb 11
#define reg_pinmux_rw_gio_pb___pb11___width 1
#define reg_pinmux_rw_gio_pb___pb11___bit 11
#define reg_pinmux_rw_gio_pb___pb12___lsb 12
#define reg_pinmux_rw_gio_pb___pb12___width 1
#define reg_pinmux_rw_gio_pb___pb12___bit 12
#define reg_pinmux_rw_gio_pb___pb13___lsb 13
#define reg_pinmux_rw_gio_pb___pb13___width 1
#define reg_pinmux_rw_gio_pb___pb13___bit 13
#define reg_pinmux_rw_gio_pb___pb14___lsb 14
#define reg_pinmux_rw_gio_pb___pb14___width 1
#define reg_pinmux_rw_gio_pb___pb14___bit 14
#define reg_pinmux_rw_gio_pb___pb15___lsb 15
#define reg_pinmux_rw_gio_pb___pb15___width 1
#define reg_pinmux_rw_gio_pb___pb15___bit 15
#define reg_pinmux_rw_gio_pb___pb16___lsb 16
#define reg_pinmux_rw_gio_pb___pb16___width 1
#define reg_pinmux_rw_gio_pb___pb16___bit 16
#define reg_pinmux_rw_gio_pb___pb17___lsb 17
#define reg_pinmux_rw_gio_pb___pb17___width 1
#define reg_pinmux_rw_gio_pb___pb17___bit 17
#define reg_pinmux_rw_gio_pb___pb18___lsb 18
#define reg_pinmux_rw_gio_pb___pb18___width 1
#define reg_pinmux_rw_gio_pb___pb18___bit 18
#define reg_pinmux_rw_gio_pb___pb19___lsb 19
#define reg_pinmux_rw_gio_pb___pb19___width 1
#define reg_pinmux_rw_gio_pb___pb19___bit 19
#define reg_pinmux_rw_gio_pb___pb20___lsb 20
#define reg_pinmux_rw_gio_pb___pb20___width 1
#define reg_pinmux_rw_gio_pb___pb20___bit 20
#define reg_pinmux_rw_gio_pb___pb21___lsb 21
#define reg_pinmux_rw_gio_pb___pb21___width 1
#define reg_pinmux_rw_gio_pb___pb21___bit 21
#define reg_pinmux_rw_gio_pb___pb22___lsb 22
#define reg_pinmux_rw_gio_pb___pb22___width 1
#define reg_pinmux_rw_gio_pb___pb22___bit 22
#define reg_pinmux_rw_gio_pb___pb23___lsb 23
#define reg_pinmux_rw_gio_pb___pb23___width 1
#define reg_pinmux_rw_gio_pb___pb23___bit 23
#define reg_pinmux_rw_gio_pb___pb24___lsb 24
#define reg_pinmux_rw_gio_pb___pb24___width 1
#define reg_pinmux_rw_gio_pb___pb24___bit 24
#define reg_pinmux_rw_gio_pb___pb25___lsb 25
#define reg_pinmux_rw_gio_pb___pb25___width 1
#define reg_pinmux_rw_gio_pb___pb25___bit 25
#define reg_pinmux_rw_gio_pb___pb26___lsb 26
#define reg_pinmux_rw_gio_pb___pb26___width 1
#define reg_pinmux_rw_gio_pb___pb26___bit 26
#define reg_pinmux_rw_gio_pb___pb27___lsb 27
#define reg_pinmux_rw_gio_pb___pb27___width 1
#define reg_pinmux_rw_gio_pb___pb27___bit 27
#define reg_pinmux_rw_gio_pb___pb28___lsb 28
#define reg_pinmux_rw_gio_pb___pb28___width 1
#define reg_pinmux_rw_gio_pb___pb28___bit 28
#define reg_pinmux_rw_gio_pb___pb29___lsb 29
#define reg_pinmux_rw_gio_pb___pb29___width 1
#define reg_pinmux_rw_gio_pb___pb29___bit 29
#define reg_pinmux_rw_gio_pb___pb30___lsb 30
#define reg_pinmux_rw_gio_pb___pb30___width 1
#define reg_pinmux_rw_gio_pb___pb30___bit 30
#define reg_pinmux_rw_gio_pb___pb31___lsb 31
#define reg_pinmux_rw_gio_pb___pb31___width 1
#define reg_pinmux_rw_gio_pb___pb31___bit 31
#define reg_pinmux_rw_gio_pb_offset 8
/* Register rw_gio_pc, scope pinmux, type rw */
#define reg_pinmux_rw_gio_pc___pc0___lsb 0
#define reg_pinmux_rw_gio_pc___pc0___width 1
#define reg_pinmux_rw_gio_pc___pc0___bit 0
#define reg_pinmux_rw_gio_pc___pc1___lsb 1
#define reg_pinmux_rw_gio_pc___pc1___width 1
#define reg_pinmux_rw_gio_pc___pc1___bit 1
#define reg_pinmux_rw_gio_pc___pc2___lsb 2
#define reg_pinmux_rw_gio_pc___pc2___width 1
#define reg_pinmux_rw_gio_pc___pc2___bit 2
#define reg_pinmux_rw_gio_pc___pc3___lsb 3
#define reg_pinmux_rw_gio_pc___pc3___width 1
#define reg_pinmux_rw_gio_pc___pc3___bit 3
#define reg_pinmux_rw_gio_pc___pc4___lsb 4
#define reg_pinmux_rw_gio_pc___pc4___width 1
#define reg_pinmux_rw_gio_pc___pc4___bit 4
#define reg_pinmux_rw_gio_pc___pc5___lsb 5
#define reg_pinmux_rw_gio_pc___pc5___width 1
#define reg_pinmux_rw_gio_pc___pc5___bit 5
#define reg_pinmux_rw_gio_pc___pc6___lsb 6
#define reg_pinmux_rw_gio_pc___pc6___width 1
#define reg_pinmux_rw_gio_pc___pc6___bit 6
#define reg_pinmux_rw_gio_pc___pc7___lsb 7
#define reg_pinmux_rw_gio_pc___pc7___width 1
#define reg_pinmux_rw_gio_pc___pc7___bit 7
#define reg_pinmux_rw_gio_pc___pc8___lsb 8
#define reg_pinmux_rw_gio_pc___pc8___width 1
#define reg_pinmux_rw_gio_pc___pc8___bit 8
#define reg_pinmux_rw_gio_pc___pc9___lsb 9
#define reg_pinmux_rw_gio_pc___pc9___width 1
#define reg_pinmux_rw_gio_pc___pc9___bit 9
#define reg_pinmux_rw_gio_pc___pc10___lsb 10
#define reg_pinmux_rw_gio_pc___pc10___width 1
#define reg_pinmux_rw_gio_pc___pc10___bit 10
#define reg_pinmux_rw_gio_pc___pc11___lsb 11
#define reg_pinmux_rw_gio_pc___pc11___width 1
#define reg_pinmux_rw_gio_pc___pc11___bit 11
#define reg_pinmux_rw_gio_pc___pc12___lsb 12
#define reg_pinmux_rw_gio_pc___pc12___width 1
#define reg_pinmux_rw_gio_pc___pc12___bit 12
#define reg_pinmux_rw_gio_pc___pc13___lsb 13
#define reg_pinmux_rw_gio_pc___pc13___width 1
#define reg_pinmux_rw_gio_pc___pc13___bit 13
#define reg_pinmux_rw_gio_pc___pc14___lsb 14
#define reg_pinmux_rw_gio_pc___pc14___width 1
#define reg_pinmux_rw_gio_pc___pc14___bit 14
#define reg_pinmux_rw_gio_pc___pc15___lsb 15
#define reg_pinmux_rw_gio_pc___pc15___width 1
#define reg_pinmux_rw_gio_pc___pc15___bit 15
#define reg_pinmux_rw_gio_pc_offset 12
/* Register rw_iop_pa, scope pinmux, type rw */
#define reg_pinmux_rw_iop_pa___pa0___lsb 0
#define reg_pinmux_rw_iop_pa___pa0___width 1
#define reg_pinmux_rw_iop_pa___pa0___bit 0
#define reg_pinmux_rw_iop_pa___pa1___lsb 1
#define reg_pinmux_rw_iop_pa___pa1___width 1
#define reg_pinmux_rw_iop_pa___pa1___bit 1
#define reg_pinmux_rw_iop_pa___pa2___lsb 2
#define reg_pinmux_rw_iop_pa___pa2___width 1
#define reg_pinmux_rw_iop_pa___pa2___bit 2
#define reg_pinmux_rw_iop_pa___pa3___lsb 3
#define reg_pinmux_rw_iop_pa___pa3___width 1
#define reg_pinmux_rw_iop_pa___pa3___bit 3
#define reg_pinmux_rw_iop_pa___pa4___lsb 4
#define reg_pinmux_rw_iop_pa___pa4___width 1
#define reg_pinmux_rw_iop_pa___pa4___bit 4
#define reg_pinmux_rw_iop_pa___pa5___lsb 5
#define reg_pinmux_rw_iop_pa___pa5___width 1
#define reg_pinmux_rw_iop_pa___pa5___bit 5
#define reg_pinmux_rw_iop_pa___pa6___lsb 6
#define reg_pinmux_rw_iop_pa___pa6___width 1
#define reg_pinmux_rw_iop_pa___pa6___bit 6
#define reg_pinmux_rw_iop_pa___pa7___lsb 7
#define reg_pinmux_rw_iop_pa___pa7___width 1
#define reg_pinmux_rw_iop_pa___pa7___bit 7
#define reg_pinmux_rw_iop_pa___pa8___lsb 8
#define reg_pinmux_rw_iop_pa___pa8___width 1
#define reg_pinmux_rw_iop_pa___pa8___bit 8
#define reg_pinmux_rw_iop_pa___pa9___lsb 9
#define reg_pinmux_rw_iop_pa___pa9___width 1
#define reg_pinmux_rw_iop_pa___pa9___bit 9
#define reg_pinmux_rw_iop_pa___pa10___lsb 10
#define reg_pinmux_rw_iop_pa___pa10___width 1
#define reg_pinmux_rw_iop_pa___pa10___bit 10
#define reg_pinmux_rw_iop_pa___pa11___lsb 11
#define reg_pinmux_rw_iop_pa___pa11___width 1
#define reg_pinmux_rw_iop_pa___pa11___bit 11
#define reg_pinmux_rw_iop_pa___pa12___lsb 12
#define reg_pinmux_rw_iop_pa___pa12___width 1
#define reg_pinmux_rw_iop_pa___pa12___bit 12
#define reg_pinmux_rw_iop_pa___pa13___lsb 13
#define reg_pinmux_rw_iop_pa___pa13___width 1
#define reg_pinmux_rw_iop_pa___pa13___bit 13
#define reg_pinmux_rw_iop_pa___pa14___lsb 14
#define reg_pinmux_rw_iop_pa___pa14___width 1
#define reg_pinmux_rw_iop_pa___pa14___bit 14
#define reg_pinmux_rw_iop_pa___pa15___lsb 15
#define reg_pinmux_rw_iop_pa___pa15___width 1
#define reg_pinmux_rw_iop_pa___pa15___bit 15
#define reg_pinmux_rw_iop_pa___pa16___lsb 16
#define reg_pinmux_rw_iop_pa___pa16___width 1
#define reg_pinmux_rw_iop_pa___pa16___bit 16
#define reg_pinmux_rw_iop_pa___pa17___lsb 17
#define reg_pinmux_rw_iop_pa___pa17___width 1
#define reg_pinmux_rw_iop_pa___pa17___bit 17
#define reg_pinmux_rw_iop_pa___pa18___lsb 18
#define reg_pinmux_rw_iop_pa___pa18___width 1
#define reg_pinmux_rw_iop_pa___pa18___bit 18
#define reg_pinmux_rw_iop_pa___pa19___lsb 19
#define reg_pinmux_rw_iop_pa___pa19___width 1
#define reg_pinmux_rw_iop_pa___pa19___bit 19
#define reg_pinmux_rw_iop_pa___pa20___lsb 20
#define reg_pinmux_rw_iop_pa___pa20___width 1
#define reg_pinmux_rw_iop_pa___pa20___bit 20
#define reg_pinmux_rw_iop_pa___pa21___lsb 21
#define reg_pinmux_rw_iop_pa___pa21___width 1
#define reg_pinmux_rw_iop_pa___pa21___bit 21
#define reg_pinmux_rw_iop_pa___pa22___lsb 22
#define reg_pinmux_rw_iop_pa___pa22___width 1
#define reg_pinmux_rw_iop_pa___pa22___bit 22
#define reg_pinmux_rw_iop_pa___pa23___lsb 23
#define reg_pinmux_rw_iop_pa___pa23___width 1
#define reg_pinmux_rw_iop_pa___pa23___bit 23
#define reg_pinmux_rw_iop_pa___pa24___lsb 24
#define reg_pinmux_rw_iop_pa___pa24___width 1
#define reg_pinmux_rw_iop_pa___pa24___bit 24
#define reg_pinmux_rw_iop_pa___pa25___lsb 25
#define reg_pinmux_rw_iop_pa___pa25___width 1
#define reg_pinmux_rw_iop_pa___pa25___bit 25
#define reg_pinmux_rw_iop_pa___pa26___lsb 26
#define reg_pinmux_rw_iop_pa___pa26___width 1
#define reg_pinmux_rw_iop_pa___pa26___bit 26
#define reg_pinmux_rw_iop_pa___pa27___lsb 27
#define reg_pinmux_rw_iop_pa___pa27___width 1
#define reg_pinmux_rw_iop_pa___pa27___bit 27
#define reg_pinmux_rw_iop_pa___pa28___lsb 28
#define reg_pinmux_rw_iop_pa___pa28___width 1
#define reg_pinmux_rw_iop_pa___pa28___bit 28
#define reg_pinmux_rw_iop_pa___pa29___lsb 29
#define reg_pinmux_rw_iop_pa___pa29___width 1
#define reg_pinmux_rw_iop_pa___pa29___bit 29
#define reg_pinmux_rw_iop_pa___pa30___lsb 30
#define reg_pinmux_rw_iop_pa___pa30___width 1
#define reg_pinmux_rw_iop_pa___pa30___bit 30
#define reg_pinmux_rw_iop_pa___pa31___lsb 31
#define reg_pinmux_rw_iop_pa___pa31___width 1
#define reg_pinmux_rw_iop_pa___pa31___bit 31
#define reg_pinmux_rw_iop_pa_offset 16
/* Register rw_iop_pb, scope pinmux, type rw */
#define reg_pinmux_rw_iop_pb___pb0___lsb 0
#define reg_pinmux_rw_iop_pb___pb0___width 1
#define reg_pinmux_rw_iop_pb___pb0___bit 0
#define reg_pinmux_rw_iop_pb___pb1___lsb 1
#define reg_pinmux_rw_iop_pb___pb1___width 1
#define reg_pinmux_rw_iop_pb___pb1___bit 1
#define reg_pinmux_rw_iop_pb___pb2___lsb 2
#define reg_pinmux_rw_iop_pb___pb2___width 1
#define reg_pinmux_rw_iop_pb___pb2___bit 2
#define reg_pinmux_rw_iop_pb___pb3___lsb 3
#define reg_pinmux_rw_iop_pb___pb3___width 1
#define reg_pinmux_rw_iop_pb___pb3___bit 3
#define reg_pinmux_rw_iop_pb___pb4___lsb 4
#define reg_pinmux_rw_iop_pb___pb4___width 1
#define reg_pinmux_rw_iop_pb___pb4___bit 4
#define reg_pinmux_rw_iop_pb___pb5___lsb 5
#define reg_pinmux_rw_iop_pb___pb5___width 1
#define reg_pinmux_rw_iop_pb___pb5___bit 5
#define reg_pinmux_rw_iop_pb___pb6___lsb 6
#define reg_pinmux_rw_iop_pb___pb6___width 1
#define reg_pinmux_rw_iop_pb___pb6___bit 6
#define reg_pinmux_rw_iop_pb___pb7___lsb 7
#define reg_pinmux_rw_iop_pb___pb7___width 1
#define reg_pinmux_rw_iop_pb___pb7___bit 7
#define reg_pinmux_rw_iop_pb_offset 20
/* Register rw_iop_pio, scope pinmux, type rw */
#define reg_pinmux_rw_iop_pio___d0___lsb 0
#define reg_pinmux_rw_iop_pio___d0___width 1
#define reg_pinmux_rw_iop_pio___d0___bit 0
#define reg_pinmux_rw_iop_pio___d1___lsb 1
#define reg_pinmux_rw_iop_pio___d1___width 1
#define reg_pinmux_rw_iop_pio___d1___bit 1
#define reg_pinmux_rw_iop_pio___d2___lsb 2
#define reg_pinmux_rw_iop_pio___d2___width 1
#define reg_pinmux_rw_iop_pio___d2___bit 2
#define reg_pinmux_rw_iop_pio___d3___lsb 3
#define reg_pinmux_rw_iop_pio___d3___width 1
#define reg_pinmux_rw_iop_pio___d3___bit 3
#define reg_pinmux_rw_iop_pio___d4___lsb 4
#define reg_pinmux_rw_iop_pio___d4___width 1
#define reg_pinmux_rw_iop_pio___d4___bit 4
#define reg_pinmux_rw_iop_pio___d5___lsb 5
#define reg_pinmux_rw_iop_pio___d5___width 1
#define reg_pinmux_rw_iop_pio___d5___bit 5
#define reg_pinmux_rw_iop_pio___d6___lsb 6
#define reg_pinmux_rw_iop_pio___d6___width 1
#define reg_pinmux_rw_iop_pio___d6___bit 6
#define reg_pinmux_rw_iop_pio___d7___lsb 7
#define reg_pinmux_rw_iop_pio___d7___width 1
#define reg_pinmux_rw_iop_pio___d7___bit 7
#define reg_pinmux_rw_iop_pio___rd_n___lsb 8
#define reg_pinmux_rw_iop_pio___rd_n___width 1
#define reg_pinmux_rw_iop_pio___rd_n___bit 8
#define reg_pinmux_rw_iop_pio___wr_n___lsb 9
#define reg_pinmux_rw_iop_pio___wr_n___width 1
#define reg_pinmux_rw_iop_pio___wr_n___bit 9
#define reg_pinmux_rw_iop_pio___a0___lsb 10
#define reg_pinmux_rw_iop_pio___a0___width 1
#define reg_pinmux_rw_iop_pio___a0___bit 10
#define reg_pinmux_rw_iop_pio___a1___lsb 11
#define reg_pinmux_rw_iop_pio___a1___width 1
#define reg_pinmux_rw_iop_pio___a1___bit 11
#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12
#define reg_pinmux_rw_iop_pio___ce0_n___width 1
#define reg_pinmux_rw_iop_pio___ce0_n___bit 12
#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13
#define reg_pinmux_rw_iop_pio___ce1_n___width 1
#define reg_pinmux_rw_iop_pio___ce1_n___bit 13
#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14
#define reg_pinmux_rw_iop_pio___ce2_n___width 1
#define reg_pinmux_rw_iop_pio___ce2_n___bit 14
#define reg_pinmux_rw_iop_pio___rdy___lsb 15
#define reg_pinmux_rw_iop_pio___rdy___width 1
#define reg_pinmux_rw_iop_pio___rdy___bit 15
#define reg_pinmux_rw_iop_pio_offset 24
/* Register rw_iop_usb, scope pinmux, type rw */
#define reg_pinmux_rw_iop_usb___usb0___lsb 0
#define reg_pinmux_rw_iop_usb___usb0___width 1
#define reg_pinmux_rw_iop_usb___usb0___bit 0
#define reg_pinmux_rw_iop_usb_offset 28
/* Constants */
#define regk_pinmux_no 0x00000000
#define regk_pinmux_rw_gio_pa_default 0x00000000
#define regk_pinmux_rw_gio_pb_default 0x00000000
#define regk_pinmux_rw_gio_pc_default 0x00000000
#define regk_pinmux_rw_hwprot_default 0x00000000
#define regk_pinmux_rw_iop_pa_default 0x00000000
#define regk_pinmux_rw_iop_pb_default 0x00000000
#define regk_pinmux_rw_iop_pio_default 0x00000000
#define regk_pinmux_rw_iop_usb_default 0x00000001
#define regk_pinmux_yes 0x00000001
#endif /* __pinmux_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h Normal file
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#ifndef __pio_defs_asm_h
#define __pio_defs_asm_h
/*
* This file is autogenerated from
* file: pio.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_data, scope pio, type rw */
#define reg_pio_rw_data_offset 64
/* Register rw_io_access0, scope pio, type rw */
#define reg_pio_rw_io_access0___data___lsb 0
#define reg_pio_rw_io_access0___data___width 8
#define reg_pio_rw_io_access0_offset 0
/* Register rw_io_access1, scope pio, type rw */
#define reg_pio_rw_io_access1___data___lsb 0
#define reg_pio_rw_io_access1___data___width 8
#define reg_pio_rw_io_access1_offset 4
/* Register rw_io_access2, scope pio, type rw */
#define reg_pio_rw_io_access2___data___lsb 0
#define reg_pio_rw_io_access2___data___width 8
#define reg_pio_rw_io_access2_offset 8
/* Register rw_io_access3, scope pio, type rw */
#define reg_pio_rw_io_access3___data___lsb 0
#define reg_pio_rw_io_access3___data___width 8
#define reg_pio_rw_io_access3_offset 12
/* Register rw_io_access4, scope pio, type rw */
#define reg_pio_rw_io_access4___data___lsb 0
#define reg_pio_rw_io_access4___data___width 8
#define reg_pio_rw_io_access4_offset 16
/* Register rw_io_access5, scope pio, type rw */
#define reg_pio_rw_io_access5___data___lsb 0
#define reg_pio_rw_io_access5___data___width 8
#define reg_pio_rw_io_access5_offset 20
/* Register rw_io_access6, scope pio, type rw */
#define reg_pio_rw_io_access6___data___lsb 0
#define reg_pio_rw_io_access6___data___width 8
#define reg_pio_rw_io_access6_offset 24
/* Register rw_io_access7, scope pio, type rw */
#define reg_pio_rw_io_access7___data___lsb 0
#define reg_pio_rw_io_access7___data___width 8
#define reg_pio_rw_io_access7_offset 28
/* Register rw_io_access8, scope pio, type rw */
#define reg_pio_rw_io_access8___data___lsb 0
#define reg_pio_rw_io_access8___data___width 8
#define reg_pio_rw_io_access8_offset 32
/* Register rw_io_access9, scope pio, type rw */
#define reg_pio_rw_io_access9___data___lsb 0
#define reg_pio_rw_io_access9___data___width 8
#define reg_pio_rw_io_access9_offset 36
/* Register rw_io_access10, scope pio, type rw */
#define reg_pio_rw_io_access10___data___lsb 0
#define reg_pio_rw_io_access10___data___width 8
#define reg_pio_rw_io_access10_offset 40
/* Register rw_io_access11, scope pio, type rw */
#define reg_pio_rw_io_access11___data___lsb 0
#define reg_pio_rw_io_access11___data___width 8
#define reg_pio_rw_io_access11_offset 44
/* Register rw_io_access12, scope pio, type rw */
#define reg_pio_rw_io_access12___data___lsb 0
#define reg_pio_rw_io_access12___data___width 8
#define reg_pio_rw_io_access12_offset 48
/* Register rw_io_access13, scope pio, type rw */
#define reg_pio_rw_io_access13___data___lsb 0
#define reg_pio_rw_io_access13___data___width 8
#define reg_pio_rw_io_access13_offset 52
/* Register rw_io_access14, scope pio, type rw */
#define reg_pio_rw_io_access14___data___lsb 0
#define reg_pio_rw_io_access14___data___width 8
#define reg_pio_rw_io_access14_offset 56
/* Register rw_io_access15, scope pio, type rw */
#define reg_pio_rw_io_access15___data___lsb 0
#define reg_pio_rw_io_access15___data___width 8
#define reg_pio_rw_io_access15_offset 60
/* Register rw_ce0_cfg, scope pio, type rw */
#define reg_pio_rw_ce0_cfg___lw___lsb 0
#define reg_pio_rw_ce0_cfg___lw___width 6
#define reg_pio_rw_ce0_cfg___ew___lsb 6
#define reg_pio_rw_ce0_cfg___ew___width 3
#define reg_pio_rw_ce0_cfg___zw___lsb 9
#define reg_pio_rw_ce0_cfg___zw___width 3
#define reg_pio_rw_ce0_cfg___aw___lsb 12
#define reg_pio_rw_ce0_cfg___aw___width 2
#define reg_pio_rw_ce0_cfg___mode___lsb 14
#define reg_pio_rw_ce0_cfg___mode___width 2
#define reg_pio_rw_ce0_cfg_offset 68
/* Register rw_ce1_cfg, scope pio, type rw */
#define reg_pio_rw_ce1_cfg___lw___lsb 0
#define reg_pio_rw_ce1_cfg___lw___width 6
#define reg_pio_rw_ce1_cfg___ew___lsb 6
#define reg_pio_rw_ce1_cfg___ew___width 3
#define reg_pio_rw_ce1_cfg___zw___lsb 9
#define reg_pio_rw_ce1_cfg___zw___width 3
#define reg_pio_rw_ce1_cfg___aw___lsb 12
#define reg_pio_rw_ce1_cfg___aw___width 2
#define reg_pio_rw_ce1_cfg___mode___lsb 14
#define reg_pio_rw_ce1_cfg___mode___width 2
#define reg_pio_rw_ce1_cfg_offset 72
/* Register rw_ce2_cfg, scope pio, type rw */
#define reg_pio_rw_ce2_cfg___lw___lsb 0
#define reg_pio_rw_ce2_cfg___lw___width 6
#define reg_pio_rw_ce2_cfg___ew___lsb 6
#define reg_pio_rw_ce2_cfg___ew___width 3
#define reg_pio_rw_ce2_cfg___zw___lsb 9
#define reg_pio_rw_ce2_cfg___zw___width 3
#define reg_pio_rw_ce2_cfg___aw___lsb 12
#define reg_pio_rw_ce2_cfg___aw___width 2
#define reg_pio_rw_ce2_cfg___mode___lsb 14
#define reg_pio_rw_ce2_cfg___mode___width 2
#define reg_pio_rw_ce2_cfg_offset 76
/* Register rw_dout, scope pio, type rw */
#define reg_pio_rw_dout___data___lsb 0
#define reg_pio_rw_dout___data___width 8
#define reg_pio_rw_dout___rd_n___lsb 8
#define reg_pio_rw_dout___rd_n___width 1
#define reg_pio_rw_dout___rd_n___bit 8
#define reg_pio_rw_dout___wr_n___lsb 9
#define reg_pio_rw_dout___wr_n___width 1
#define reg_pio_rw_dout___wr_n___bit 9
#define reg_pio_rw_dout___a0___lsb 10
#define reg_pio_rw_dout___a0___width 1
#define reg_pio_rw_dout___a0___bit 10
#define reg_pio_rw_dout___a1___lsb 11
#define reg_pio_rw_dout___a1___width 1
#define reg_pio_rw_dout___a1___bit 11
#define reg_pio_rw_dout___ce0_n___lsb 12
#define reg_pio_rw_dout___ce0_n___width 1
#define reg_pio_rw_dout___ce0_n___bit 12
#define reg_pio_rw_dout___ce1_n___lsb 13
#define reg_pio_rw_dout___ce1_n___width 1
#define reg_pio_rw_dout___ce1_n___bit 13
#define reg_pio_rw_dout___ce2_n___lsb 14
#define reg_pio_rw_dout___ce2_n___width 1
#define reg_pio_rw_dout___ce2_n___bit 14
#define reg_pio_rw_dout___rdy___lsb 15
#define reg_pio_rw_dout___rdy___width 1
#define reg_pio_rw_dout___rdy___bit 15
#define reg_pio_rw_dout_offset 80
/* Register rw_oe, scope pio, type rw */
#define reg_pio_rw_oe___data___lsb 0
#define reg_pio_rw_oe___data___width 8
#define reg_pio_rw_oe___rd_n___lsb 8
#define reg_pio_rw_oe___rd_n___width 1
#define reg_pio_rw_oe___rd_n___bit 8
#define reg_pio_rw_oe___wr_n___lsb 9
#define reg_pio_rw_oe___wr_n___width 1
#define reg_pio_rw_oe___wr_n___bit 9
#define reg_pio_rw_oe___a0___lsb 10
#define reg_pio_rw_oe___a0___width 1
#define reg_pio_rw_oe___a0___bit 10
#define reg_pio_rw_oe___a1___lsb 11
#define reg_pio_rw_oe___a1___width 1
#define reg_pio_rw_oe___a1___bit 11
#define reg_pio_rw_oe___ce0_n___lsb 12
#define reg_pio_rw_oe___ce0_n___width 1
#define reg_pio_rw_oe___ce0_n___bit 12
#define reg_pio_rw_oe___ce1_n___lsb 13
#define reg_pio_rw_oe___ce1_n___width 1
#define reg_pio_rw_oe___ce1_n___bit 13
#define reg_pio_rw_oe___ce2_n___lsb 14
#define reg_pio_rw_oe___ce2_n___width 1
#define reg_pio_rw_oe___ce2_n___bit 14
#define reg_pio_rw_oe___rdy___lsb 15
#define reg_pio_rw_oe___rdy___width 1
#define reg_pio_rw_oe___rdy___bit 15
#define reg_pio_rw_oe_offset 84
/* Register rw_man_ctrl, scope pio, type rw */
#define reg_pio_rw_man_ctrl___data___lsb 0
#define reg_pio_rw_man_ctrl___data___width 8
#define reg_pio_rw_man_ctrl___rd_n___lsb 8
#define reg_pio_rw_man_ctrl___rd_n___width 1
#define reg_pio_rw_man_ctrl___rd_n___bit 8
#define reg_pio_rw_man_ctrl___wr_n___lsb 9
#define reg_pio_rw_man_ctrl___wr_n___width 1
#define reg_pio_rw_man_ctrl___wr_n___bit 9
#define reg_pio_rw_man_ctrl___a0___lsb 10
#define reg_pio_rw_man_ctrl___a0___width 1
#define reg_pio_rw_man_ctrl___a0___bit 10
#define reg_pio_rw_man_ctrl___a1___lsb 11
#define reg_pio_rw_man_ctrl___a1___width 1
#define reg_pio_rw_man_ctrl___a1___bit 11
#define reg_pio_rw_man_ctrl___ce0_n___lsb 12
#define reg_pio_rw_man_ctrl___ce0_n___width 1
#define reg_pio_rw_man_ctrl___ce0_n___bit 12
#define reg_pio_rw_man_ctrl___ce1_n___lsb 13
#define reg_pio_rw_man_ctrl___ce1_n___width 1
#define reg_pio_rw_man_ctrl___ce1_n___bit 13
#define reg_pio_rw_man_ctrl___ce2_n___lsb 14
#define reg_pio_rw_man_ctrl___ce2_n___width 1
#define reg_pio_rw_man_ctrl___ce2_n___bit 14
#define reg_pio_rw_man_ctrl___rdy___lsb 15
#define reg_pio_rw_man_ctrl___rdy___width 1
#define reg_pio_rw_man_ctrl___rdy___bit 15
#define reg_pio_rw_man_ctrl_offset 88
/* Register r_din, scope pio, type r */
#define reg_pio_r_din___data___lsb 0
#define reg_pio_r_din___data___width 8
#define reg_pio_r_din___rd_n___lsb 8
#define reg_pio_r_din___rd_n___width 1
#define reg_pio_r_din___rd_n___bit 8
#define reg_pio_r_din___wr_n___lsb 9
#define reg_pio_r_din___wr_n___width 1
#define reg_pio_r_din___wr_n___bit 9
#define reg_pio_r_din___a0___lsb 10
#define reg_pio_r_din___a0___width 1
#define reg_pio_r_din___a0___bit 10
#define reg_pio_r_din___a1___lsb 11
#define reg_pio_r_din___a1___width 1
#define reg_pio_r_din___a1___bit 11
#define reg_pio_r_din___ce0_n___lsb 12
#define reg_pio_r_din___ce0_n___width 1
#define reg_pio_r_din___ce0_n___bit 12
#define reg_pio_r_din___ce1_n___lsb 13
#define reg_pio_r_din___ce1_n___width 1
#define reg_pio_r_din___ce1_n___bit 13
#define reg_pio_r_din___ce2_n___lsb 14
#define reg_pio_r_din___ce2_n___width 1
#define reg_pio_r_din___ce2_n___bit 14
#define reg_pio_r_din___rdy___lsb 15
#define reg_pio_r_din___rdy___width 1
#define reg_pio_r_din___rdy___bit 15
#define reg_pio_r_din_offset 92
/* Register r_stat, scope pio, type r */
#define reg_pio_r_stat___busy___lsb 0
#define reg_pio_r_stat___busy___width 1
#define reg_pio_r_stat___busy___bit 0
#define reg_pio_r_stat_offset 96
/* Register rw_intr_mask, scope pio, type rw */
#define reg_pio_rw_intr_mask___rdy___lsb 0
#define reg_pio_rw_intr_mask___rdy___width 1
#define reg_pio_rw_intr_mask___rdy___bit 0
#define reg_pio_rw_intr_mask_offset 100
/* Register rw_ack_intr, scope pio, type rw */
#define reg_pio_rw_ack_intr___rdy___lsb 0
#define reg_pio_rw_ack_intr___rdy___width 1
#define reg_pio_rw_ack_intr___rdy___bit 0
#define reg_pio_rw_ack_intr_offset 104
/* Register r_intr, scope pio, type r */
#define reg_pio_r_intr___rdy___lsb 0
#define reg_pio_r_intr___rdy___width 1
#define reg_pio_r_intr___rdy___bit 0
#define reg_pio_r_intr_offset 108
/* Register r_masked_intr, scope pio, type r */
#define reg_pio_r_masked_intr___rdy___lsb 0
#define reg_pio_r_masked_intr___rdy___width 1
#define reg_pio_r_masked_intr___rdy___bit 0
#define reg_pio_r_masked_intr_offset 112
/* Constants */
#define regk_pio_a2 0x00000003
#define regk_pio_no 0x00000000
#define regk_pio_normal 0x00000000
#define regk_pio_rd 0x00000001
#define regk_pio_rw_ce0_cfg_default 0x00000000
#define regk_pio_rw_ce1_cfg_default 0x00000000
#define regk_pio_rw_ce2_cfg_default 0x00000000
#define regk_pio_rw_intr_mask_default 0x00000000
#define regk_pio_rw_man_ctrl_default 0x00000000
#define regk_pio_rw_oe_default 0x00000000
#define regk_pio_wr 0x00000002
#define regk_pio_wr_ce2 0x00000003
#define regk_pio_yes 0x00000001
#define regk_pio_yes_all 0x000000ff
#endif /* __pio_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h Normal file
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#ifndef __reg_map_asm_h
#define __reg_map_asm_h
/*
* This file is autogenerated from
* file: reg.rmap
*
* by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#define regi_ccd 0xb0000000
#define regi_ccd_top 0xb0000000
#define regi_ccd_dp 0xb0000400
#define regi_ccd_stat 0xb0000800
#define regi_ccd_tg 0xb0001000
#define regi_cfg 0xb0002000
#define regi_clkgen 0xb0004000
#define regi_ddr2_ctrl 0xb0006000
#define regi_dma0 0xb0008000
#define regi_dma1 0xb000a000
#define regi_dma11 0xb000c000
#define regi_dma2 0xb000e000
#define regi_dma3 0xb0010000
#define regi_dma4 0xb0012000
#define regi_dma5 0xb0014000
#define regi_dma6 0xb0016000
#define regi_dma7 0xb0018000
#define regi_dma9 0xb001a000
#define regi_eth 0xb001c000
#define regi_gio 0xb0020000
#define regi_h264 0xb0022000
#define regi_hist 0xb0026000
#define regi_iop 0xb0028000
#define regi_iop_version 0xb0028000
#define regi_iop_fifo_in_extra 0xb0028040
#define regi_iop_fifo_out_extra 0xb0028080
#define regi_iop_trigger_grp0 0xb00280c0
#define regi_iop_trigger_grp1 0xb0028100
#define regi_iop_trigger_grp2 0xb0028140
#define regi_iop_trigger_grp3 0xb0028180
#define regi_iop_trigger_grp4 0xb00281c0
#define regi_iop_trigger_grp5 0xb0028200
#define regi_iop_trigger_grp6 0xb0028240
#define regi_iop_trigger_grp7 0xb0028280
#define regi_iop_crc_par 0xb0028300
#define regi_iop_dmc_in 0xb0028380
#define regi_iop_dmc_out 0xb0028400
#define regi_iop_fifo_in 0xb0028480
#define regi_iop_fifo_out 0xb0028500
#define regi_iop_scrc_in 0xb0028580
#define regi_iop_scrc_out 0xb0028600
#define regi_iop_timer_grp0 0xb0028680
#define regi_iop_timer_grp1 0xb0028700
#define regi_iop_sap_in 0xb0028800
#define regi_iop_sap_out 0xb0028900
#define regi_iop_spu 0xb0028a00
#define regi_iop_sw_cfg 0xb0028b00
#define regi_iop_sw_cpu 0xb0028c00
#define regi_iop_sw_mpu 0xb0028d00
#define regi_iop_sw_spu 0xb0028e00
#define regi_iop_mpu 0xb0029000
#define regi_irq 0xb002a000
#define regi_jpeg 0xb002c000
#define regi_l2cache 0xb0030000
#define regi_marb_bar 0xb0032000
#define regi_marb_bar_bp0 0xb0032140
#define regi_marb_bar_bp1 0xb0032180
#define regi_marb_bar_bp2 0xb00321c0
#define regi_marb_bar_bp3 0xb0032200
#define regi_marb_foo 0xb0034000
#define regi_marb_foo_bp0 0xb0034280
#define regi_marb_foo_bp1 0xb00342c0
#define regi_marb_foo_bp2 0xb0034300
#define regi_marb_foo_bp3 0xb0034340
#define regi_pinmux 0xb0038000
#define regi_pio 0xb0036000
#define regi_sclr 0xb003a000
#define regi_sclr_fifo 0xb003c000
#define regi_ser0 0xb003e000
#define regi_ser1 0xb0040000
#define regi_ser2 0xb0042000
#define regi_ser3 0xb0044000
#define regi_ser4 0xb0046000
#define regi_sser 0xb0048000
#define regi_strcop 0xb004a000
#define regi_strdma0 0xb004e000
#define regi_strdma1 0xb0050000
#define regi_strdma2 0xb0052000
#define regi_strdma3 0xb0054000
#define regi_strdma5 0xb0056000
#define regi_strmux 0xb004c000
#define regi_timer0 0xb0058000
#define regi_timer1 0xb005a000
#define regi_trace 0xb005c000
#define regi_vin 0xb005e000
#define regi_vout 0xb0060000
#endif /* __reg_map_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h Normal file
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#ifndef __timer_defs_asm_h
#define __timer_defs_asm_h
/*
* This file is autogenerated from
* file: timer.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_tmr0_div, scope timer, type rw */
#define reg_timer_rw_tmr0_div_offset 0
/* Register r_tmr0_data, scope timer, type r */
#define reg_timer_r_tmr0_data_offset 4
/* Register rw_tmr0_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr0_ctrl___op___lsb 0
#define reg_timer_rw_tmr0_ctrl___op___width 2
#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
#define reg_timer_rw_tmr0_ctrl___freq___width 3
#define reg_timer_rw_tmr0_ctrl_offset 8
/* Register rw_tmr1_div, scope timer, type rw */
#define reg_timer_rw_tmr1_div_offset 16
/* Register r_tmr1_data, scope timer, type r */
#define reg_timer_r_tmr1_data_offset 20
/* Register rw_tmr1_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr1_ctrl___op___lsb 0
#define reg_timer_rw_tmr1_ctrl___op___width 2
#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
#define reg_timer_rw_tmr1_ctrl___freq___width 3
#define reg_timer_rw_tmr1_ctrl_offset 24
/* Register rs_cnt_data, scope timer, type rs */
#define reg_timer_rs_cnt_data___tmr___lsb 0
#define reg_timer_rs_cnt_data___tmr___width 24
#define reg_timer_rs_cnt_data___cnt___lsb 24
#define reg_timer_rs_cnt_data___cnt___width 8
#define reg_timer_rs_cnt_data_offset 32
/* Register r_cnt_data, scope timer, type r */
#define reg_timer_r_cnt_data___tmr___lsb 0
#define reg_timer_r_cnt_data___tmr___width 24
#define reg_timer_r_cnt_data___cnt___lsb 24
#define reg_timer_r_cnt_data___cnt___width 8
#define reg_timer_r_cnt_data_offset 36
/* Register rw_cnt_cfg, scope timer, type rw */
#define reg_timer_rw_cnt_cfg___clk___lsb 0
#define reg_timer_rw_cnt_cfg___clk___width 2
#define reg_timer_rw_cnt_cfg_offset 40
/* Register rw_trig, scope timer, type rw */
#define reg_timer_rw_trig_offset 48
/* Register rw_trig_cfg, scope timer, type rw */
#define reg_timer_rw_trig_cfg___tmr___lsb 0
#define reg_timer_rw_trig_cfg___tmr___width 2
#define reg_timer_rw_trig_cfg_offset 52
/* Register r_time, scope timer, type r */
#define reg_timer_r_time_offset 56
/* Register rw_out, scope timer, type rw */
#define reg_timer_rw_out___tmr___lsb 0
#define reg_timer_rw_out___tmr___width 2
#define reg_timer_rw_out_offset 60
/* Register rw_wd_ctrl, scope timer, type rw */
#define reg_timer_rw_wd_ctrl___cnt___lsb 0
#define reg_timer_rw_wd_ctrl___cnt___width 8
#define reg_timer_rw_wd_ctrl___cmd___lsb 8
#define reg_timer_rw_wd_ctrl___cmd___width 1
#define reg_timer_rw_wd_ctrl___cmd___bit 8
#define reg_timer_rw_wd_ctrl___key___lsb 9
#define reg_timer_rw_wd_ctrl___key___width 7
#define reg_timer_rw_wd_ctrl_offset 64
/* Register r_wd_stat, scope timer, type r */
#define reg_timer_r_wd_stat___cnt___lsb 0
#define reg_timer_r_wd_stat___cnt___width 8
#define reg_timer_r_wd_stat___cmd___lsb 8
#define reg_timer_r_wd_stat___cmd___width 1
#define reg_timer_r_wd_stat___cmd___bit 8
#define reg_timer_r_wd_stat_offset 68
/* Register rw_intr_mask, scope timer, type rw */
#define reg_timer_rw_intr_mask___tmr0___lsb 0
#define reg_timer_rw_intr_mask___tmr0___width 1
#define reg_timer_rw_intr_mask___tmr0___bit 0
#define reg_timer_rw_intr_mask___tmr1___lsb 1
#define reg_timer_rw_intr_mask___tmr1___width 1
#define reg_timer_rw_intr_mask___tmr1___bit 1
#define reg_timer_rw_intr_mask___cnt___lsb 2
#define reg_timer_rw_intr_mask___cnt___width 1
#define reg_timer_rw_intr_mask___cnt___bit 2
#define reg_timer_rw_intr_mask___trig___lsb 3
#define reg_timer_rw_intr_mask___trig___width 1
#define reg_timer_rw_intr_mask___trig___bit 3
#define reg_timer_rw_intr_mask_offset 72
/* Register rw_ack_intr, scope timer, type rw */
#define reg_timer_rw_ack_intr___tmr0___lsb 0
#define reg_timer_rw_ack_intr___tmr0___width 1
#define reg_timer_rw_ack_intr___tmr0___bit 0
#define reg_timer_rw_ack_intr___tmr1___lsb 1
#define reg_timer_rw_ack_intr___tmr1___width 1
#define reg_timer_rw_ack_intr___tmr1___bit 1
#define reg_timer_rw_ack_intr___cnt___lsb 2
#define reg_timer_rw_ack_intr___cnt___width 1
#define reg_timer_rw_ack_intr___cnt___bit 2
#define reg_timer_rw_ack_intr___trig___lsb 3
#define reg_timer_rw_ack_intr___trig___width 1
#define reg_timer_rw_ack_intr___trig___bit 3
#define reg_timer_rw_ack_intr_offset 76
/* Register r_intr, scope timer, type r */
#define reg_timer_r_intr___tmr0___lsb 0
#define reg_timer_r_intr___tmr0___width 1
#define reg_timer_r_intr___tmr0___bit 0
#define reg_timer_r_intr___tmr1___lsb 1
#define reg_timer_r_intr___tmr1___width 1
#define reg_timer_r_intr___tmr1___bit 1
#define reg_timer_r_intr___cnt___lsb 2
#define reg_timer_r_intr___cnt___width 1
#define reg_timer_r_intr___cnt___bit 2
#define reg_timer_r_intr___trig___lsb 3
#define reg_timer_r_intr___trig___width 1
#define reg_timer_r_intr___trig___bit 3
#define reg_timer_r_intr_offset 80
/* Register r_masked_intr, scope timer, type r */
#define reg_timer_r_masked_intr___tmr0___lsb 0
#define reg_timer_r_masked_intr___tmr0___width 1
#define reg_timer_r_masked_intr___tmr0___bit 0
#define reg_timer_r_masked_intr___tmr1___lsb 1
#define reg_timer_r_masked_intr___tmr1___width 1
#define reg_timer_r_masked_intr___tmr1___bit 1
#define reg_timer_r_masked_intr___cnt___lsb 2
#define reg_timer_r_masked_intr___cnt___width 1
#define reg_timer_r_masked_intr___cnt___bit 2
#define reg_timer_r_masked_intr___trig___lsb 3
#define reg_timer_r_masked_intr___trig___width 1
#define reg_timer_r_masked_intr___trig___bit 3
#define reg_timer_r_masked_intr_offset 84
/* Register rw_test, scope timer, type rw */
#define reg_timer_rw_test___dis___lsb 0
#define reg_timer_rw_test___dis___width 1
#define reg_timer_rw_test___dis___bit 0
#define reg_timer_rw_test___en___lsb 1
#define reg_timer_rw_test___en___width 1
#define reg_timer_rw_test___en___bit 1
#define reg_timer_rw_test_offset 88
/* Constants */
#define regk_timer_ext 0x00000001
#define regk_timer_f100 0x00000007
#define regk_timer_f29_493 0x00000004
#define regk_timer_f32 0x00000005
#define regk_timer_f32_768 0x00000006
#define regk_timer_f90 0x00000003
#define regk_timer_hold 0x00000001
#define regk_timer_ld 0x00000000
#define regk_timer_no 0x00000000
#define regk_timer_off 0x00000000
#define regk_timer_run 0x00000002
#define regk_timer_rw_cnt_cfg_default 0x00000000
#define regk_timer_rw_intr_mask_default 0x00000000
#define regk_timer_rw_out_default 0x00000000
#define regk_timer_rw_test_default 0x00000000
#define regk_timer_rw_tmr0_ctrl_default 0x00000000
#define regk_timer_rw_tmr1_ctrl_default 0x00000000
#define regk_timer_rw_trig_cfg_default 0x00000000
#define regk_timer_start 0x00000001
#define regk_timer_stop 0x00000000
#define regk_timer_time 0x00000001
#define regk_timer_tmr0 0x00000002
#define regk_timer_tmr1 0x00000003
#define regk_timer_vclk 0x00000002
#define regk_timer_yes 0x00000001
#endif /* __timer_defs_asm_h */

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#ifndef __clkgen_defs_h
#define __clkgen_defs_h
/*
* This file is autogenerated from
* file: clkgen.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope clkgen */
/* Register r_bootsel, scope clkgen, type r */
typedef struct {
unsigned int boot_mode : 5;
unsigned int intern_main_clk : 1;
unsigned int extern_usb2_clk : 1;
unsigned int dummy1 : 25;
} reg_clkgen_r_bootsel;
#define REG_RD_ADDR_clkgen_r_bootsel 0
/* Register rw_clk_ctrl, scope clkgen, type rw */
typedef struct {
unsigned int pll : 1;
unsigned int cpu : 1;
unsigned int iop_usb : 1;
unsigned int vin : 1;
unsigned int sclr : 1;
unsigned int h264 : 1;
unsigned int ddr2 : 1;
unsigned int vout_hist : 1;
unsigned int eth : 1;
unsigned int ccd_tg_200 : 1;
unsigned int dma0_1_eth : 1;
unsigned int ccd_tg_100 : 1;
unsigned int jpeg : 1;
unsigned int sser_ser_dma6_7 : 1;
unsigned int strdma0_2_video : 1;
unsigned int dma2_3_strcop : 1;
unsigned int dma4_5_iop : 1;
unsigned int dma9_11 : 1;
unsigned int memarb_bar_ddr : 1;
unsigned int sclr_h264 : 1;
unsigned int dummy1 : 12;
} reg_clkgen_rw_clk_ctrl;
#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
/* Constants */
enum {
regk_clkgen_eth1000_rx = 0x0000000c,
regk_clkgen_eth1000_tx = 0x0000000e,
regk_clkgen_eth100_rx = 0x0000001d,
regk_clkgen_eth100_rx_half = 0x0000001c,
regk_clkgen_eth100_tx = 0x0000001f,
regk_clkgen_eth100_tx_half = 0x0000001e,
regk_clkgen_nand_3_2 = 0x00000000,
regk_clkgen_nand_3_2_0x30 = 0x00000002,
regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
regk_clkgen_nand_3_2_pll = 0x00000010,
regk_clkgen_nand_3_3 = 0x00000001,
regk_clkgen_nand_3_3_0x30 = 0x00000003,
regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
regk_clkgen_nand_3_3_pll = 0x00000011,
regk_clkgen_nand_4_2 = 0x00000004,
regk_clkgen_nand_4_2_0x30 = 0x00000006,
regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
regk_clkgen_nand_4_2_pll = 0x00000014,
regk_clkgen_nand_4_3 = 0x00000005,
regk_clkgen_nand_4_3_0x30 = 0x00000007,
regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
regk_clkgen_nand_4_3_pll = 0x00000015,
regk_clkgen_nand_5_2 = 0x00000008,
regk_clkgen_nand_5_2_0x30 = 0x0000000a,
regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
regk_clkgen_nand_5_2_pll = 0x00000018,
regk_clkgen_nand_5_3 = 0x00000009,
regk_clkgen_nand_5_3_0x30 = 0x0000000b,
regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
regk_clkgen_nand_5_3_pll = 0x00000019,
regk_clkgen_no = 0x00000000,
regk_clkgen_rw_clk_ctrl_default = 0x00000002,
regk_clkgen_ser = 0x0000000d,
regk_clkgen_ser_pll = 0x0000000f,
regk_clkgen_yes = 0x00000001
};
#endif /* __clkgen_defs_h */

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#ifndef __ddr2_defs_h
#define __ddr2_defs_h
/*
* This file is autogenerated from
* file: ddr2.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope ddr2 */
/* Register rw_cfg, scope ddr2, type rw */
typedef struct {
unsigned int col_width : 4;
unsigned int nr_banks : 1;
unsigned int bw : 1;
unsigned int nr_ref : 4;
unsigned int ref_interval : 11;
unsigned int odt_ctrl : 2;
unsigned int odt_mem : 1;
unsigned int imp_strength : 1;
unsigned int auto_imp_cal : 1;
unsigned int imp_cal_override : 1;
unsigned int dll_override : 1;
unsigned int dummy1 : 4;
} reg_ddr2_rw_cfg;
#define REG_RD_ADDR_ddr2_rw_cfg 0
#define REG_WR_ADDR_ddr2_rw_cfg 0
/* Register rw_timing, scope ddr2, type rw */
typedef struct {
unsigned int wr : 3;
unsigned int rcd : 3;
unsigned int rp : 3;
unsigned int ras : 4;
unsigned int rfc : 7;
unsigned int rc : 5;
unsigned int rtp : 2;
unsigned int rtw : 3;
unsigned int wtr : 2;
} reg_ddr2_rw_timing;
#define REG_RD_ADDR_ddr2_rw_timing 4
#define REG_WR_ADDR_ddr2_rw_timing 4
/* Register rw_latency, scope ddr2, type rw */
typedef struct {
unsigned int cas : 3;
unsigned int additive : 3;
unsigned int dummy1 : 26;
} reg_ddr2_rw_latency;
#define REG_RD_ADDR_ddr2_rw_latency 8
#define REG_WR_ADDR_ddr2_rw_latency 8
/* Register rw_phy_cfg, scope ddr2, type rw */
typedef struct {
unsigned int en : 1;
unsigned int dummy1 : 31;
} reg_ddr2_rw_phy_cfg;
#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
/* Register rw_phy_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int rst : 1;
unsigned int cal_rst : 1;
unsigned int cal_start : 1;
unsigned int dummy1 : 29;
} reg_ddr2_rw_phy_ctrl;
#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
/* Register rw_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int mrs_data : 16;
unsigned int cmd : 8;
unsigned int dummy1 : 8;
} reg_ddr2_rw_ctrl;
#define REG_RD_ADDR_ddr2_rw_ctrl 20
#define REG_WR_ADDR_ddr2_rw_ctrl 20
/* Register rw_pwr_down, scope ddr2, type rw */
typedef struct {
unsigned int self_ref : 2;
unsigned int phy_en : 1;
unsigned int dummy1 : 29;
} reg_ddr2_rw_pwr_down;
#define REG_RD_ADDR_ddr2_rw_pwr_down 24
#define REG_WR_ADDR_ddr2_rw_pwr_down 24
/* Register r_stat, scope ddr2, type r */
typedef struct {
unsigned int dll_lock : 1;
unsigned int dll_delay_code : 7;
unsigned int imp_cal_done : 1;
unsigned int imp_cal_fault : 1;
unsigned int cal_imp_pu : 4;
unsigned int cal_imp_pd : 4;
unsigned int dummy1 : 14;
} reg_ddr2_r_stat;
#define REG_RD_ADDR_ddr2_r_stat 28
/* Register rw_imp_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int imp_pu : 4;
unsigned int imp_pd : 4;
unsigned int dummy1 : 24;
} reg_ddr2_rw_imp_ctrl;
#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
#define STRIDE_ddr2_rw_dll_ctrl 4
/* Register rw_dll_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int mode : 1;
unsigned int clk_delay : 7;
unsigned int dummy1 : 24;
} reg_ddr2_rw_dll_ctrl;
#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
typedef struct {
unsigned int dqs90_delay : 7;
unsigned int dqs180_delay : 7;
unsigned int dqs270_delay : 7;
unsigned int dqs360_delay : 7;
unsigned int dummy1 : 4;
} reg_ddr2_rw_dqs_dll_ctrl;
#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
/* Constants */
enum {
regk_ddr2_al0 = 0x00000000,
regk_ddr2_al1 = 0x00000008,
regk_ddr2_al2 = 0x00000010,
regk_ddr2_al3 = 0x00000018,
regk_ddr2_al4 = 0x00000020,
regk_ddr2_auto = 0x00000003,
regk_ddr2_bank4 = 0x00000000,
regk_ddr2_bank8 = 0x00000001,
regk_ddr2_bl4 = 0x00000002,
regk_ddr2_bl8 = 0x00000003,
regk_ddr2_bt_il = 0x00000008,
regk_ddr2_bt_seq = 0x00000000,
regk_ddr2_bw16 = 0x00000001,
regk_ddr2_bw32 = 0x00000000,
regk_ddr2_cas2 = 0x00000020,
regk_ddr2_cas3 = 0x00000030,
regk_ddr2_cas4 = 0x00000040,
regk_ddr2_cas5 = 0x00000050,
regk_ddr2_deselect = 0x000000c0,
regk_ddr2_dic_weak = 0x00000002,
regk_ddr2_direct = 0x00000001,
regk_ddr2_dis = 0x00000000,
regk_ddr2_dll_dis = 0x00000001,
regk_ddr2_dll_en = 0x00000000,
regk_ddr2_dll_rst = 0x00000100,
regk_ddr2_emrs = 0x00000081,
regk_ddr2_emrs2 = 0x00000082,
regk_ddr2_emrs3 = 0x00000083,
regk_ddr2_full = 0x00000001,
regk_ddr2_hi_ref_rate = 0x00000080,
regk_ddr2_mrs = 0x00000080,
regk_ddr2_no = 0x00000000,
regk_ddr2_nop = 0x000000b8,
regk_ddr2_ocd_adj = 0x00000200,
regk_ddr2_ocd_default = 0x00000380,
regk_ddr2_ocd_drive0 = 0x00000100,
regk_ddr2_ocd_drive1 = 0x00000080,
regk_ddr2_ocd_exit = 0x00000000,
regk_ddr2_odt_dis = 0x00000000,
regk_ddr2_offs = 0x00000000,
regk_ddr2_pre = 0x00000090,
regk_ddr2_pre_all = 0x00000400,
regk_ddr2_pwr_down_fast = 0x00000000,
regk_ddr2_pwr_down_slow = 0x00001000,
regk_ddr2_ref = 0x00000088,
regk_ddr2_rtt150 = 0x00000040,
regk_ddr2_rtt50 = 0x00000044,
regk_ddr2_rtt75 = 0x00000004,
regk_ddr2_rw_cfg_default = 0x00186000,
regk_ddr2_rw_dll_ctrl_default = 0x00000000,
regk_ddr2_rw_dll_ctrl_size = 0x00000004,
regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
regk_ddr2_rw_latency_default = 0x00000000,
regk_ddr2_rw_phy_cfg_default = 0x00000000,
regk_ddr2_rw_pwr_down_default = 0x00000000,
regk_ddr2_rw_timing_default = 0x00000000,
regk_ddr2_s1Gb = 0x0000001a,
regk_ddr2_s256Mb = 0x0000000f,
regk_ddr2_s2Gb = 0x00000027,
regk_ddr2_s4Gb = 0x00000042,
regk_ddr2_s512Mb = 0x00000015,
regk_ddr2_temp0_85 = 0x00000618,
regk_ddr2_temp85_95 = 0x0000030c,
regk_ddr2_term150 = 0x00000002,
regk_ddr2_term50 = 0x00000003,
regk_ddr2_term75 = 0x00000001,
regk_ddr2_test = 0x00000080,
regk_ddr2_weak = 0x00000000,
regk_ddr2_wr2 = 0x00000200,
regk_ddr2_wr3 = 0x00000400,
regk_ddr2_yes = 0x00000001
};
#endif /* __ddr2_defs_h */

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#ifndef __gio_defs_h
#define __gio_defs_h
/*
* This file is autogenerated from
* file: gio.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope gio */
/* Register r_pa_din, scope gio, type r */
typedef struct {
unsigned int data : 32;
} reg_gio_r_pa_din;
#define REG_RD_ADDR_gio_r_pa_din 0
/* Register rw_pa_dout, scope gio, type rw */
typedef struct {
unsigned int data : 32;
} reg_gio_rw_pa_dout;
#define REG_RD_ADDR_gio_rw_pa_dout 4
#define REG_WR_ADDR_gio_rw_pa_dout 4
/* Register rw_pa_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 32;
} reg_gio_rw_pa_oe;
#define REG_RD_ADDR_gio_rw_pa_oe 8
#define REG_WR_ADDR_gio_rw_pa_oe 8
/* Register rw_pa_byte0_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte0_dout;
#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12
/* Register rw_pa_byte0_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte0_oe;
#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16
/* Register rw_pa_byte1_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte1_dout;
#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20
/* Register rw_pa_byte1_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte1_oe;
#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24
/* Register rw_pa_byte2_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte2_dout;
#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28
/* Register rw_pa_byte2_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte2_oe;
#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32
/* Register rw_pa_byte3_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte3_dout;
#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36
/* Register rw_pa_byte3_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte3_oe;
#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40
/* Register r_pb_din, scope gio, type r */
typedef struct {
unsigned int data : 32;
} reg_gio_r_pb_din;
#define REG_RD_ADDR_gio_r_pb_din 44
/* Register rw_pb_dout, scope gio, type rw */
typedef struct {
unsigned int data : 32;
} reg_gio_rw_pb_dout;
#define REG_RD_ADDR_gio_rw_pb_dout 48
#define REG_WR_ADDR_gio_rw_pb_dout 48
/* Register rw_pb_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 32;
} reg_gio_rw_pb_oe;
#define REG_RD_ADDR_gio_rw_pb_oe 52
#define REG_WR_ADDR_gio_rw_pb_oe 52
/* Register rw_pb_byte0_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte0_dout;
#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56
/* Register rw_pb_byte0_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte0_oe;
#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60
/* Register rw_pb_byte1_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte1_dout;
#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64
/* Register rw_pb_byte1_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte1_oe;
#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68
/* Register rw_pb_byte2_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte2_dout;
#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72
/* Register rw_pb_byte2_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte2_oe;
#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76
/* Register rw_pb_byte3_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte3_dout;
#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80
/* Register rw_pb_byte3_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte3_oe;
#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84
/* Register r_pc_din, scope gio, type r */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_gio_r_pc_din;
#define REG_RD_ADDR_gio_r_pc_din 88
/* Register rw_pc_dout, scope gio, type rw */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_gio_rw_pc_dout;
#define REG_RD_ADDR_gio_rw_pc_dout 92
#define REG_WR_ADDR_gio_rw_pc_dout 92
/* Register rw_pc_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 16;
unsigned int dummy1 : 16;
} reg_gio_rw_pc_oe;
#define REG_RD_ADDR_gio_rw_pc_oe 96
#define REG_WR_ADDR_gio_rw_pc_oe 96
/* Register rw_pc_byte0_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte0_dout;
#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100
/* Register rw_pc_byte0_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte0_oe;
#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104
/* Register rw_pc_byte1_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte1_dout;
#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108
/* Register rw_pc_byte1_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte1_oe;
#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112
/* Register r_pd_din, scope gio, type r */
typedef struct {
unsigned int data : 32;
} reg_gio_r_pd_din;
#define REG_RD_ADDR_gio_r_pd_din 116
/* Register rw_intr_cfg, scope gio, type rw */
typedef struct {
unsigned int intr0 : 3;
unsigned int intr1 : 3;
unsigned int intr2 : 3;
unsigned int intr3 : 3;
unsigned int intr4 : 3;
unsigned int intr5 : 3;
unsigned int intr6 : 3;
unsigned int intr7 : 3;
unsigned int dummy1 : 8;
} reg_gio_rw_intr_cfg;
#define REG_RD_ADDR_gio_rw_intr_cfg 120
#define REG_WR_ADDR_gio_rw_intr_cfg 120
/* Register rw_intr_pins, scope gio, type rw */
typedef struct {
unsigned int intr0 : 4;
unsigned int intr1 : 4;
unsigned int intr2 : 4;
unsigned int intr3 : 4;
unsigned int intr4 : 4;
unsigned int intr5 : 4;
unsigned int intr6 : 4;
unsigned int intr7 : 4;
} reg_gio_rw_intr_pins;
#define REG_RD_ADDR_gio_rw_intr_pins 124
#define REG_WR_ADDR_gio_rw_intr_pins 124
/* Register rw_intr_mask, scope gio, type rw */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int i2c0_done : 1;
unsigned int i2c1_done : 1;
unsigned int dummy1 : 22;
} reg_gio_rw_intr_mask;
#define REG_RD_ADDR_gio_rw_intr_mask 128
#define REG_WR_ADDR_gio_rw_intr_mask 128
/* Register rw_ack_intr, scope gio, type rw */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int i2c0_done : 1;
unsigned int i2c1_done : 1;
unsigned int dummy1 : 22;
} reg_gio_rw_ack_intr;
#define REG_RD_ADDR_gio_rw_ack_intr 132
#define REG_WR_ADDR_gio_rw_ack_intr 132
/* Register r_intr, scope gio, type r */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int i2c0_done : 1;
unsigned int i2c1_done : 1;
unsigned int dummy1 : 22;
} reg_gio_r_intr;
#define REG_RD_ADDR_gio_r_intr 136
/* Register r_masked_intr, scope gio, type r */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int i2c0_done : 1;
unsigned int i2c1_done : 1;
unsigned int dummy1 : 22;
} reg_gio_r_masked_intr;
#define REG_RD_ADDR_gio_r_masked_intr 140
/* Register rw_i2c0_start, scope gio, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_gio_rw_i2c0_start;
#define REG_RD_ADDR_gio_rw_i2c0_start 144
#define REG_WR_ADDR_gio_rw_i2c0_start 144
/* Register rw_i2c0_cfg, scope gio, type rw */
typedef struct {
unsigned int en : 1;
unsigned int bit_order : 1;
unsigned int scl_io : 1;
unsigned int scl_inv : 1;
unsigned int sda_io : 1;
unsigned int sda_idle : 1;
unsigned int dummy1 : 26;
} reg_gio_rw_i2c0_cfg;
#define REG_RD_ADDR_gio_rw_i2c0_cfg 148
#define REG_WR_ADDR_gio_rw_i2c0_cfg 148
/* Register rw_i2c0_ctrl, scope gio, type rw */
typedef struct {
unsigned int trf_bits : 6;
unsigned int switch_dir : 6;
unsigned int extra_start : 3;
unsigned int early_end : 1;
unsigned int start_stop : 1;
unsigned int ack_dir0 : 1;
unsigned int ack_dir1 : 1;
unsigned int ack_dir2 : 1;
unsigned int ack_dir3 : 1;
unsigned int ack_dir4 : 1;
unsigned int ack_dir5 : 1;
unsigned int ack_bit : 1;
unsigned int start_bit : 1;
unsigned int freq : 2;
unsigned int dummy1 : 5;
} reg_gio_rw_i2c0_ctrl;
#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152
/* Register rw_i2c0_data, scope gio, type rw */
typedef struct {
unsigned int data0 : 8;
unsigned int data1 : 8;
unsigned int data2 : 8;
unsigned int data3 : 8;
} reg_gio_rw_i2c0_data;
#define REG_RD_ADDR_gio_rw_i2c0_data 156
#define REG_WR_ADDR_gio_rw_i2c0_data 156
/* Register rw_i2c0_data2, scope gio, type rw */
typedef struct {
unsigned int data4 : 8;
unsigned int data5 : 8;
unsigned int start_val : 6;
unsigned int ack_val : 6;
unsigned int dummy1 : 4;
} reg_gio_rw_i2c0_data2;
#define REG_RD_ADDR_gio_rw_i2c0_data2 160
#define REG_WR_ADDR_gio_rw_i2c0_data2 160
/* Register rw_i2c1_start, scope gio, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_gio_rw_i2c1_start;
#define REG_RD_ADDR_gio_rw_i2c1_start 164
#define REG_WR_ADDR_gio_rw_i2c1_start 164
/* Register rw_i2c1_cfg, scope gio, type rw */
typedef struct {
unsigned int en : 1;
unsigned int bit_order : 1;
unsigned int scl_io : 1;
unsigned int scl_inv : 1;
unsigned int sda0_io : 1;
unsigned int sda0_idle : 1;
unsigned int sda1_io : 1;
unsigned int sda1_idle : 1;
unsigned int sda2_io : 1;
unsigned int sda2_idle : 1;
unsigned int sda3_io : 1;
unsigned int sda3_idle : 1;
unsigned int sda_sel : 2;
unsigned int sen_idle : 1;
unsigned int sen_inv : 1;
unsigned int sen_sel : 2;
unsigned int dummy1 : 14;
} reg_gio_rw_i2c1_cfg;
#define REG_RD_ADDR_gio_rw_i2c1_cfg 168
#define REG_WR_ADDR_gio_rw_i2c1_cfg 168
/* Register rw_i2c1_ctrl, scope gio, type rw */
typedef struct {
unsigned int trf_bits : 6;
unsigned int switch_dir : 6;
unsigned int extra_start : 3;
unsigned int early_end : 1;
unsigned int start_stop : 1;
unsigned int ack_dir0 : 1;
unsigned int ack_dir1 : 1;
unsigned int ack_dir2 : 1;
unsigned int ack_dir3 : 1;
unsigned int ack_dir4 : 1;
unsigned int ack_dir5 : 1;
unsigned int ack_bit : 1;
unsigned int start_bit : 1;
unsigned int freq : 2;
unsigned int dummy1 : 5;
} reg_gio_rw_i2c1_ctrl;
#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172
/* Register rw_i2c1_data, scope gio, type rw */
typedef struct {
unsigned int data0 : 8;
unsigned int data1 : 8;
unsigned int data2 : 8;
unsigned int data3 : 8;
} reg_gio_rw_i2c1_data;
#define REG_RD_ADDR_gio_rw_i2c1_data 176
#define REG_WR_ADDR_gio_rw_i2c1_data 176
/* Register rw_i2c1_data2, scope gio, type rw */
typedef struct {
unsigned int data4 : 8;
unsigned int data5 : 8;
unsigned int start_val : 6;
unsigned int ack_val : 6;
unsigned int dummy1 : 4;
} reg_gio_rw_i2c1_data2;
#define REG_RD_ADDR_gio_rw_i2c1_data2 180
#define REG_WR_ADDR_gio_rw_i2c1_data2 180
/* Register r_ppwm_stat, scope gio, type r */
typedef struct {
unsigned int freq : 2;
unsigned int dummy1 : 30;
} reg_gio_r_ppwm_stat;
#define REG_RD_ADDR_gio_r_ppwm_stat 184
/* Register rw_ppwm_data, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_ppwm_data;
#define REG_RD_ADDR_gio_rw_ppwm_data 188
#define REG_WR_ADDR_gio_rw_ppwm_data 188
/* Register rw_pwm0_ctrl, scope gio, type rw */
typedef struct {
unsigned int mode : 2;
unsigned int ccd_override : 1;
unsigned int ccd_val : 1;
unsigned int dummy1 : 28;
} reg_gio_rw_pwm0_ctrl;
#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192
/* Register rw_pwm0_var, scope gio, type rw */
typedef struct {
unsigned int lo : 13;
unsigned int hi : 13;
unsigned int dummy1 : 6;
} reg_gio_rw_pwm0_var;
#define REG_RD_ADDR_gio_rw_pwm0_var 196
#define REG_WR_ADDR_gio_rw_pwm0_var 196
/* Register rw_pwm0_data, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pwm0_data;
#define REG_RD_ADDR_gio_rw_pwm0_data 200
#define REG_WR_ADDR_gio_rw_pwm0_data 200
/* Register rw_pwm1_ctrl, scope gio, type rw */
typedef struct {
unsigned int mode : 2;
unsigned int ccd_override : 1;
unsigned int ccd_val : 1;
unsigned int dummy1 : 28;
} reg_gio_rw_pwm1_ctrl;
#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204
/* Register rw_pwm1_var, scope gio, type rw */
typedef struct {
unsigned int lo : 13;
unsigned int hi : 13;
unsigned int dummy1 : 6;
} reg_gio_rw_pwm1_var;
#define REG_RD_ADDR_gio_rw_pwm1_var 208
#define REG_WR_ADDR_gio_rw_pwm1_var 208
/* Register rw_pwm1_data, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pwm1_data;
#define REG_RD_ADDR_gio_rw_pwm1_data 212
#define REG_WR_ADDR_gio_rw_pwm1_data 212
/* Register rw_pwm2_ctrl, scope gio, type rw */
typedef struct {
unsigned int mode : 2;
unsigned int ccd_override : 1;
unsigned int ccd_val : 1;
unsigned int dummy1 : 28;
} reg_gio_rw_pwm2_ctrl;
#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216
/* Register rw_pwm2_var, scope gio, type rw */
typedef struct {
unsigned int lo : 13;
unsigned int hi : 13;
unsigned int dummy1 : 6;
} reg_gio_rw_pwm2_var;
#define REG_RD_ADDR_gio_rw_pwm2_var 220
#define REG_WR_ADDR_gio_rw_pwm2_var 220
/* Register rw_pwm2_data, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pwm2_data;
#define REG_RD_ADDR_gio_rw_pwm2_data 224
#define REG_WR_ADDR_gio_rw_pwm2_data 224
/* Register rw_pwm_in_cfg, scope gio, type rw */
typedef struct {
unsigned int pin : 3;
unsigned int dummy1 : 29;
} reg_gio_rw_pwm_in_cfg;
#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228
/* Register r_pwm_in_lo, scope gio, type r */
typedef struct {
unsigned int data : 32;
} reg_gio_r_pwm_in_lo;
#define REG_RD_ADDR_gio_r_pwm_in_lo 232
/* Register r_pwm_in_hi, scope gio, type r */
typedef struct {
unsigned int data : 32;
} reg_gio_r_pwm_in_hi;
#define REG_RD_ADDR_gio_r_pwm_in_hi 236
/* Register r_pwm_in_cnt, scope gio, type r */
typedef struct {
unsigned int data : 32;
} reg_gio_r_pwm_in_cnt;
#define REG_RD_ADDR_gio_r_pwm_in_cnt 240
/* Constants */
enum {
regk_gio_anyedge = 0x00000007,
regk_gio_f100k = 0x00000000,
regk_gio_f1562 = 0x00000000,
regk_gio_f195 = 0x00000003,
regk_gio_f1m = 0x00000002,
regk_gio_f390 = 0x00000002,
regk_gio_f400k = 0x00000001,
regk_gio_f5m = 0x00000003,
regk_gio_f781 = 0x00000001,
regk_gio_hi = 0x00000001,
regk_gio_in = 0x00000000,
regk_gio_intr_pa0 = 0x00000000,
regk_gio_intr_pa1 = 0x00000000,
regk_gio_intr_pa10 = 0x00000001,
regk_gio_intr_pa11 = 0x00000001,
regk_gio_intr_pa12 = 0x00000001,
regk_gio_intr_pa13 = 0x00000001,
regk_gio_intr_pa14 = 0x00000001,
regk_gio_intr_pa15 = 0x00000001,
regk_gio_intr_pa16 = 0x00000002,
regk_gio_intr_pa17 = 0x00000002,
regk_gio_intr_pa18 = 0x00000002,
regk_gio_intr_pa19 = 0x00000002,
regk_gio_intr_pa2 = 0x00000000,
regk_gio_intr_pa20 = 0x00000002,
regk_gio_intr_pa21 = 0x00000002,
regk_gio_intr_pa22 = 0x00000002,
regk_gio_intr_pa23 = 0x00000002,
regk_gio_intr_pa24 = 0x00000003,
regk_gio_intr_pa25 = 0x00000003,
regk_gio_intr_pa26 = 0x00000003,
regk_gio_intr_pa27 = 0x00000003,
regk_gio_intr_pa28 = 0x00000003,
regk_gio_intr_pa29 = 0x00000003,
regk_gio_intr_pa3 = 0x00000000,
regk_gio_intr_pa30 = 0x00000003,
regk_gio_intr_pa31 = 0x00000003,
regk_gio_intr_pa4 = 0x00000000,
regk_gio_intr_pa5 = 0x00000000,
regk_gio_intr_pa6 = 0x00000000,
regk_gio_intr_pa7 = 0x00000000,
regk_gio_intr_pa8 = 0x00000001,
regk_gio_intr_pa9 = 0x00000001,
regk_gio_intr_pb0 = 0x00000004,
regk_gio_intr_pb1 = 0x00000004,
regk_gio_intr_pb10 = 0x00000005,
regk_gio_intr_pb11 = 0x00000005,
regk_gio_intr_pb12 = 0x00000005,
regk_gio_intr_pb13 = 0x00000005,
regk_gio_intr_pb14 = 0x00000005,
regk_gio_intr_pb15 = 0x00000005,
regk_gio_intr_pb16 = 0x00000006,
regk_gio_intr_pb17 = 0x00000006,
regk_gio_intr_pb18 = 0x00000006,
regk_gio_intr_pb19 = 0x00000006,
regk_gio_intr_pb2 = 0x00000004,
regk_gio_intr_pb20 = 0x00000006,
regk_gio_intr_pb21 = 0x00000006,
regk_gio_intr_pb22 = 0x00000006,
regk_gio_intr_pb23 = 0x00000006,
regk_gio_intr_pb24 = 0x00000007,
regk_gio_intr_pb25 = 0x00000007,
regk_gio_intr_pb26 = 0x00000007,
regk_gio_intr_pb27 = 0x00000007,
regk_gio_intr_pb28 = 0x00000007,
regk_gio_intr_pb29 = 0x00000007,
regk_gio_intr_pb3 = 0x00000004,
regk_gio_intr_pb30 = 0x00000007,
regk_gio_intr_pb31 = 0x00000007,
regk_gio_intr_pb4 = 0x00000004,
regk_gio_intr_pb5 = 0x00000004,
regk_gio_intr_pb6 = 0x00000004,
regk_gio_intr_pb7 = 0x00000004,
regk_gio_intr_pb8 = 0x00000005,
regk_gio_intr_pb9 = 0x00000005,
regk_gio_intr_pc0 = 0x00000008,
regk_gio_intr_pc1 = 0x00000008,
regk_gio_intr_pc10 = 0x00000009,
regk_gio_intr_pc11 = 0x00000009,
regk_gio_intr_pc12 = 0x00000009,
regk_gio_intr_pc13 = 0x00000009,
regk_gio_intr_pc14 = 0x00000009,
regk_gio_intr_pc15 = 0x00000009,
regk_gio_intr_pc2 = 0x00000008,
regk_gio_intr_pc3 = 0x00000008,
regk_gio_intr_pc4 = 0x00000008,
regk_gio_intr_pc5 = 0x00000008,
regk_gio_intr_pc6 = 0x00000008,
regk_gio_intr_pc7 = 0x00000008,
regk_gio_intr_pc8 = 0x00000009,
regk_gio_intr_pc9 = 0x00000009,
regk_gio_intr_pd0 = 0x0000000c,
regk_gio_intr_pd1 = 0x0000000c,
regk_gio_intr_pd10 = 0x0000000d,
regk_gio_intr_pd11 = 0x0000000d,
regk_gio_intr_pd12 = 0x0000000d,
regk_gio_intr_pd13 = 0x0000000d,
regk_gio_intr_pd14 = 0x0000000d,
regk_gio_intr_pd15 = 0x0000000d,
regk_gio_intr_pd16 = 0x0000000e,
regk_gio_intr_pd17 = 0x0000000e,
regk_gio_intr_pd18 = 0x0000000e,
regk_gio_intr_pd19 = 0x0000000e,
regk_gio_intr_pd2 = 0x0000000c,
regk_gio_intr_pd20 = 0x0000000e,
regk_gio_intr_pd21 = 0x0000000e,
regk_gio_intr_pd22 = 0x0000000e,
regk_gio_intr_pd23 = 0x0000000e,
regk_gio_intr_pd24 = 0x0000000f,
regk_gio_intr_pd25 = 0x0000000f,
regk_gio_intr_pd26 = 0x0000000f,
regk_gio_intr_pd27 = 0x0000000f,
regk_gio_intr_pd28 = 0x0000000f,
regk_gio_intr_pd29 = 0x0000000f,
regk_gio_intr_pd3 = 0x0000000c,
regk_gio_intr_pd30 = 0x0000000f,
regk_gio_intr_pd31 = 0x0000000f,
regk_gio_intr_pd4 = 0x0000000c,
regk_gio_intr_pd5 = 0x0000000c,
regk_gio_intr_pd6 = 0x0000000c,
regk_gio_intr_pd7 = 0x0000000c,
regk_gio_intr_pd8 = 0x0000000d,
regk_gio_intr_pd9 = 0x0000000d,
regk_gio_lo = 0x00000002,
regk_gio_lsb = 0x00000000,
regk_gio_msb = 0x00000001,
regk_gio_negedge = 0x00000006,
regk_gio_no = 0x00000000,
regk_gio_no_switch = 0x0000003f,
regk_gio_none = 0x00000007,
regk_gio_off = 0x00000000,
regk_gio_opendrain = 0x00000000,
regk_gio_out = 0x00000001,
regk_gio_posedge = 0x00000005,
regk_gio_pwm_hfp = 0x00000002,
regk_gio_pwm_pa0 = 0x00000001,
regk_gio_pwm_pa19 = 0x00000004,
regk_gio_pwm_pa6 = 0x00000002,
regk_gio_pwm_pa7 = 0x00000003,
regk_gio_pwm_pb26 = 0x00000005,
regk_gio_pwm_pd23 = 0x00000006,
regk_gio_pwm_pd31 = 0x00000007,
regk_gio_pwm_std = 0x00000001,
regk_gio_pwm_var = 0x00000003,
regk_gio_rw_i2c0_cfg_default = 0x00000020,
regk_gio_rw_i2c0_ctrl_default = 0x00010000,
regk_gio_rw_i2c0_start_default = 0x00000000,
regk_gio_rw_i2c1_cfg_default = 0x00000aa0,
regk_gio_rw_i2c1_ctrl_default = 0x00010000,
regk_gio_rw_i2c1_start_default = 0x00000000,
regk_gio_rw_intr_cfg_default = 0x00000000,
regk_gio_rw_intr_mask_default = 0x00000000,
regk_gio_rw_pa_oe_default = 0x00000000,
regk_gio_rw_pb_oe_default = 0x00000000,
regk_gio_rw_pc_oe_default = 0x00000000,
regk_gio_rw_ppwm_data_default = 0x00000000,
regk_gio_rw_pwm0_ctrl_default = 0x00000000,
regk_gio_rw_pwm1_ctrl_default = 0x00000000,
regk_gio_rw_pwm2_ctrl_default = 0x00000000,
regk_gio_rw_pwm_in_cfg_default = 0x00000000,
regk_gio_sda0 = 0x00000000,
regk_gio_sda1 = 0x00000001,
regk_gio_sda2 = 0x00000002,
regk_gio_sda3 = 0x00000003,
regk_gio_sen = 0x00000000,
regk_gio_set = 0x00000003,
regk_gio_yes = 0x00000001
};
#endif /* __gio_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h Normal file
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/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr
from intr_vect.r */
#ifndef _INTR_VECT_R
#define _INTR_VECT_R
#define TIMER0_INTR_VECT 0x31
#define TIMER1_INTR_VECT 0x32
#define DMA0_INTR_VECT 0x33
#define DMA1_INTR_VECT 0x34
#define DMA2_INTR_VECT 0x35
#define DMA3_INTR_VECT 0x36
#define DMA4_INTR_VECT 0x37
#define DMA5_INTR_VECT 0x38
#define DMA6_INTR_VECT 0x39
#define DMA7_INTR_VECT 0x3a
#define DMA9_INTR_VECT 0x3b
#define DMA11_INTR_VECT 0x3c
#define GIO_INTR_VECT 0x3d
#define IOP0_INTR_VECT 0x3e
#define IOP1_INTR_VECT 0x3f
#define SER0_INTR_VECT 0x40
#define SER1_INTR_VECT 0x41
#define SER2_INTR_VECT 0x42
#define SER3_INTR_VECT 0x43
#define SER4_INTR_VECT 0x44
#define SSER_INTR_VECT 0x45
#define STRDMA0_INTR_VECT 0x46
#define STRDMA1_INTR_VECT 0x47
#define STRDMA2_INTR_VECT 0x48
#define STRDMA3_INTR_VECT 0x49
#define STRDMA5_INTR_VECT 0x4a
#define VIN_INTR_VECT 0x4b
#define VOUT_INTR_VECT 0x4c
#define JPEG_INTR_VECT 0x4d
#define H264_INTR_VECT 0x4e
#define HISTO_INTR_VECT 0x4f
#define CCD_INTR_VECT 0x50
#define ETH_INTR_VECT 0x51
#define MEMARB_BAR_INTR_VECT 0x52
#define MEMARB_FOO_INTR_VECT 0x53
#define PIO_INTR_VECT 0x54
#define SCLR_INTR_VECT 0x55
#define SCLR_FIFO_INTR_VECT 0x56
#define IPI_INTR_VECT 0x57
#define NBR_INTR_VECT 0x58
#endif

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#ifndef __intr_vect_defs_h
#define __intr_vect_defs_h
/*
* This file is autogenerated from
* file: intr_vect.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope intr_vect */
#define STRIDE_intr_vect_rw_mask 4
/* Register rw_mask0, scope intr_vect, type rw */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_rw_mask0;
#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
#define REG_RD_ADDR_intr_vect_rw_mask 0
#define REG_WR_ADDR_intr_vect_rw_mask 0
#define REG_RD_ADDR_intr_vect_rw_mask0 0
#define REG_WR_ADDR_intr_vect_rw_mask0 0
#define STRIDE_intr_vect_r_vect 4
/* Register r_vect0, scope intr_vect, type r */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_r_vect0;
#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
#define REG_RD_ADDR_intr_vect_r_vect 8
#define REG_RD_ADDR_intr_vect_r_vect0 8
#define STRIDE_intr_vect_r_masked_vect 4
/* Register r_masked_vect0, scope intr_vect, type r */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_r_masked_vect0;
#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
#define REG_RD_ADDR_intr_vect_r_masked_vect 16
#define STRIDE_intr_vect_rw_xmask 4
/* Register rw_xmask0, scope intr_vect, type rw */
typedef struct {
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int gio : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int strdma0 : 1;
unsigned int strdma1 : 1;
unsigned int strdma2 : 1;
unsigned int strdma3 : 1;
unsigned int strdma5 : 1;
unsigned int vin : 1;
unsigned int vout : 1;
unsigned int jpeg : 1;
unsigned int h264 : 1;
unsigned int histo : 1;
unsigned int ccd : 1;
} reg_intr_vect_rw_xmask0;
#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
#define REG_RD_ADDR_intr_vect_rw_xmask0 24
#define REG_WR_ADDR_intr_vect_rw_xmask0 24
#define REG_RD_ADDR_intr_vect_rw_xmask 24
#define REG_WR_ADDR_intr_vect_rw_xmask 24
/* Register rw_mask1, scope intr_vect, type rw */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_rw_mask1;
#define REG_RD_ADDR_intr_vect_rw_mask1 4
#define REG_WR_ADDR_intr_vect_rw_mask1 4
/* Register r_vect1, scope intr_vect, type r */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_r_vect1;
#define REG_RD_ADDR_intr_vect_r_vect1 12
/* Register r_masked_vect1, scope intr_vect, type r */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_r_masked_vect1;
#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
/* Register rw_xmask1, scope intr_vect, type rw */
typedef struct {
unsigned int eth : 1;
unsigned int memarb_bar : 1;
unsigned int memarb_foo : 1;
unsigned int pio : 1;
unsigned int sclr : 1;
unsigned int sclr_fifo : 1;
unsigned int dummy1 : 26;
} reg_intr_vect_rw_xmask1;
#define REG_RD_ADDR_intr_vect_rw_xmask1 28
#define REG_WR_ADDR_intr_vect_rw_xmask1 28
/* Register rw_xmask_ctrl, scope intr_vect, type rw */
typedef struct {
unsigned int en : 1;
unsigned int dummy1 : 31;
} reg_intr_vect_rw_xmask_ctrl;
#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
/* Register r_nmi, scope intr_vect, type r */
typedef struct {
unsigned int watchdog0 : 1;
unsigned int watchdog1 : 1;
unsigned int dummy1 : 30;
} reg_intr_vect_r_nmi;
#define REG_RD_ADDR_intr_vect_r_nmi 64
/* Register r_guru, scope intr_vect, type r */
typedef struct {
unsigned int jtag : 1;
unsigned int dummy1 : 31;
} reg_intr_vect_r_guru;
#define REG_RD_ADDR_intr_vect_r_guru 68
/* Register rw_ipi, scope intr_vect, type rw */
typedef struct
{
unsigned int vector;
} reg_intr_vect_rw_ipi;
#define REG_RD_ADDR_intr_vect_rw_ipi 72
#define REG_WR_ADDR_intr_vect_rw_ipi 72
/* Constants */
enum {
regk_intr_vect_no = 0x00000000,
regk_intr_vect_rw_mask0_default = 0x00000000,
regk_intr_vect_rw_mask1_default = 0x00000000,
regk_intr_vect_rw_xmask0_default = 0x00000000,
regk_intr_vect_rw_xmask1_default = 0x00000000,
regk_intr_vect_rw_xmask_ctrl_default = 0x00000000,
regk_intr_vect_yes = 0x00000001
};
#endif /* __intr_vect_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h Normal file
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/* Autogenerated Changes here will be lost!
* generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
*/
#define iop_version 0
#define iop_fifo_in_extra 64
#define iop_fifo_out_extra 128
#define iop_trigger_grp0 192
#define iop_trigger_grp1 256
#define iop_trigger_grp2 320
#define iop_trigger_grp3 384
#define iop_trigger_grp4 448
#define iop_trigger_grp5 512
#define iop_trigger_grp6 576
#define iop_trigger_grp7 640
#define iop_crc_par 768
#define iop_dmc_in 896
#define iop_dmc_out 1024
#define iop_fifo_in 1152
#define iop_fifo_out 1280
#define iop_scrc_in 1408
#define iop_scrc_out 1536
#define iop_timer_grp0 1664
#define iop_timer_grp1 1792
#define iop_sap_in 2048
#define iop_sap_out 2304
#define iop_spu 2560
#define iop_sw_cfg 2816
#define iop_sw_cpu 3072
#define iop_sw_mpu 3328
#define iop_sw_spu 3584
#define iop_mpu 4096

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h Normal file
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#ifndef __iop_sap_in_defs_asm_h
#define __iop_sap_in_defs_asm_h
/*
* This file is autogenerated from
* file: iop_sap_in.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
#define STRIDE_iop_sap_in_rw_bus_byte 4
/* Register rw_bus_byte, scope iop_sap_in, type rw */
#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
#define reg_iop_sap_in_rw_bus_byte___delay___width 2
#define reg_iop_sap_in_rw_bus_byte_offset 0
#define STRIDE_iop_sap_in_rw_gio 4
/* Register rw_gio, scope iop_sap_in, type rw */
#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
#define reg_iop_sap_in_rw_gio___sync_sel___width 2
#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
#define reg_iop_sap_in_rw_gio___sync_edge___width 2
#define reg_iop_sap_in_rw_gio___delay___lsb 7
#define reg_iop_sap_in_rw_gio___delay___width 2
#define reg_iop_sap_in_rw_gio___logic___lsb 9
#define reg_iop_sap_in_rw_gio___logic___width 2
#define reg_iop_sap_in_rw_gio_offset 16
/* Constants */
#define regk_iop_sap_in_and 0x00000002
#define regk_iop_sap_in_ext_clk200 0x00000003
#define regk_iop_sap_in_gio0 0x00000000
#define regk_iop_sap_in_gio12 0x00000003
#define regk_iop_sap_in_gio16 0x00000004
#define regk_iop_sap_in_gio20 0x00000005
#define regk_iop_sap_in_gio24 0x00000006
#define regk_iop_sap_in_gio28 0x00000007
#define regk_iop_sap_in_gio4 0x00000001
#define regk_iop_sap_in_gio8 0x00000002
#define regk_iop_sap_in_inv 0x00000001
#define regk_iop_sap_in_neg 0x00000002
#define regk_iop_sap_in_no 0x00000000
#define regk_iop_sap_in_no_del_ext_clk200 0x00000002
#define regk_iop_sap_in_none 0x00000000
#define regk_iop_sap_in_one 0x00000001
#define regk_iop_sap_in_or 0x00000003
#define regk_iop_sap_in_pos 0x00000001
#define regk_iop_sap_in_pos_neg 0x00000003
#define regk_iop_sap_in_rw_bus_byte_default 0x00000000
#define regk_iop_sap_in_rw_bus_byte_size 0x00000004
#define regk_iop_sap_in_rw_gio_default 0x00000000
#define regk_iop_sap_in_rw_gio_size 0x00000020
#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000
#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001
#define regk_iop_sap_in_tmr_clk200 0x00000001
#define regk_iop_sap_in_two 0x00000002
#define regk_iop_sap_in_two_clk200 0x00000000
#endif /* __iop_sap_in_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h Normal file
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#ifndef __iop_sap_out_defs_asm_h
#define __iop_sap_out_defs_asm_h
/*
* This file is autogenerated from
* file: iop_sap_out.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_gen_gated, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated_offset 0
/* Register rw_bus, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2
#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4
#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4
#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6
#define reg_iop_sap_out_rw_bus___byte0_delay___width 1
#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6
#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7
#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9
#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11
#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11
#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12
#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12
#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13
#define reg_iop_sap_out_rw_bus___byte1_delay___width 1
#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13
#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14
#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16
#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18
#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18
#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19
#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19
#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20
#define reg_iop_sap_out_rw_bus___byte2_delay___width 1
#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20
#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21
#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2
#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23
#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2
#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25
#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1
#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25
#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26
#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26
#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27
#define reg_iop_sap_out_rw_bus___byte3_delay___width 1
#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27
#define reg_iop_sap_out_rw_bus_offset 4
/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9
#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20
#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2
#define reg_iop_sap_out_rw_bus_lo_oe_offset 8
/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9
#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20
#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2
#define reg_iop_sap_out_rw_bus_hi_oe_offset 12
#define STRIDE_iop_sap_out_rw_gio 4
/* Register rw_gio, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2
#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5
#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1
#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5
#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6
#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6
#define reg_iop_sap_out_rw_gio___out_delay___lsb 7
#define reg_iop_sap_out_rw_gio___out_delay___width 1
#define reg_iop_sap_out_rw_gio___out_delay___bit 7
#define reg_iop_sap_out_rw_gio___out_logic___lsb 8
#define reg_iop_sap_out_rw_gio___out_logic___width 2
#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10
#define reg_iop_sap_out_rw_gio___out_logic_src___width 2
#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12
#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15
#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2
#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1
#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17
#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18
#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18
#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19
#define reg_iop_sap_out_rw_gio___oe_delay___width 1
#define reg_iop_sap_out_rw_gio___oe_delay___bit 19
#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
#define reg_iop_sap_out_rw_gio___oe_logic___width 2
#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22
#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2
#define reg_iop_sap_out_rw_gio_offset 16
/* Constants */
#define regk_iop_sap_out_always 0x00000001
#define regk_iop_sap_out_and 0x00000002
#define regk_iop_sap_out_clk0 0x00000000
#define regk_iop_sap_out_clk1 0x00000001
#define regk_iop_sap_out_clk12 0x00000004
#define regk_iop_sap_out_clk200 0x00000000
#define regk_iop_sap_out_ext 0x00000002
#define regk_iop_sap_out_gated 0x00000003
#define regk_iop_sap_out_gio0 0x00000000
#define regk_iop_sap_out_gio1 0x00000000
#define regk_iop_sap_out_gio16 0x00000002
#define regk_iop_sap_out_gio17 0x00000002
#define regk_iop_sap_out_gio24 0x00000003
#define regk_iop_sap_out_gio25 0x00000003
#define regk_iop_sap_out_gio8 0x00000001
#define regk_iop_sap_out_gio9 0x00000001
#define regk_iop_sap_out_gio_out10 0x00000005
#define regk_iop_sap_out_gio_out18 0x00000006
#define regk_iop_sap_out_gio_out2 0x00000004
#define regk_iop_sap_out_gio_out26 0x00000007
#define regk_iop_sap_out_inv 0x00000001
#define regk_iop_sap_out_nand 0x00000003
#define regk_iop_sap_out_no 0x00000000
#define regk_iop_sap_out_none 0x00000000
#define regk_iop_sap_out_one 0x00000001
#define regk_iop_sap_out_rw_bus_default 0x00000000
#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000
#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000
#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
#define regk_iop_sap_out_rw_gio_default 0x00000000
#define regk_iop_sap_out_rw_gio_size 0x00000020
#define regk_iop_sap_out_spu_gio6 0x00000002
#define regk_iop_sap_out_spu_gio7 0x00000003
#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000
#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001
#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002
#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003
#define regk_iop_sap_out_tmr200 0x00000001
#define regk_iop_sap_out_yes 0x00000001
#endif /* __iop_sap_out_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h Normal file
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#ifndef __iop_sw_cfg_defs_asm_h
#define __iop_sw_cfg_defs_asm_h
/*
* This file is autogenerated from
* file: iop_sw_cfg.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0
/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4
/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8
/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12
/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16
/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20
/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24
/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28
/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32
/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36
/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40
/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1
#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0
#define reg_iop_sw_cfg_rw_spu_owner_offset 44
/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48
/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52
/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56
/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60
/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64
/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68
/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72
/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76
/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80
/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84
/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0
#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8
#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8
#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8
#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16
#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8
#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24
#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8
#define reg_iop_sw_cfg_rw_bus_mask_offset 88
/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1
#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3
#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92
/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
#define reg_iop_sw_cfg_rw_gio_mask_offset 96
/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100
/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6
#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8
#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10
#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12
#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14
#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16
#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18
#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20
#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22
#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
#define reg_iop_sw_cfg_rw_pinmapping_offset 104
/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2
#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108
/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112
/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116
/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120
/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124
/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128
/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132
/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136
/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140
/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0
#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1
#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0
#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1
#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1
#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1
#define reg_iop_sw_cfg_rw_spu_cfg_offset 144
/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148
/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152
/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156
/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0
#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4
#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4
#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2
#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6
#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3
#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9
#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2
#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11
#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4
#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160
/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164
/* Constants */
#define regk_iop_sw_cfg_a 0x00000001
#define regk_iop_sw_cfg_b 0x00000002
#define regk_iop_sw_cfg_bus 0x00000000
#define regk_iop_sw_cfg_bus_rot16 0x00000002
#define regk_iop_sw_cfg_bus_rot24 0x00000003
#define regk_iop_sw_cfg_bus_rot8 0x00000001
#define regk_iop_sw_cfg_clk12 0x00000000
#define regk_iop_sw_cfg_cpu 0x00000000
#define regk_iop_sw_cfg_gated_clk0 0x0000000e
#define regk_iop_sw_cfg_gated_clk1 0x0000000f
#define regk_iop_sw_cfg_gio0 0x00000004
#define regk_iop_sw_cfg_gio1 0x00000001
#define regk_iop_sw_cfg_gio2 0x00000005
#define regk_iop_sw_cfg_gio3 0x00000002
#define regk_iop_sw_cfg_gio4 0x00000006
#define regk_iop_sw_cfg_gio5 0x00000003
#define regk_iop_sw_cfg_gio6 0x00000007
#define regk_iop_sw_cfg_gio7 0x00000004
#define regk_iop_sw_cfg_gio_in18 0x00000002
#define regk_iop_sw_cfg_gio_in19 0x00000003
#define regk_iop_sw_cfg_gio_in20 0x00000004
#define regk_iop_sw_cfg_gio_in21 0x00000005
#define regk_iop_sw_cfg_gio_in26 0x00000006
#define regk_iop_sw_cfg_gio_in27 0x00000007
#define regk_iop_sw_cfg_gio_in4 0x00000000
#define regk_iop_sw_cfg_gio_in5 0x00000001
#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002
#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003
#define regk_iop_sw_cfg_mpu 0x00000001
#define regk_iop_sw_cfg_none 0x00000000
#define regk_iop_sw_cfg_pdp_out 0x00000001
#define regk_iop_sw_cfg_pdp_out_hi 0x00000001
#define regk_iop_sw_cfg_pdp_out_lo 0x00000000
#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000
#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000
#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555
#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
#define regk_iop_sw_cfg_sdp_out 0x00000004
#define regk_iop_sw_cfg_size16 0x00000002
#define regk_iop_sw_cfg_size24 0x00000003
#define regk_iop_sw_cfg_size32 0x00000004
#define regk_iop_sw_cfg_size8 0x00000001
#define regk_iop_sw_cfg_spu 0x00000002
#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002
#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002
#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003
#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003
#define regk_iop_sw_cfg_spu_g0 0x00000007
#define regk_iop_sw_cfg_spu_g1 0x00000007
#define regk_iop_sw_cfg_spu_g2 0x00000007
#define regk_iop_sw_cfg_spu_g3 0x00000007
#define regk_iop_sw_cfg_spu_g4 0x00000007
#define regk_iop_sw_cfg_spu_g5 0x00000007
#define regk_iop_sw_cfg_spu_g6 0x00000007
#define regk_iop_sw_cfg_spu_g7 0x00000007
#define regk_iop_sw_cfg_spu_gio0 0x00000000
#define regk_iop_sw_cfg_spu_gio1 0x00000001
#define regk_iop_sw_cfg_spu_gio5 0x00000005
#define regk_iop_sw_cfg_spu_gio6 0x00000006
#define regk_iop_sw_cfg_spu_gio7 0x00000007
#define regk_iop_sw_cfg_spu_gio_out0 0x00000008
#define regk_iop_sw_cfg_spu_gio_out1 0x00000009
#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a
#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b
#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c
#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d
#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e
#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f
#define regk_iop_sw_cfg_spu_gioout0 0x00000000
#define regk_iop_sw_cfg_spu_gioout1 0x00000000
#define regk_iop_sw_cfg_spu_gioout10 0x00000007
#define regk_iop_sw_cfg_spu_gioout11 0x00000007
#define regk_iop_sw_cfg_spu_gioout12 0x00000007
#define regk_iop_sw_cfg_spu_gioout13 0x00000007
#define regk_iop_sw_cfg_spu_gioout14 0x00000007
#define regk_iop_sw_cfg_spu_gioout15 0x00000007
#define regk_iop_sw_cfg_spu_gioout16 0x00000007
#define regk_iop_sw_cfg_spu_gioout17 0x00000007
#define regk_iop_sw_cfg_spu_gioout18 0x00000007
#define regk_iop_sw_cfg_spu_gioout19 0x00000007
#define regk_iop_sw_cfg_spu_gioout2 0x00000001
#define regk_iop_sw_cfg_spu_gioout20 0x00000007
#define regk_iop_sw_cfg_spu_gioout21 0x00000007
#define regk_iop_sw_cfg_spu_gioout22 0x00000007
#define regk_iop_sw_cfg_spu_gioout23 0x00000007
#define regk_iop_sw_cfg_spu_gioout24 0x00000007
#define regk_iop_sw_cfg_spu_gioout25 0x00000007
#define regk_iop_sw_cfg_spu_gioout26 0x00000007
#define regk_iop_sw_cfg_spu_gioout27 0x00000007
#define regk_iop_sw_cfg_spu_gioout28 0x00000007
#define regk_iop_sw_cfg_spu_gioout29 0x00000007
#define regk_iop_sw_cfg_spu_gioout3 0x00000001
#define regk_iop_sw_cfg_spu_gioout30 0x00000007
#define regk_iop_sw_cfg_spu_gioout31 0x00000007
#define regk_iop_sw_cfg_spu_gioout4 0x00000002
#define regk_iop_sw_cfg_spu_gioout5 0x00000002
#define regk_iop_sw_cfg_spu_gioout6 0x00000003
#define regk_iop_sw_cfg_spu_gioout7 0x00000003
#define regk_iop_sw_cfg_spu_gioout8 0x00000007
#define regk_iop_sw_cfg_spu_gioout9 0x00000007
#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003
#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
#define regk_iop_sw_cfg_timer_grp0 0x00000000
#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005
#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005
#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005
#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005
#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002
#define regk_iop_sw_cfg_timer_grp1 0x00000000
#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006
#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006
#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006
#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006
#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003
#define regk_iop_sw_cfg_trig0_0 0x00000000
#define regk_iop_sw_cfg_trig0_1 0x00000000
#define regk_iop_sw_cfg_trig0_2 0x00000000
#define regk_iop_sw_cfg_trig0_3 0x00000000
#define regk_iop_sw_cfg_trig1_0 0x00000000
#define regk_iop_sw_cfg_trig1_1 0x00000000
#define regk_iop_sw_cfg_trig1_2 0x00000000
#define regk_iop_sw_cfg_trig1_3 0x00000000
#define regk_iop_sw_cfg_trig2_0 0x00000001
#define regk_iop_sw_cfg_trig2_1 0x00000001
#define regk_iop_sw_cfg_trig2_2 0x00000001
#define regk_iop_sw_cfg_trig2_3 0x00000001
#define regk_iop_sw_cfg_trig3_0 0x00000001
#define regk_iop_sw_cfg_trig3_1 0x00000001
#define regk_iop_sw_cfg_trig3_2 0x00000001
#define regk_iop_sw_cfg_trig3_3 0x00000001
#define regk_iop_sw_cfg_trig4_0 0x00000002
#define regk_iop_sw_cfg_trig4_1 0x00000002
#define regk_iop_sw_cfg_trig4_2 0x00000002
#define regk_iop_sw_cfg_trig4_3 0x00000002
#define regk_iop_sw_cfg_trig5_0 0x00000002
#define regk_iop_sw_cfg_trig5_1 0x00000002
#define regk_iop_sw_cfg_trig5_2 0x00000002
#define regk_iop_sw_cfg_trig5_3 0x00000002
#define regk_iop_sw_cfg_trig6_0 0x00000003
#define regk_iop_sw_cfg_trig6_1 0x00000003
#define regk_iop_sw_cfg_trig6_2 0x00000003
#define regk_iop_sw_cfg_trig6_3 0x00000003
#define regk_iop_sw_cfg_trig7_0 0x00000003
#define regk_iop_sw_cfg_trig7_1 0x00000003
#define regk_iop_sw_cfg_trig7_2 0x00000003
#define regk_iop_sw_cfg_trig7_3 0x00000003
#endif /* __iop_sw_cfg_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h Normal file
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#ifndef __iop_sw_cpu_defs_asm_h
#define __iop_sw_cpu_defs_asm_h
/*
* This file is autogenerated from
* file: iop_sw_cpu.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_mpu_trace, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_mpu_trace_offset 0
/* Register r_spu_trace, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_spu_trace_offset 4
/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8
/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6
#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1
#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6
#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12
/* Register rw_mc_data, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
#define reg_iop_sw_cpu_rw_mc_data___val___width 32
#define reg_iop_sw_cpu_rw_mc_data_offset 16
/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_mc_addr_offset 20
/* Register rs_mc_data, scope iop_sw_cpu, type rs */
#define reg_iop_sw_cpu_rs_mc_data_offset 24
/* Register r_mc_data, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_mc_data_offset 28
/* Register r_mc_stat, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2
#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1
#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2
#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3
#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3
#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4
#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4
#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5
#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1
#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5
#define reg_iop_sw_cpu_r_mc_stat_offset 32
/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24
#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8
#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36
/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0
#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8
#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8
#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8
#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16
#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8
#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24
#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8
#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40
/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3
#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44
/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1
#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3
#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48
/* Register r_bus_in, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_bus_in_offset 52
/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56
/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60
/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64
/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68
/* Register r_gio_in, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_gio_in_offset 72
/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16
#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16
#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17
#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17
#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18
#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18
#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19
#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19
#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20
#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20
#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21
#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21
#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22
#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22
#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23
#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23
#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24
#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24
#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25
#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25
#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26
#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26
#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27
#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27
#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28
#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28
#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29
#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29
#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30
#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30
#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31
#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31
#define reg_iop_sw_cpu_rw_intr0_mask_offset 76
/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16
#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16
#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17
#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17
#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18
#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18
#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19
#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19
#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20
#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20
#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21
#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21
#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22
#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22
#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23
#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23
#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24
#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24
#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25
#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25
#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26
#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26
#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27
#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27
#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28
#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28
#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29
#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29
#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30
#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30
#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31
#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31
#define reg_iop_sw_cpu_rw_ack_intr0_offset 80
/* Register r_intr0, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16
#define reg_iop_sw_cpu_r_intr0___spu_0___width 1
#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16
#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17
#define reg_iop_sw_cpu_r_intr0___spu_1___width 1
#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17
#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18
#define reg_iop_sw_cpu_r_intr0___spu_2___width 1
#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18
#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19
#define reg_iop_sw_cpu_r_intr0___spu_3___width 1
#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19
#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20
#define reg_iop_sw_cpu_r_intr0___spu_4___width 1
#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20
#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21
#define reg_iop_sw_cpu_r_intr0___spu_5___width 1
#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21
#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22
#define reg_iop_sw_cpu_r_intr0___spu_6___width 1
#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22
#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23
#define reg_iop_sw_cpu_r_intr0___spu_7___width 1
#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23
#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24
#define reg_iop_sw_cpu_r_intr0___spu_8___width 1
#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24
#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25
#define reg_iop_sw_cpu_r_intr0___spu_9___width 1
#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25
#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26
#define reg_iop_sw_cpu_r_intr0___spu_10___width 1
#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26
#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27
#define reg_iop_sw_cpu_r_intr0___spu_11___width 1
#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27
#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28
#define reg_iop_sw_cpu_r_intr0___spu_12___width 1
#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28
#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29
#define reg_iop_sw_cpu_r_intr0___spu_13___width 1
#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29
#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30
#define reg_iop_sw_cpu_r_intr0___spu_14___width 1
#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30
#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31
#define reg_iop_sw_cpu_r_intr0___spu_15___width 1
#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31
#define reg_iop_sw_cpu_r_intr0_offset 84
/* Register r_masked_intr0, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16
#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16
#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17
#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17
#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18
#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18
#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19
#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19
#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20
#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20
#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21
#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21
#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22
#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22
#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23
#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23
#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24
#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24
#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25
#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25
#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26
#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26
#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27
#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27
#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28
#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28
#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29
#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29
#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30
#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30
#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31
#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1
#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31
#define reg_iop_sw_cpu_r_masked_intr0_offset 88
/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16
#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16
#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17
#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29
#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30
#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30
#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31
#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1
#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31
#define reg_iop_sw_cpu_rw_intr1_mask_offset 92
/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_rw_ack_intr1_offset 96
/* Register r_intr1, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16
#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1
#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16
#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17
#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1
#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17
#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18
#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18
#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19
#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19
#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20
#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20
#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21
#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1
#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21
#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22
#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22
#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23
#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23
#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24
#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24
#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25
#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25
#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26
#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26
#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27
#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27
#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28
#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28
#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29
#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1
#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29
#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30
#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1
#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30
#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31
#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1
#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31
#define reg_iop_sw_cpu_r_intr1_offset 100
/* Register r_masked_intr1, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16
#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1
#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16
#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17
#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1
#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1
#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1
#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1
#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31
#define reg_iop_sw_cpu_r_masked_intr1_offset 104
/* Constants */
#define regk_iop_sw_cpu_copy 0x00000000
#define regk_iop_sw_cpu_no 0x00000000
#define regk_iop_sw_cpu_rd 0x00000002
#define regk_iop_sw_cpu_reg_copy 0x00000001
#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
#define regk_iop_sw_cpu_wr 0x00000003
#define regk_iop_sw_cpu_yes 0x00000001
#endif /* __iop_sw_cpu_defs_asm_h */

1086
include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h Normal file
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523
include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h Normal file
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#ifndef __iop_sw_spu_defs_asm_h
#define __iop_sw_spu_defs_asm_h
/*
* This file is autogenerated from
* file: iop_sw_spu.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_mpu_trace, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_mpu_trace_offset 0
/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6
#define reg_iop_sw_spu_rw_mc_ctrl_offset 4
/* Register rw_mc_data, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
#define reg_iop_sw_spu_rw_mc_data___val___width 32
#define reg_iop_sw_spu_rw_mc_data_offset 8
/* Register rw_mc_addr, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mc_addr_offset 12
/* Register rs_mc_data, scope iop_sw_spu, type rs */
#define reg_iop_sw_spu_rs_mc_data_offset 16
/* Register r_mc_data, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_mc_data_offset 20
/* Register r_mc_stat, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2
#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1
#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2
#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3
#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3
#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4
#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5
#define reg_iop_sw_spu_r_mc_stat_offset 24
/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16
#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24
#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28
/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8
#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8
#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16
#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8
#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24
#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8
#define reg_iop_sw_spu_rw_bus_set_mask_offset 32
/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1
#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3
#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36
/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1
#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3
#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40
/* Register r_bus_in, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_bus_in_offset 44
/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48
/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_set_mask_offset 52
/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56
/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60
/* Register r_gio_in, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_gio_in_offset 64
/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68
/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0
#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8
#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8
#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72
/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8
#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8
#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76
/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0
#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8
#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8
#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8
#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80
/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84
/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88
/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92
/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96
/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100
/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104
/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108
/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112
/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
#define reg_iop_sw_spu_rw_cpu_intr_offset 116
/* Register r_cpu_intr, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
#define reg_iop_sw_spu_r_cpu_intr_offset 120
/* Register r_hw_intr, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10
#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10
#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11
#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11
#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12
#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12
#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13
#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13
#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14
#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1
#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14
#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15
#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1
#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15
#define reg_iop_sw_spu_r_hw_intr_offset 124
/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
#define reg_iop_sw_spu_rw_mpu_intr_offset 128
/* Register r_mpu_intr, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
#define reg_iop_sw_spu_r_mpu_intr_offset 132
/* Constants */
#define regk_iop_sw_spu_copy 0x00000000
#define regk_iop_sw_spu_no 0x00000000
#define regk_iop_sw_spu_nop 0x00000000
#define regk_iop_sw_spu_rd 0x00000002
#define regk_iop_sw_spu_reg_copy 0x00000001
#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
#define regk_iop_sw_spu_set 0x00000001
#define regk_iop_sw_spu_wr 0x00000003
#define regk_iop_sw_spu_yes 0x00000001
#endif /* __iop_sw_spu_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h Normal file
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#ifndef __iop_version_defs_asm_h
#define __iop_version_defs_asm_h
/*
* This file is autogenerated from
* file: iop_version.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_version, scope iop_version, type r */
#define reg_iop_version_r_version___nr___lsb 0
#define reg_iop_version_r_version___nr___width 8
#define reg_iop_version_r_version_offset 0
/* Constants */
#define regk_iop_version_v2_0 0x00000002
#endif /* __iop_version_defs_asm_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h Normal file
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/* Autogenerated Changes here will be lost!
* generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
*/
#define regi_iop_version (regi_iop + 0)
#define regi_iop_fifo_in_extra (regi_iop + 64)
#define regi_iop_fifo_out_extra (regi_iop + 128)
#define regi_iop_trigger_grp0 (regi_iop + 192)
#define regi_iop_trigger_grp1 (regi_iop + 256)
#define regi_iop_trigger_grp2 (regi_iop + 320)
#define regi_iop_trigger_grp3 (regi_iop + 384)
#define regi_iop_trigger_grp4 (regi_iop + 448)
#define regi_iop_trigger_grp5 (regi_iop + 512)
#define regi_iop_trigger_grp6 (regi_iop + 576)
#define regi_iop_trigger_grp7 (regi_iop + 640)
#define regi_iop_crc_par (regi_iop + 768)
#define regi_iop_dmc_in (regi_iop + 896)
#define regi_iop_dmc_out (regi_iop + 1024)
#define regi_iop_fifo_in (regi_iop + 1152)
#define regi_iop_fifo_out (regi_iop + 1280)
#define regi_iop_scrc_in (regi_iop + 1408)
#define regi_iop_scrc_out (regi_iop + 1536)
#define regi_iop_timer_grp0 (regi_iop + 1664)
#define regi_iop_timer_grp1 (regi_iop + 1792)
#define regi_iop_sap_in (regi_iop + 2048)
#define regi_iop_sap_out (regi_iop + 2304)
#define regi_iop_spu (regi_iop + 2560)
#define regi_iop_sw_cfg (regi_iop + 2816)
#define regi_iop_sw_cpu (regi_iop + 3072)
#define regi_iop_sw_mpu (regi_iop + 3328)
#define regi_iop_sw_spu (regi_iop + 3584)
#define regi_iop_mpu (regi_iop + 4096)

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h Normal file
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#ifndef __iop_sap_in_defs_h
#define __iop_sap_in_defs_h
/*
* This file is autogenerated from
* file: iop_sap_in.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_sap_in */
#define STRIDE_iop_sap_in_rw_bus_byte 4
/* Register rw_bus_byte, scope iop_sap_in, type rw */
typedef struct {
unsigned int sync_sel : 2;
unsigned int sync_ext_src : 3;
unsigned int sync_edge : 2;
unsigned int delay : 2;
unsigned int dummy1 : 23;
} reg_iop_sap_in_rw_bus_byte;
#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
#define STRIDE_iop_sap_in_rw_gio 4
/* Register rw_gio, scope iop_sap_in, type rw */
typedef struct {
unsigned int sync_sel : 2;
unsigned int sync_ext_src : 3;
unsigned int sync_edge : 2;
unsigned int delay : 2;
unsigned int logic : 2;
unsigned int dummy1 : 21;
} reg_iop_sap_in_rw_gio;
#define REG_RD_ADDR_iop_sap_in_rw_gio 16
#define REG_WR_ADDR_iop_sap_in_rw_gio 16
/* Constants */
enum {
regk_iop_sap_in_and = 0x00000002,
regk_iop_sap_in_ext_clk200 = 0x00000003,
regk_iop_sap_in_gio0 = 0x00000000,
regk_iop_sap_in_gio12 = 0x00000003,
regk_iop_sap_in_gio16 = 0x00000004,
regk_iop_sap_in_gio20 = 0x00000005,
regk_iop_sap_in_gio24 = 0x00000006,
regk_iop_sap_in_gio28 = 0x00000007,
regk_iop_sap_in_gio4 = 0x00000001,
regk_iop_sap_in_gio8 = 0x00000002,
regk_iop_sap_in_inv = 0x00000001,
regk_iop_sap_in_neg = 0x00000002,
regk_iop_sap_in_no = 0x00000000,
regk_iop_sap_in_no_del_ext_clk200 = 0x00000002,
regk_iop_sap_in_none = 0x00000000,
regk_iop_sap_in_one = 0x00000001,
regk_iop_sap_in_or = 0x00000003,
regk_iop_sap_in_pos = 0x00000001,
regk_iop_sap_in_pos_neg = 0x00000003,
regk_iop_sap_in_rw_bus_byte_default = 0x00000000,
regk_iop_sap_in_rw_bus_byte_size = 0x00000004,
regk_iop_sap_in_rw_gio_default = 0x00000000,
regk_iop_sap_in_rw_gio_size = 0x00000020,
regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000,
regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001,
regk_iop_sap_in_tmr_clk200 = 0x00000001,
regk_iop_sap_in_two = 0x00000002,
regk_iop_sap_in_two_clk200 = 0x00000000
};
#endif /* __iop_sap_in_defs_h */

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#ifndef __iop_sap_out_defs_h
#define __iop_sap_out_defs_h
/*
* This file is autogenerated from
* file: iop_sap_out.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_sap_out */
/* Register rw_gen_gated, scope iop_sap_out, type rw */
typedef struct {
unsigned int clk0_src : 2;
unsigned int clk0_gate_src : 2;
unsigned int clk0_force_src : 3;
unsigned int clk1_src : 2;
unsigned int clk1_gate_src : 2;
unsigned int clk1_force_src : 3;
unsigned int dummy1 : 18;
} reg_iop_sap_out_rw_gen_gated;
#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
/* Register rw_bus, scope iop_sap_out, type rw */
typedef struct {
unsigned int byte0_clk_sel : 2;
unsigned int byte0_clk_ext : 2;
unsigned int byte0_gated_clk : 1;
unsigned int byte0_clk_inv : 1;
unsigned int byte0_delay : 1;
unsigned int byte1_clk_sel : 2;
unsigned int byte1_clk_ext : 2;
unsigned int byte1_gated_clk : 1;
unsigned int byte1_clk_inv : 1;
unsigned int byte1_delay : 1;
unsigned int byte2_clk_sel : 2;
unsigned int byte2_clk_ext : 2;
unsigned int byte2_gated_clk : 1;
unsigned int byte2_clk_inv : 1;
unsigned int byte2_delay : 1;
unsigned int byte3_clk_sel : 2;
unsigned int byte3_clk_ext : 2;
unsigned int byte3_gated_clk : 1;
unsigned int byte3_clk_inv : 1;
unsigned int byte3_delay : 1;
unsigned int dummy1 : 4;
} reg_iop_sap_out_rw_bus;
#define REG_RD_ADDR_iop_sap_out_rw_bus 4
#define REG_WR_ADDR_iop_sap_out_rw_bus 4
/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
typedef struct {
unsigned int byte0_clk_sel : 2;
unsigned int byte0_clk_ext : 2;
unsigned int byte0_gated_clk : 1;
unsigned int byte0_clk_inv : 1;
unsigned int byte0_delay : 1;
unsigned int byte0_logic : 2;
unsigned int byte0_logic_src : 2;
unsigned int byte1_clk_sel : 2;
unsigned int byte1_clk_ext : 2;
unsigned int byte1_gated_clk : 1;
unsigned int byte1_clk_inv : 1;
unsigned int byte1_delay : 1;
unsigned int byte1_logic : 2;
unsigned int byte1_logic_src : 2;
unsigned int dummy1 : 10;
} reg_iop_sap_out_rw_bus_lo_oe;
#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8
#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8
/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
typedef struct {
unsigned int byte2_clk_sel : 2;
unsigned int byte2_clk_ext : 2;
unsigned int byte2_gated_clk : 1;
unsigned int byte2_clk_inv : 1;
unsigned int byte2_delay : 1;
unsigned int byte2_logic : 2;
unsigned int byte2_logic_src : 2;
unsigned int byte3_clk_sel : 2;
unsigned int byte3_clk_ext : 2;
unsigned int byte3_gated_clk : 1;
unsigned int byte3_clk_inv : 1;
unsigned int byte3_delay : 1;
unsigned int byte3_logic : 2;
unsigned int byte3_logic_src : 2;
unsigned int dummy1 : 10;
} reg_iop_sap_out_rw_bus_hi_oe;
#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12
#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12
#define STRIDE_iop_sap_out_rw_gio 4
/* Register rw_gio, scope iop_sap_out, type rw */
typedef struct {
unsigned int out_clk_sel : 3;
unsigned int out_clk_ext : 2;
unsigned int out_gated_clk : 1;
unsigned int out_clk_inv : 1;
unsigned int out_delay : 1;
unsigned int out_logic : 2;
unsigned int out_logic_src : 2;
unsigned int oe_clk_sel : 3;
unsigned int oe_clk_ext : 2;
unsigned int oe_gated_clk : 1;
unsigned int oe_clk_inv : 1;
unsigned int oe_delay : 1;
unsigned int oe_logic : 2;
unsigned int oe_logic_src : 2;
unsigned int dummy1 : 8;
} reg_iop_sap_out_rw_gio;
#define REG_RD_ADDR_iop_sap_out_rw_gio 16
#define REG_WR_ADDR_iop_sap_out_rw_gio 16
/* Constants */
enum {
regk_iop_sap_out_always = 0x00000001,
regk_iop_sap_out_and = 0x00000002,
regk_iop_sap_out_clk0 = 0x00000000,
regk_iop_sap_out_clk1 = 0x00000001,
regk_iop_sap_out_clk12 = 0x00000004,
regk_iop_sap_out_clk200 = 0x00000000,
regk_iop_sap_out_ext = 0x00000002,
regk_iop_sap_out_gated = 0x00000003,
regk_iop_sap_out_gio0 = 0x00000000,
regk_iop_sap_out_gio1 = 0x00000000,
regk_iop_sap_out_gio16 = 0x00000002,
regk_iop_sap_out_gio17 = 0x00000002,
regk_iop_sap_out_gio24 = 0x00000003,
regk_iop_sap_out_gio25 = 0x00000003,
regk_iop_sap_out_gio8 = 0x00000001,
regk_iop_sap_out_gio9 = 0x00000001,
regk_iop_sap_out_gio_out10 = 0x00000005,
regk_iop_sap_out_gio_out18 = 0x00000006,
regk_iop_sap_out_gio_out2 = 0x00000004,
regk_iop_sap_out_gio_out26 = 0x00000007,
regk_iop_sap_out_inv = 0x00000001,
regk_iop_sap_out_nand = 0x00000003,
regk_iop_sap_out_no = 0x00000000,
regk_iop_sap_out_none = 0x00000000,
regk_iop_sap_out_one = 0x00000001,
regk_iop_sap_out_rw_bus_default = 0x00000000,
regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000,
regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000,
regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
regk_iop_sap_out_rw_gio_default = 0x00000000,
regk_iop_sap_out_rw_gio_size = 0x00000020,
regk_iop_sap_out_spu_gio6 = 0x00000002,
regk_iop_sap_out_spu_gio7 = 0x00000003,
regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000,
regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001,
regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002,
regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003,
regk_iop_sap_out_tmr200 = 0x00000001,
regk_iop_sap_out_yes = 0x00000001
};
#endif /* __iop_sap_out_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h Normal file
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#ifndef __iop_sw_cfg_defs_h
#define __iop_sw_cfg_defs_h
/*
* This file is autogenerated from
* file: iop_sw_cfg.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_sw_cfg */
/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_crc_par_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0
#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0
/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_sap_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28
#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28
/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_sap_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32
#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32
/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 1;
unsigned int dummy1 : 31;
} reg_iop_sw_cfg_rw_spu_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44
#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44
/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp2_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp3_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp4_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp5_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp6_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp7_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int byte2 : 8;
unsigned int byte3 : 8;
} reg_iop_sw_cfg_rw_bus_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88
#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88
/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int byte0 : 1;
unsigned int byte1 : 1;
unsigned int byte2 : 1;
unsigned int byte3 : 1;
unsigned int dummy1 : 28;
} reg_iop_sw_cfg_rw_bus_oe_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_cfg_rw_gio_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96
/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_cfg_rw_gio_oe_mask;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int bus_byte0 : 2;
unsigned int bus_byte1 : 2;
unsigned int bus_byte2 : 2;
unsigned int bus_byte3 : 2;
unsigned int gio3_0 : 2;
unsigned int gio7_4 : 2;
unsigned int gio11_8 : 2;
unsigned int gio15_12 : 2;
unsigned int gio19_16 : 2;
unsigned int gio23_20 : 2;
unsigned int gio27_24 : 2;
unsigned int gio31_28 : 2;
unsigned int dummy1 : 8;
} reg_iop_sw_cfg_rw_pinmapping;
#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104
#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104
/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int bus_lo : 2;
unsigned int bus_hi : 2;
unsigned int bus_lo_oe : 2;
unsigned int bus_hi_oe : 2;
unsigned int dummy1 : 24;
} reg_iop_sw_cfg_rw_bus_out_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio0 : 3;
unsigned int gio0_oe : 1;
unsigned int gio1 : 3;
unsigned int gio1_oe : 1;
unsigned int gio2 : 3;
unsigned int gio2_oe : 1;
unsigned int gio3 : 3;
unsigned int gio3_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio4 : 3;
unsigned int gio4_oe : 1;
unsigned int gio5 : 3;
unsigned int gio5_oe : 1;
unsigned int gio6 : 3;
unsigned int gio6_oe : 1;
unsigned int gio7 : 3;
unsigned int gio7_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio8 : 3;
unsigned int gio8_oe : 1;
unsigned int gio9 : 3;
unsigned int gio9_oe : 1;
unsigned int gio10 : 3;
unsigned int gio10_oe : 1;
unsigned int gio11 : 3;
unsigned int gio11_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio12 : 3;
unsigned int gio12_oe : 1;
unsigned int gio13 : 3;
unsigned int gio13_oe : 1;
unsigned int gio14 : 3;
unsigned int gio14_oe : 1;
unsigned int gio15 : 3;
unsigned int gio15_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio16 : 3;
unsigned int gio16_oe : 1;
unsigned int gio17 : 3;
unsigned int gio17_oe : 1;
unsigned int gio18 : 3;
unsigned int gio18_oe : 1;
unsigned int gio19 : 3;
unsigned int gio19_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio20 : 3;
unsigned int gio20_oe : 1;
unsigned int gio21 : 3;
unsigned int gio21_oe : 1;
unsigned int gio22 : 3;
unsigned int gio22_oe : 1;
unsigned int gio23 : 3;
unsigned int gio23_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio24 : 3;
unsigned int gio24_oe : 1;
unsigned int gio25 : 3;
unsigned int gio25_oe : 1;
unsigned int gio26 : 3;
unsigned int gio26_oe : 1;
unsigned int gio27 : 3;
unsigned int gio27_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int gio28 : 3;
unsigned int gio28_oe : 1;
unsigned int gio29 : 3;
unsigned int gio29_oe : 1;
unsigned int gio30 : 3;
unsigned int gio30_oe : 1;
unsigned int gio31 : 3;
unsigned int gio31_oe : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int bus0_in : 1;
unsigned int bus1_in : 1;
unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_spu_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144
#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144
/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int ext_clk : 3;
unsigned int tmr0_en : 2;
unsigned int tmr1_en : 2;
unsigned int tmr2_en : 2;
unsigned int tmr3_en : 2;
unsigned int tmr0_dis : 2;
unsigned int tmr1_dis : 2;
unsigned int tmr2_dis : 2;
unsigned int tmr3_dis : 2;
unsigned int dummy1 : 13;
} reg_iop_sw_cfg_rw_timer_grp0_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int ext_clk : 3;
unsigned int tmr0_en : 2;
unsigned int tmr1_en : 2;
unsigned int tmr2_en : 2;
unsigned int tmr3_en : 2;
unsigned int tmr0_dis : 2;
unsigned int tmr1_dis : 2;
unsigned int tmr2_dis : 2;
unsigned int tmr3_dis : 2;
unsigned int dummy1 : 13;
} reg_iop_sw_cfg_rw_timer_grp1_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int grp0_dis : 1;
unsigned int grp0_en : 1;
unsigned int grp1_dis : 1;
unsigned int grp1_en : 1;
unsigned int grp2_dis : 1;
unsigned int grp2_en : 1;
unsigned int grp3_dis : 1;
unsigned int grp3_en : 1;
unsigned int grp4_dis : 1;
unsigned int grp4_en : 1;
unsigned int grp5_dis : 1;
unsigned int grp5_en : 1;
unsigned int grp6_dis : 1;
unsigned int grp6_en : 1;
unsigned int grp7_dis : 1;
unsigned int grp7_en : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cfg_rw_trigger_grps_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int out_strb : 4;
unsigned int in_src : 2;
unsigned int in_size : 3;
unsigned int in_last : 2;
unsigned int in_strb : 4;
unsigned int dummy1 : 17;
} reg_iop_sw_cfg_rw_pdp_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160
#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160
/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
typedef struct {
unsigned int sdp_out_strb : 3;
unsigned int sdp_in_data : 3;
unsigned int sdp_in_last : 2;
unsigned int sdp_in_strb : 3;
unsigned int dummy1 : 21;
} reg_iop_sw_cfg_rw_sdp_cfg;
#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164
#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164
/* Constants */
enum {
regk_iop_sw_cfg_a = 0x00000001,
regk_iop_sw_cfg_b = 0x00000002,
regk_iop_sw_cfg_bus = 0x00000000,
regk_iop_sw_cfg_bus_rot16 = 0x00000002,
regk_iop_sw_cfg_bus_rot24 = 0x00000003,
regk_iop_sw_cfg_bus_rot8 = 0x00000001,
regk_iop_sw_cfg_clk12 = 0x00000000,
regk_iop_sw_cfg_cpu = 0x00000000,
regk_iop_sw_cfg_gated_clk0 = 0x0000000e,
regk_iop_sw_cfg_gated_clk1 = 0x0000000f,
regk_iop_sw_cfg_gio0 = 0x00000004,
regk_iop_sw_cfg_gio1 = 0x00000001,
regk_iop_sw_cfg_gio2 = 0x00000005,
regk_iop_sw_cfg_gio3 = 0x00000002,
regk_iop_sw_cfg_gio4 = 0x00000006,
regk_iop_sw_cfg_gio5 = 0x00000003,
regk_iop_sw_cfg_gio6 = 0x00000007,
regk_iop_sw_cfg_gio7 = 0x00000004,
regk_iop_sw_cfg_gio_in18 = 0x00000002,
regk_iop_sw_cfg_gio_in19 = 0x00000003,
regk_iop_sw_cfg_gio_in20 = 0x00000004,
regk_iop_sw_cfg_gio_in21 = 0x00000005,
regk_iop_sw_cfg_gio_in26 = 0x00000006,
regk_iop_sw_cfg_gio_in27 = 0x00000007,
regk_iop_sw_cfg_gio_in4 = 0x00000000,
regk_iop_sw_cfg_gio_in5 = 0x00000001,
regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002,
regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003,
regk_iop_sw_cfg_mpu = 0x00000001,
regk_iop_sw_cfg_none = 0x00000000,
regk_iop_sw_cfg_pdp_out = 0x00000001,
regk_iop_sw_cfg_pdp_out_hi = 0x00000001,
regk_iop_sw_cfg_pdp_out_lo = 0x00000000,
regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000,
regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000,
regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555,
regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
regk_iop_sw_cfg_sdp_out = 0x00000004,
regk_iop_sw_cfg_size16 = 0x00000002,
regk_iop_sw_cfg_size24 = 0x00000003,
regk_iop_sw_cfg_size32 = 0x00000004,
regk_iop_sw_cfg_size8 = 0x00000001,
regk_iop_sw_cfg_spu = 0x00000002,
regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002,
regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002,
regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003,
regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003,
regk_iop_sw_cfg_spu_g0 = 0x00000007,
regk_iop_sw_cfg_spu_g1 = 0x00000007,
regk_iop_sw_cfg_spu_g2 = 0x00000007,
regk_iop_sw_cfg_spu_g3 = 0x00000007,
regk_iop_sw_cfg_spu_g4 = 0x00000007,
regk_iop_sw_cfg_spu_g5 = 0x00000007,
regk_iop_sw_cfg_spu_g6 = 0x00000007,
regk_iop_sw_cfg_spu_g7 = 0x00000007,
regk_iop_sw_cfg_spu_gio0 = 0x00000000,
regk_iop_sw_cfg_spu_gio1 = 0x00000001,
regk_iop_sw_cfg_spu_gio5 = 0x00000005,
regk_iop_sw_cfg_spu_gio6 = 0x00000006,
regk_iop_sw_cfg_spu_gio7 = 0x00000007,
regk_iop_sw_cfg_spu_gio_out0 = 0x00000008,
regk_iop_sw_cfg_spu_gio_out1 = 0x00000009,
regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a,
regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b,
regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c,
regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d,
regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e,
regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f,
regk_iop_sw_cfg_spu_gioout0 = 0x00000000,
regk_iop_sw_cfg_spu_gioout1 = 0x00000000,
regk_iop_sw_cfg_spu_gioout10 = 0x00000007,
regk_iop_sw_cfg_spu_gioout11 = 0x00000007,
regk_iop_sw_cfg_spu_gioout12 = 0x00000007,
regk_iop_sw_cfg_spu_gioout13 = 0x00000007,
regk_iop_sw_cfg_spu_gioout14 = 0x00000007,
regk_iop_sw_cfg_spu_gioout15 = 0x00000007,
regk_iop_sw_cfg_spu_gioout16 = 0x00000007,
regk_iop_sw_cfg_spu_gioout17 = 0x00000007,
regk_iop_sw_cfg_spu_gioout18 = 0x00000007,
regk_iop_sw_cfg_spu_gioout19 = 0x00000007,
regk_iop_sw_cfg_spu_gioout2 = 0x00000001,
regk_iop_sw_cfg_spu_gioout20 = 0x00000007,
regk_iop_sw_cfg_spu_gioout21 = 0x00000007,
regk_iop_sw_cfg_spu_gioout22 = 0x00000007,
regk_iop_sw_cfg_spu_gioout23 = 0x00000007,
regk_iop_sw_cfg_spu_gioout24 = 0x00000007,
regk_iop_sw_cfg_spu_gioout25 = 0x00000007,
regk_iop_sw_cfg_spu_gioout26 = 0x00000007,
regk_iop_sw_cfg_spu_gioout27 = 0x00000007,
regk_iop_sw_cfg_spu_gioout28 = 0x00000007,
regk_iop_sw_cfg_spu_gioout29 = 0x00000007,
regk_iop_sw_cfg_spu_gioout3 = 0x00000001,
regk_iop_sw_cfg_spu_gioout30 = 0x00000007,
regk_iop_sw_cfg_spu_gioout31 = 0x00000007,
regk_iop_sw_cfg_spu_gioout4 = 0x00000002,
regk_iop_sw_cfg_spu_gioout5 = 0x00000002,
regk_iop_sw_cfg_spu_gioout6 = 0x00000003,
regk_iop_sw_cfg_spu_gioout7 = 0x00000003,
regk_iop_sw_cfg_spu_gioout8 = 0x00000007,
regk_iop_sw_cfg_spu_gioout9 = 0x00000007,
regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003,
regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
regk_iop_sw_cfg_timer_grp0 = 0x00000000,
regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005,
regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005,
regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005,
regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005,
regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002,
regk_iop_sw_cfg_timer_grp1 = 0x00000000,
regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006,
regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006,
regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006,
regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006,
regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003,
regk_iop_sw_cfg_trig0_0 = 0x00000000,
regk_iop_sw_cfg_trig0_1 = 0x00000000,
regk_iop_sw_cfg_trig0_2 = 0x00000000,
regk_iop_sw_cfg_trig0_3 = 0x00000000,
regk_iop_sw_cfg_trig1_0 = 0x00000000,
regk_iop_sw_cfg_trig1_1 = 0x00000000,
regk_iop_sw_cfg_trig1_2 = 0x00000000,
regk_iop_sw_cfg_trig1_3 = 0x00000000,
regk_iop_sw_cfg_trig2_0 = 0x00000001,
regk_iop_sw_cfg_trig2_1 = 0x00000001,
regk_iop_sw_cfg_trig2_2 = 0x00000001,
regk_iop_sw_cfg_trig2_3 = 0x00000001,
regk_iop_sw_cfg_trig3_0 = 0x00000001,
regk_iop_sw_cfg_trig3_1 = 0x00000001,
regk_iop_sw_cfg_trig3_2 = 0x00000001,
regk_iop_sw_cfg_trig3_3 = 0x00000001,
regk_iop_sw_cfg_trig4_0 = 0x00000002,
regk_iop_sw_cfg_trig4_1 = 0x00000002,
regk_iop_sw_cfg_trig4_2 = 0x00000002,
regk_iop_sw_cfg_trig4_3 = 0x00000002,
regk_iop_sw_cfg_trig5_0 = 0x00000002,
regk_iop_sw_cfg_trig5_1 = 0x00000002,
regk_iop_sw_cfg_trig5_2 = 0x00000002,
regk_iop_sw_cfg_trig5_3 = 0x00000002,
regk_iop_sw_cfg_trig6_0 = 0x00000003,
regk_iop_sw_cfg_trig6_1 = 0x00000003,
regk_iop_sw_cfg_trig6_2 = 0x00000003,
regk_iop_sw_cfg_trig6_3 = 0x00000003,
regk_iop_sw_cfg_trig7_0 = 0x00000003,
regk_iop_sw_cfg_trig7_1 = 0x00000003,
regk_iop_sw_cfg_trig7_2 = 0x00000003,
regk_iop_sw_cfg_trig7_3 = 0x00000003
};
#endif /* __iop_sw_cfg_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h Normal file
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#ifndef __iop_sw_cpu_defs_h
#define __iop_sw_cpu_defs_h
/*
* This file is autogenerated from
* file: iop_sw_cpu.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_sw_cpu */
/* Register r_mpu_trace, scope iop_sw_cpu, type r */
typedef unsigned int reg_iop_sw_cpu_r_mpu_trace;
#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0
/* Register r_spu_trace, scope iop_sw_cpu, type r */
typedef unsigned int reg_iop_sw_cpu_r_spu_trace;
#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4
/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace;
#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8
/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int keep_owner : 1;
unsigned int cmd : 2;
unsigned int size : 3;
unsigned int wr_spu_mem : 1;
unsigned int dummy1 : 25;
} reg_iop_sw_cpu_rw_mc_ctrl;
#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12
#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12
/* Register rw_mc_data, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_cpu_rw_mc_data;
#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16
#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16
/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20
#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20
/* Register rs_mc_data, scope iop_sw_cpu, type rs */
typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24
/* Register r_mc_data, scope iop_sw_cpu, type r */
typedef unsigned int reg_iop_sw_cpu_r_mc_data;
#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28
/* Register r_mc_stat, scope iop_sw_cpu, type r */
typedef struct {
unsigned int busy_cpu : 1;
unsigned int busy_mpu : 1;
unsigned int busy_spu : 1;
unsigned int owned_by_cpu : 1;
unsigned int owned_by_mpu : 1;
unsigned int owned_by_spu : 1;
unsigned int dummy1 : 26;
} reg_iop_sw_cpu_r_mc_stat;
#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32
/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int byte2 : 8;
unsigned int byte3 : 8;
} reg_iop_sw_cpu_rw_bus_clr_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int byte2 : 8;
unsigned int byte3 : 8;
} reg_iop_sw_cpu_rw_bus_set_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40
#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40
/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int byte0 : 1;
unsigned int byte1 : 1;
unsigned int byte2 : 1;
unsigned int byte3 : 1;
unsigned int dummy1 : 28;
} reg_iop_sw_cpu_rw_bus_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int byte0 : 1;
unsigned int byte1 : 1;
unsigned int byte2 : 1;
unsigned int byte3 : 1;
unsigned int dummy1 : 28;
} reg_iop_sw_cpu_rw_bus_oe_set_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
/* Register r_bus_in, scope iop_sw_cpu, type r */
typedef unsigned int reg_iop_sw_cpu_r_bus_in;
#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52
/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_cpu_rw_gio_clr_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_cpu_rw_gio_set_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60
#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60
/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_cpu_rw_gio_oe_set_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
/* Register r_gio_in, scope iop_sw_cpu, type r */
typedef unsigned int reg_iop_sw_cpu_r_gio_in;
#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72
/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int mpu_0 : 1;
unsigned int mpu_1 : 1;
unsigned int mpu_2 : 1;
unsigned int mpu_3 : 1;
unsigned int mpu_4 : 1;
unsigned int mpu_5 : 1;
unsigned int mpu_6 : 1;
unsigned int mpu_7 : 1;
unsigned int mpu_8 : 1;
unsigned int mpu_9 : 1;
unsigned int mpu_10 : 1;
unsigned int mpu_11 : 1;
unsigned int mpu_12 : 1;
unsigned int mpu_13 : 1;
unsigned int mpu_14 : 1;
unsigned int mpu_15 : 1;
unsigned int spu_0 : 1;
unsigned int spu_1 : 1;
unsigned int spu_2 : 1;
unsigned int spu_3 : 1;
unsigned int spu_4 : 1;
unsigned int spu_5 : 1;
unsigned int spu_6 : 1;
unsigned int spu_7 : 1;
unsigned int spu_8 : 1;
unsigned int spu_9 : 1;
unsigned int spu_10 : 1;
unsigned int spu_11 : 1;
unsigned int spu_12 : 1;
unsigned int spu_13 : 1;
unsigned int spu_14 : 1;
unsigned int spu_15 : 1;
} reg_iop_sw_cpu_rw_intr0_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76
#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76
/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int mpu_0 : 1;
unsigned int mpu_1 : 1;
unsigned int mpu_2 : 1;
unsigned int mpu_3 : 1;
unsigned int mpu_4 : 1;
unsigned int mpu_5 : 1;
unsigned int mpu_6 : 1;
unsigned int mpu_7 : 1;
unsigned int mpu_8 : 1;
unsigned int mpu_9 : 1;
unsigned int mpu_10 : 1;
unsigned int mpu_11 : 1;
unsigned int mpu_12 : 1;
unsigned int mpu_13 : 1;
unsigned int mpu_14 : 1;
unsigned int mpu_15 : 1;
unsigned int spu_0 : 1;
unsigned int spu_1 : 1;
unsigned int spu_2 : 1;
unsigned int spu_3 : 1;
unsigned int spu_4 : 1;
unsigned int spu_5 : 1;
unsigned int spu_6 : 1;
unsigned int spu_7 : 1;
unsigned int spu_8 : 1;
unsigned int spu_9 : 1;
unsigned int spu_10 : 1;
unsigned int spu_11 : 1;
unsigned int spu_12 : 1;
unsigned int spu_13 : 1;
unsigned int spu_14 : 1;
unsigned int spu_15 : 1;
} reg_iop_sw_cpu_rw_ack_intr0;
#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80
#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80
/* Register r_intr0, scope iop_sw_cpu, type r */
typedef struct {
unsigned int mpu_0 : 1;
unsigned int mpu_1 : 1;
unsigned int mpu_2 : 1;
unsigned int mpu_3 : 1;
unsigned int mpu_4 : 1;
unsigned int mpu_5 : 1;
unsigned int mpu_6 : 1;
unsigned int mpu_7 : 1;
unsigned int mpu_8 : 1;
unsigned int mpu_9 : 1;
unsigned int mpu_10 : 1;
unsigned int mpu_11 : 1;
unsigned int mpu_12 : 1;
unsigned int mpu_13 : 1;
unsigned int mpu_14 : 1;
unsigned int mpu_15 : 1;
unsigned int spu_0 : 1;
unsigned int spu_1 : 1;
unsigned int spu_2 : 1;
unsigned int spu_3 : 1;
unsigned int spu_4 : 1;
unsigned int spu_5 : 1;
unsigned int spu_6 : 1;
unsigned int spu_7 : 1;
unsigned int spu_8 : 1;
unsigned int spu_9 : 1;
unsigned int spu_10 : 1;
unsigned int spu_11 : 1;
unsigned int spu_12 : 1;
unsigned int spu_13 : 1;
unsigned int spu_14 : 1;
unsigned int spu_15 : 1;
} reg_iop_sw_cpu_r_intr0;
#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84
/* Register r_masked_intr0, scope iop_sw_cpu, type r */
typedef struct {
unsigned int mpu_0 : 1;
unsigned int mpu_1 : 1;
unsigned int mpu_2 : 1;
unsigned int mpu_3 : 1;
unsigned int mpu_4 : 1;
unsigned int mpu_5 : 1;
unsigned int mpu_6 : 1;
unsigned int mpu_7 : 1;
unsigned int mpu_8 : 1;
unsigned int mpu_9 : 1;
unsigned int mpu_10 : 1;
unsigned int mpu_11 : 1;
unsigned int mpu_12 : 1;
unsigned int mpu_13 : 1;
unsigned int mpu_14 : 1;
unsigned int mpu_15 : 1;
unsigned int spu_0 : 1;
unsigned int spu_1 : 1;
unsigned int spu_2 : 1;
unsigned int spu_3 : 1;
unsigned int spu_4 : 1;
unsigned int spu_5 : 1;
unsigned int spu_6 : 1;
unsigned int spu_7 : 1;
unsigned int spu_8 : 1;
unsigned int spu_9 : 1;
unsigned int spu_10 : 1;
unsigned int spu_11 : 1;
unsigned int spu_12 : 1;
unsigned int spu_13 : 1;
unsigned int spu_14 : 1;
unsigned int spu_15 : 1;
} reg_iop_sw_cpu_r_masked_intr0;
#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88
/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int mpu_16 : 1;
unsigned int mpu_17 : 1;
unsigned int mpu_18 : 1;
unsigned int mpu_19 : 1;
unsigned int mpu_20 : 1;
unsigned int mpu_21 : 1;
unsigned int mpu_22 : 1;
unsigned int mpu_23 : 1;
unsigned int mpu_24 : 1;
unsigned int mpu_25 : 1;
unsigned int mpu_26 : 1;
unsigned int mpu_27 : 1;
unsigned int mpu_28 : 1;
unsigned int mpu_29 : 1;
unsigned int mpu_30 : 1;
unsigned int mpu_31 : 1;
unsigned int dmc_in : 1;
unsigned int dmc_out : 1;
unsigned int fifo_in : 1;
unsigned int fifo_out : 1;
unsigned int fifo_in_extra : 1;
unsigned int fifo_out_extra : 1;
unsigned int trigger_grp0 : 1;
unsigned int trigger_grp1 : 1;
unsigned int trigger_grp2 : 1;
unsigned int trigger_grp3 : 1;
unsigned int trigger_grp4 : 1;
unsigned int trigger_grp5 : 1;
unsigned int trigger_grp6 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp0 : 1;
unsigned int timer_grp1 : 1;
} reg_iop_sw_cpu_rw_intr1_mask;
#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92
#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92
/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
typedef struct {
unsigned int mpu_16 : 1;
unsigned int mpu_17 : 1;
unsigned int mpu_18 : 1;
unsigned int mpu_19 : 1;
unsigned int mpu_20 : 1;
unsigned int mpu_21 : 1;
unsigned int mpu_22 : 1;
unsigned int mpu_23 : 1;
unsigned int mpu_24 : 1;
unsigned int mpu_25 : 1;
unsigned int mpu_26 : 1;
unsigned int mpu_27 : 1;
unsigned int mpu_28 : 1;
unsigned int mpu_29 : 1;
unsigned int mpu_30 : 1;
unsigned int mpu_31 : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_cpu_rw_ack_intr1;
#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96
#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96
/* Register r_intr1, scope iop_sw_cpu, type r */
typedef struct {
unsigned int mpu_16 : 1;
unsigned int mpu_17 : 1;
unsigned int mpu_18 : 1;
unsigned int mpu_19 : 1;
unsigned int mpu_20 : 1;
unsigned int mpu_21 : 1;
unsigned int mpu_22 : 1;
unsigned int mpu_23 : 1;
unsigned int mpu_24 : 1;
unsigned int mpu_25 : 1;
unsigned int mpu_26 : 1;
unsigned int mpu_27 : 1;
unsigned int mpu_28 : 1;
unsigned int mpu_29 : 1;
unsigned int mpu_30 : 1;
unsigned int mpu_31 : 1;
unsigned int dmc_in : 1;
unsigned int dmc_out : 1;
unsigned int fifo_in : 1;
unsigned int fifo_out : 1;
unsigned int fifo_in_extra : 1;
unsigned int fifo_out_extra : 1;
unsigned int trigger_grp0 : 1;
unsigned int trigger_grp1 : 1;
unsigned int trigger_grp2 : 1;
unsigned int trigger_grp3 : 1;
unsigned int trigger_grp4 : 1;
unsigned int trigger_grp5 : 1;
unsigned int trigger_grp6 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp0 : 1;
unsigned int timer_grp1 : 1;
} reg_iop_sw_cpu_r_intr1;
#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100
/* Register r_masked_intr1, scope iop_sw_cpu, type r */
typedef struct {
unsigned int mpu_16 : 1;
unsigned int mpu_17 : 1;
unsigned int mpu_18 : 1;
unsigned int mpu_19 : 1;
unsigned int mpu_20 : 1;
unsigned int mpu_21 : 1;
unsigned int mpu_22 : 1;
unsigned int mpu_23 : 1;
unsigned int mpu_24 : 1;
unsigned int mpu_25 : 1;
unsigned int mpu_26 : 1;
unsigned int mpu_27 : 1;
unsigned int mpu_28 : 1;
unsigned int mpu_29 : 1;
unsigned int mpu_30 : 1;
unsigned int mpu_31 : 1;
unsigned int dmc_in : 1;
unsigned int dmc_out : 1;
unsigned int fifo_in : 1;
unsigned int fifo_out : 1;
unsigned int fifo_in_extra : 1;
unsigned int fifo_out_extra : 1;
unsigned int trigger_grp0 : 1;
unsigned int trigger_grp1 : 1;
unsigned int trigger_grp2 : 1;
unsigned int trigger_grp3 : 1;
unsigned int trigger_grp4 : 1;
unsigned int trigger_grp5 : 1;
unsigned int trigger_grp6 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp0 : 1;
unsigned int timer_grp1 : 1;
} reg_iop_sw_cpu_r_masked_intr1;
#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104
/* Constants */
enum {
regk_iop_sw_cpu_copy = 0x00000000,
regk_iop_sw_cpu_no = 0x00000000,
regk_iop_sw_cpu_rd = 0x00000002,
regk_iop_sw_cpu_reg_copy = 0x00000001,
regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
regk_iop_sw_cpu_wr = 0x00000003,
regk_iop_sw_cpu_yes = 0x00000001
};
#endif /* __iop_sw_cpu_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h Normal file
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#ifndef __iop_sw_mpu_defs_h
#define __iop_sw_mpu_defs_h
/*
* This file is autogenerated from
* file: iop_sw_mpu.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_sw_mpu */
/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int cfg : 2;
unsigned int dummy1 : 30;
} reg_iop_sw_mpu_rw_sw_cfg_owner;
#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
/* Register r_spu_trace, scope iop_sw_mpu, type r */
typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int keep_owner : 1;
unsigned int cmd : 2;
unsigned int size : 3;
unsigned int wr_spu_mem : 1;
unsigned int dummy1 : 25;
} reg_iop_sw_mpu_rw_mc_ctrl;
#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
/* Register rw_mc_data, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_mpu_rw_mc_data;
#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
/* Register rs_mc_data, scope iop_sw_mpu, type rs */
typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
/* Register r_mc_data, scope iop_sw_mpu, type r */
typedef unsigned int reg_iop_sw_mpu_r_mc_data;
#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
/* Register r_mc_stat, scope iop_sw_mpu, type r */
typedef struct {
unsigned int busy_cpu : 1;
unsigned int busy_mpu : 1;
unsigned int busy_spu : 1;
unsigned int owned_by_cpu : 1;
unsigned int owned_by_mpu : 1;
unsigned int owned_by_spu : 1;
unsigned int dummy1 : 26;
} reg_iop_sw_mpu_r_mc_stat;
#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int byte2 : 8;
unsigned int byte3 : 8;
} reg_iop_sw_mpu_rw_bus_clr_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int byte2 : 8;
unsigned int byte3 : 8;
} reg_iop_sw_mpu_rw_bus_set_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int byte0 : 1;
unsigned int byte1 : 1;
unsigned int byte2 : 1;
unsigned int byte3 : 1;
unsigned int dummy1 : 28;
} reg_iop_sw_mpu_rw_bus_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int byte0 : 1;
unsigned int byte1 : 1;
unsigned int byte2 : 1;
unsigned int byte3 : 1;
unsigned int dummy1 : 28;
} reg_iop_sw_mpu_rw_bus_oe_set_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
/* Register r_bus_in, scope iop_sw_mpu, type r */
typedef unsigned int reg_iop_sw_mpu_r_bus_in;
#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_mpu_rw_gio_clr_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_mpu_rw_gio_set_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_mpu_rw_gio_oe_set_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
/* Register r_gio_in, scope iop_sw_mpu, type r */
typedef unsigned int reg_iop_sw_mpu_r_gio_in;
#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int intr8 : 1;
unsigned int intr9 : 1;
unsigned int intr10 : 1;
unsigned int intr11 : 1;
unsigned int intr12 : 1;
unsigned int intr13 : 1;
unsigned int intr14 : 1;
unsigned int intr15 : 1;
unsigned int intr16 : 1;
unsigned int intr17 : 1;
unsigned int intr18 : 1;
unsigned int intr19 : 1;
unsigned int intr20 : 1;
unsigned int intr21 : 1;
unsigned int intr22 : 1;
unsigned int intr23 : 1;
unsigned int intr24 : 1;
unsigned int intr25 : 1;
unsigned int intr26 : 1;
unsigned int intr27 : 1;
unsigned int intr28 : 1;
unsigned int intr29 : 1;
unsigned int intr30 : 1;
unsigned int intr31 : 1;
} reg_iop_sw_mpu_rw_cpu_intr;
#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
/* Register r_cpu_intr, scope iop_sw_mpu, type r */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int intr8 : 1;
unsigned int intr9 : 1;
unsigned int intr10 : 1;
unsigned int intr11 : 1;
unsigned int intr12 : 1;
unsigned int intr13 : 1;
unsigned int intr14 : 1;
unsigned int intr15 : 1;
unsigned int intr16 : 1;
unsigned int intr17 : 1;
unsigned int intr18 : 1;
unsigned int intr19 : 1;
unsigned int intr20 : 1;
unsigned int intr21 : 1;
unsigned int intr22 : 1;
unsigned int intr23 : 1;
unsigned int intr24 : 1;
unsigned int intr25 : 1;
unsigned int intr26 : 1;
unsigned int intr27 : 1;
unsigned int intr28 : 1;
unsigned int intr29 : 1;
unsigned int intr30 : 1;
unsigned int intr31 : 1;
} reg_iop_sw_mpu_r_cpu_intr;
#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr0 : 1;
unsigned int trigger_grp0 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr1 : 1;
unsigned int trigger_grp1 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int spu_intr2 : 1;
unsigned int trigger_grp2 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr3 : 1;
unsigned int trigger_grp3 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_rw_intr_grp0_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr0 : 1;
unsigned int dummy1 : 3;
unsigned int spu_intr1 : 1;
unsigned int dummy2 : 3;
unsigned int spu_intr2 : 1;
unsigned int dummy3 : 3;
unsigned int spu_intr3 : 1;
unsigned int dummy4 : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp0;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
/* Register r_intr_grp0, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr0 : 1;
unsigned int trigger_grp0 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr1 : 1;
unsigned int trigger_grp1 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int spu_intr2 : 1;
unsigned int trigger_grp2 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr3 : 1;
unsigned int trigger_grp3 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_intr_grp0;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr0 : 1;
unsigned int trigger_grp0 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr1 : 1;
unsigned int trigger_grp1 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int spu_intr2 : 1;
unsigned int trigger_grp2 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr3 : 1;
unsigned int trigger_grp3 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_masked_intr_grp0;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr4 : 1;
unsigned int trigger_grp4 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr5 : 1;
unsigned int trigger_grp5 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int spu_intr6 : 1;
unsigned int trigger_grp6 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr7 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_rw_intr_grp1_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr4 : 1;
unsigned int dummy1 : 3;
unsigned int spu_intr5 : 1;
unsigned int dummy2 : 3;
unsigned int spu_intr6 : 1;
unsigned int dummy3 : 3;
unsigned int spu_intr7 : 1;
unsigned int dummy4 : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp1;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
/* Register r_intr_grp1, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr4 : 1;
unsigned int trigger_grp4 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr5 : 1;
unsigned int trigger_grp5 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int spu_intr6 : 1;
unsigned int trigger_grp6 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr7 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_intr_grp1;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr4 : 1;
unsigned int trigger_grp4 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr5 : 1;
unsigned int trigger_grp5 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int spu_intr6 : 1;
unsigned int trigger_grp6 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr7 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_masked_intr_grp1;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr8 : 1;
unsigned int trigger_grp0 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr9 : 1;
unsigned int trigger_grp1 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int spu_intr10 : 1;
unsigned int trigger_grp2 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr11 : 1;
unsigned int trigger_grp3 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_rw_intr_grp2_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr8 : 1;
unsigned int dummy1 : 3;
unsigned int spu_intr9 : 1;
unsigned int dummy2 : 3;
unsigned int spu_intr10 : 1;
unsigned int dummy3 : 3;
unsigned int spu_intr11 : 1;
unsigned int dummy4 : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp2;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
/* Register r_intr_grp2, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr8 : 1;
unsigned int trigger_grp0 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr9 : 1;
unsigned int trigger_grp1 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int spu_intr10 : 1;
unsigned int trigger_grp2 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr11 : 1;
unsigned int trigger_grp3 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_intr_grp2;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr8 : 1;
unsigned int trigger_grp0 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr9 : 1;
unsigned int trigger_grp1 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int spu_intr10 : 1;
unsigned int trigger_grp2 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr11 : 1;
unsigned int trigger_grp3 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_masked_intr_grp2;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr12 : 1;
unsigned int trigger_grp4 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr13 : 1;
unsigned int trigger_grp5 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int spu_intr14 : 1;
unsigned int trigger_grp6 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr15 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_rw_intr_grp3_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
typedef struct {
unsigned int spu_intr12 : 1;
unsigned int dummy1 : 3;
unsigned int spu_intr13 : 1;
unsigned int dummy2 : 3;
unsigned int spu_intr14 : 1;
unsigned int dummy3 : 3;
unsigned int spu_intr15 : 1;
unsigned int dummy4 : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp3;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
/* Register r_intr_grp3, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr12 : 1;
unsigned int trigger_grp4 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr13 : 1;
unsigned int trigger_grp5 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int spu_intr14 : 1;
unsigned int trigger_grp6 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr15 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_intr_grp3;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
typedef struct {
unsigned int spu_intr12 : 1;
unsigned int trigger_grp4 : 1;
unsigned int fifo_out_extra : 1;
unsigned int dmc_out : 1;
unsigned int spu_intr13 : 1;
unsigned int trigger_grp5 : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_in : 1;
unsigned int spu_intr14 : 1;
unsigned int trigger_grp6 : 1;
unsigned int timer_grp0 : 1;
unsigned int fifo_out : 1;
unsigned int spu_intr15 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_mpu_r_masked_intr_grp3;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
/* Constants */
enum {
regk_iop_sw_mpu_copy = 0x00000000,
regk_iop_sw_mpu_cpu = 0x00000000,
regk_iop_sw_mpu_mpu = 0x00000001,
regk_iop_sw_mpu_no = 0x00000000,
regk_iop_sw_mpu_nop = 0x00000000,
regk_iop_sw_mpu_rd = 0x00000002,
regk_iop_sw_mpu_reg_copy = 0x00000001,
regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
regk_iop_sw_mpu_set = 0x00000001,
regk_iop_sw_mpu_spu = 0x00000002,
regk_iop_sw_mpu_wr = 0x00000003,
regk_iop_sw_mpu_yes = 0x00000001
};
#endif /* __iop_sw_mpu_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h Normal file
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#ifndef __iop_sw_spu_defs_h
#define __iop_sw_spu_defs_h
/*
* This file is autogenerated from
* file: iop_sw_spu.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_sw_spu */
/* Register r_mpu_trace, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0
/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
typedef struct {
unsigned int keep_owner : 1;
unsigned int cmd : 2;
unsigned int size : 3;
unsigned int wr_spu_mem : 1;
unsigned int dummy1 : 25;
} reg_iop_sw_spu_rw_mc_ctrl;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4
/* Register rw_mc_data, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_spu_rw_mc_data;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8
/* Register rw_mc_addr, scope iop_sw_spu, type rw */
typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12
/* Register rs_mc_data, scope iop_sw_spu, type rs */
typedef unsigned int reg_iop_sw_spu_rs_mc_data;
#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16
/* Register r_mc_data, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_mc_data;
#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20
/* Register r_mc_stat, scope iop_sw_spu, type r */
typedef struct {
unsigned int busy_cpu : 1;
unsigned int busy_mpu : 1;
unsigned int busy_spu : 1;
unsigned int owned_by_cpu : 1;
unsigned int owned_by_mpu : 1;
unsigned int owned_by_spu : 1;
unsigned int dummy1 : 26;
} reg_iop_sw_spu_r_mc_stat;
#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24
/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int byte2 : 8;
unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28
/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int byte2 : 8;
unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32
/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte0 : 1;
unsigned int byte1 : 1;
unsigned int byte2 : 1;
unsigned int byte3 : 1;
unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte0 : 1;
unsigned int byte1 : 1;
unsigned int byte2 : 1;
unsigned int byte3 : 1;
unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus_oe_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
/* Register r_bus_in, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_bus_in;
#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44
/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48
/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52
/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_oe_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
/* Register r_gio_in, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_gio_in;
#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64
/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte2 : 8;
unsigned int byte3 : 8;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte0 : 8;
unsigned int byte1 : 8;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
unsigned int byte2 : 8;
unsigned int byte3 : 8;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int intr8 : 1;
unsigned int intr9 : 1;
unsigned int intr10 : 1;
unsigned int intr11 : 1;
unsigned int intr12 : 1;
unsigned int intr13 : 1;
unsigned int intr14 : 1;
unsigned int intr15 : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_cpu_intr;
#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116
/* Register r_cpu_intr, scope iop_sw_spu, type r */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int intr8 : 1;
unsigned int intr9 : 1;
unsigned int intr10 : 1;
unsigned int intr11 : 1;
unsigned int intr12 : 1;
unsigned int intr13 : 1;
unsigned int intr14 : 1;
unsigned int intr15 : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_r_cpu_intr;
#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120
/* Register r_hw_intr, scope iop_sw_spu, type r */
typedef struct {
unsigned int trigger_grp0 : 1;
unsigned int trigger_grp1 : 1;
unsigned int trigger_grp2 : 1;
unsigned int trigger_grp3 : 1;
unsigned int trigger_grp4 : 1;
unsigned int trigger_grp5 : 1;
unsigned int trigger_grp6 : 1;
unsigned int trigger_grp7 : 1;
unsigned int timer_grp0 : 1;
unsigned int timer_grp1 : 1;
unsigned int fifo_out : 1;
unsigned int fifo_out_extra : 1;
unsigned int fifo_in : 1;
unsigned int fifo_in_extra : 1;
unsigned int dmc_out : 1;
unsigned int dmc_in : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_r_hw_intr;
#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124
/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int intr8 : 1;
unsigned int intr9 : 1;
unsigned int intr10 : 1;
unsigned int intr11 : 1;
unsigned int intr12 : 1;
unsigned int intr13 : 1;
unsigned int intr14 : 1;
unsigned int intr15 : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_mpu_intr;
#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128
/* Register r_mpu_intr, scope iop_sw_spu, type r */
typedef struct {
unsigned int intr0 : 1;
unsigned int intr1 : 1;
unsigned int intr2 : 1;
unsigned int intr3 : 1;
unsigned int intr4 : 1;
unsigned int intr5 : 1;
unsigned int intr6 : 1;
unsigned int intr7 : 1;
unsigned int intr8 : 1;
unsigned int intr9 : 1;
unsigned int intr10 : 1;
unsigned int intr11 : 1;
unsigned int intr12 : 1;
unsigned int intr13 : 1;
unsigned int intr14 : 1;
unsigned int intr15 : 1;
unsigned int dummy1 : 16;
} reg_iop_sw_spu_r_mpu_intr;
#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132
/* Constants */
enum {
regk_iop_sw_spu_copy = 0x00000000,
regk_iop_sw_spu_no = 0x00000000,
regk_iop_sw_spu_nop = 0x00000000,
regk_iop_sw_spu_rd = 0x00000002,
regk_iop_sw_spu_reg_copy = 0x00000001,
regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000,
regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000,
regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
regk_iop_sw_spu_set = 0x00000001,
regk_iop_sw_spu_wr = 0x00000003,
regk_iop_sw_spu_yes = 0x00000001
};
#endif /* __iop_sw_spu_defs_h */

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#ifndef __iop_version_defs_h
#define __iop_version_defs_h
/*
* This file is autogenerated from
* file: iop_version.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_version */
/* Register r_version, scope iop_version, type r */
typedef struct {
unsigned int nr : 8;
unsigned int dummy1 : 24;
} reg_iop_version_r_version;
#define REG_RD_ADDR_iop_version_r_version 0
/* Constants */
enum {
regk_iop_version_v2_0 = 0x00000002
};
#endif /* __iop_version_defs_h */

142
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#ifndef __l2cache_defs_h
#define __l2cache_defs_h
/*
* This file is autogenerated from
* file: l2cache.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope l2cache */
/* Register rw_cfg, scope l2cache, type rw */
typedef struct {
unsigned int en : 1;
unsigned int dummy1 : 31;
} reg_l2cache_rw_cfg;
#define REG_RD_ADDR_l2cache_rw_cfg 0
#define REG_WR_ADDR_l2cache_rw_cfg 0
/* Register rw_ctrl, scope l2cache, type rw */
typedef struct {
unsigned int dummy1 : 7;
unsigned int cbase : 9;
unsigned int dummy2 : 4;
unsigned int csize : 10;
unsigned int dummy3 : 2;
} reg_l2cache_rw_ctrl;
#define REG_RD_ADDR_l2cache_rw_ctrl 4
#define REG_WR_ADDR_l2cache_rw_ctrl 4
/* Register rw_idxop, scope l2cache, type rw */
typedef struct {
unsigned int idx : 10;
unsigned int dummy1 : 14;
unsigned int way : 3;
unsigned int dummy2 : 2;
unsigned int cmd : 3;
} reg_l2cache_rw_idxop;
#define REG_RD_ADDR_l2cache_rw_idxop 8
#define REG_WR_ADDR_l2cache_rw_idxop 8
/* Register rw_addrop_addr, scope l2cache, type rw */
typedef struct {
unsigned int addr : 32;
} reg_l2cache_rw_addrop_addr;
#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
/* Register rw_addrop_ctrl, scope l2cache, type rw */
typedef struct {
unsigned int size : 16;
unsigned int dummy1 : 13;
unsigned int cmd : 3;
} reg_l2cache_rw_addrop_ctrl;
#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
/* Constants */
enum {
regk_l2cache_flush = 0x00000001,
regk_l2cache_no = 0x00000000,
regk_l2cache_rw_addrop_addr_default = 0x00000000,
regk_l2cache_rw_addrop_ctrl_default = 0x00000000,
regk_l2cache_rw_cfg_default = 0x00000000,
regk_l2cache_rw_ctrl_default = 0x00000000,
regk_l2cache_rw_idxop_default = 0x00000000,
regk_l2cache_yes = 0x00000001
};
#endif /* __l2cache_defs_h */

482
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#ifndef __marb_bar_defs_h
#define __marb_bar_defs_h
/*
* This file is autogenerated from
* file: marb_bar.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope marb_bar */
#define STRIDE_marb_bar_rw_ddr2_slots 4
/* Register rw_ddr2_slots, scope marb_bar, type rw */
typedef struct {
unsigned int owner : 4;
unsigned int dummy1 : 28;
} reg_marb_bar_rw_ddr2_slots;
#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0
#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0
/* Register rw_h264_rd_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_h264_rd_burst;
#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256
#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256
/* Register rw_h264_wr_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_h264_wr_burst;
#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260
#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260
/* Register rw_ccd_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_ccd_burst;
#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264
#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264
/* Register rw_vin_wr_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_vin_wr_burst;
#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268
#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268
/* Register rw_vin_rd_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_vin_rd_burst;
#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272
#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272
/* Register rw_sclr_rd_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_sclr_rd_burst;
#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276
#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276
/* Register rw_vout_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_vout_burst;
#define REG_RD_ADDR_marb_bar_rw_vout_burst 280
#define REG_WR_ADDR_marb_bar_rw_vout_burst 280
/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_sclr_fifo_burst;
#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284
#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284
/* Register rw_l2cache_burst, scope marb_bar, type rw */
typedef struct {
unsigned int ddr2_bsize : 2;
unsigned int dummy1 : 30;
} reg_marb_bar_rw_l2cache_burst;
#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288
#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288
/* Register rw_intr_mask, scope marb_bar, type rw */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_bar_rw_intr_mask;
#define REG_RD_ADDR_marb_bar_rw_intr_mask 292
#define REG_WR_ADDR_marb_bar_rw_intr_mask 292
/* Register rw_ack_intr, scope marb_bar, type rw */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_bar_rw_ack_intr;
#define REG_RD_ADDR_marb_bar_rw_ack_intr 296
#define REG_WR_ADDR_marb_bar_rw_ack_intr 296
/* Register r_intr, scope marb_bar, type r */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_bar_r_intr;
#define REG_RD_ADDR_marb_bar_r_intr 300
/* Register r_masked_intr, scope marb_bar, type r */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_bar_r_masked_intr;
#define REG_RD_ADDR_marb_bar_r_masked_intr 304
/* Register rw_stop_mask, scope marb_bar, type rw */
typedef struct {
unsigned int h264_rd : 1;
unsigned int h264_wr : 1;
unsigned int ccd : 1;
unsigned int vin_wr : 1;
unsigned int vin_rd : 1;
unsigned int sclr_rd : 1;
unsigned int vout : 1;
unsigned int sclr_fifo : 1;
unsigned int l2cache : 1;
unsigned int dummy1 : 23;
} reg_marb_bar_rw_stop_mask;
#define REG_RD_ADDR_marb_bar_rw_stop_mask 308
#define REG_WR_ADDR_marb_bar_rw_stop_mask 308
/* Register r_stopped, scope marb_bar, type r */
typedef struct {
unsigned int h264_rd : 1;
unsigned int h264_wr : 1;
unsigned int ccd : 1;
unsigned int vin_wr : 1;
unsigned int vin_rd : 1;
unsigned int sclr_rd : 1;
unsigned int vout : 1;
unsigned int sclr_fifo : 1;
unsigned int l2cache : 1;
unsigned int dummy1 : 23;
} reg_marb_bar_r_stopped;
#define REG_RD_ADDR_marb_bar_r_stopped 312
/* Register rw_no_snoop, scope marb_bar, type rw */
typedef struct {
unsigned int h264_rd : 1;
unsigned int h264_wr : 1;
unsigned int ccd : 1;
unsigned int vin_wr : 1;
unsigned int vin_rd : 1;
unsigned int sclr_rd : 1;
unsigned int vout : 1;
unsigned int sclr_fifo : 1;
unsigned int l2cache : 1;
unsigned int dummy1 : 23;
} reg_marb_bar_rw_no_snoop;
#define REG_RD_ADDR_marb_bar_rw_no_snoop 576
#define REG_WR_ADDR_marb_bar_rw_no_snoop 576
/* Constants */
enum {
regk_marb_bar_ccd = 0x00000002,
regk_marb_bar_h264_rd = 0x00000000,
regk_marb_bar_h264_wr = 0x00000001,
regk_marb_bar_l2cache = 0x00000008,
regk_marb_bar_no = 0x00000000,
regk_marb_bar_r_stopped_default = 0x00000000,
regk_marb_bar_rw_ccd_burst_default = 0x00000000,
regk_marb_bar_rw_ddr2_slots_default = 0x00000000,
regk_marb_bar_rw_ddr2_slots_size = 0x00000040,
regk_marb_bar_rw_h264_rd_burst_default = 0x00000000,
regk_marb_bar_rw_h264_wr_burst_default = 0x00000000,
regk_marb_bar_rw_intr_mask_default = 0x00000000,
regk_marb_bar_rw_l2cache_burst_default = 0x00000000,
regk_marb_bar_rw_no_snoop_default = 0x00000000,
regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000,
regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000,
regk_marb_bar_rw_stop_mask_default = 0x00000000,
regk_marb_bar_rw_vin_rd_burst_default = 0x00000000,
regk_marb_bar_rw_vin_wr_burst_default = 0x00000000,
regk_marb_bar_rw_vout_burst_default = 0x00000000,
regk_marb_bar_sclr_fifo = 0x00000007,
regk_marb_bar_sclr_rd = 0x00000005,
regk_marb_bar_vin_rd = 0x00000004,
regk_marb_bar_vin_wr = 0x00000003,
regk_marb_bar_vout = 0x00000006,
regk_marb_bar_yes = 0x00000001
};
#endif /* __marb_bar_defs_h */
#ifndef __marb_bar_bp_defs_h
#define __marb_bar_bp_defs_h
/*
* This file is autogenerated from
* file: marb_bar.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope marb_bar_bp */
/* Register rw_first_addr, scope marb_bar_bp, type rw */
typedef unsigned int reg_marb_bar_bp_rw_first_addr;
#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0
#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0
/* Register rw_last_addr, scope marb_bar_bp, type rw */
typedef unsigned int reg_marb_bar_bp_rw_last_addr;
#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4
#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4
/* Register rw_op, scope marb_bar_bp, type rw */
typedef struct {
unsigned int rd : 1;
unsigned int wr : 1;
unsigned int rd_excl : 1;
unsigned int pri_wr : 1;
unsigned int us_rd : 1;
unsigned int us_wr : 1;
unsigned int us_rd_excl : 1;
unsigned int us_pri_wr : 1;
unsigned int dummy1 : 24;
} reg_marb_bar_bp_rw_op;
#define REG_RD_ADDR_marb_bar_bp_rw_op 8
#define REG_WR_ADDR_marb_bar_bp_rw_op 8
/* Register rw_clients, scope marb_bar_bp, type rw */
typedef struct {
unsigned int h264_rd : 1;
unsigned int h264_wr : 1;
unsigned int ccd : 1;
unsigned int vin_wr : 1;
unsigned int vin_rd : 1;
unsigned int sclr_rd : 1;
unsigned int vout : 1;
unsigned int sclr_fifo : 1;
unsigned int l2cache : 1;
unsigned int dummy1 : 23;
} reg_marb_bar_bp_rw_clients;
#define REG_RD_ADDR_marb_bar_bp_rw_clients 12
#define REG_WR_ADDR_marb_bar_bp_rw_clients 12
/* Register rw_options, scope marb_bar_bp, type rw */
typedef struct {
unsigned int wrap : 1;
unsigned int dummy1 : 31;
} reg_marb_bar_bp_rw_options;
#define REG_RD_ADDR_marb_bar_bp_rw_options 16
#define REG_WR_ADDR_marb_bar_bp_rw_options 16
/* Register r_brk_addr, scope marb_bar_bp, type r */
typedef unsigned int reg_marb_bar_bp_r_brk_addr;
#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20
/* Register r_brk_op, scope marb_bar_bp, type r */
typedef struct {
unsigned int rd : 1;
unsigned int wr : 1;
unsigned int rd_excl : 1;
unsigned int pri_wr : 1;
unsigned int us_rd : 1;
unsigned int us_wr : 1;
unsigned int us_rd_excl : 1;
unsigned int us_pri_wr : 1;
unsigned int dummy1 : 24;
} reg_marb_bar_bp_r_brk_op;
#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24
/* Register r_brk_clients, scope marb_bar_bp, type r */
typedef struct {
unsigned int h264_rd : 1;
unsigned int h264_wr : 1;
unsigned int ccd : 1;
unsigned int vin_wr : 1;
unsigned int vin_rd : 1;
unsigned int sclr_rd : 1;
unsigned int vout : 1;
unsigned int sclr_fifo : 1;
unsigned int l2cache : 1;
unsigned int dummy1 : 23;
} reg_marb_bar_bp_r_brk_clients;
#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28
/* Register r_brk_first_client, scope marb_bar_bp, type r */
typedef struct {
unsigned int h264_rd : 1;
unsigned int h264_wr : 1;
unsigned int ccd : 1;
unsigned int vin_wr : 1;
unsigned int vin_rd : 1;
unsigned int sclr_rd : 1;
unsigned int vout : 1;
unsigned int sclr_fifo : 1;
unsigned int l2cache : 1;
unsigned int dummy1 : 23;
} reg_marb_bar_bp_r_brk_first_client;
#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32
/* Register r_brk_size, scope marb_bar_bp, type r */
typedef unsigned int reg_marb_bar_bp_r_brk_size;
#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36
/* Register rw_ack, scope marb_bar_bp, type rw */
typedef unsigned int reg_marb_bar_bp_rw_ack;
#define REG_RD_ADDR_marb_bar_bp_rw_ack 40
#define REG_WR_ADDR_marb_bar_bp_rw_ack 40
/* Constants */
enum {
regk_marb_bar_bp_no = 0x00000000,
regk_marb_bar_bp_rw_op_default = 0x00000000,
regk_marb_bar_bp_rw_options_default = 0x00000000,
regk_marb_bar_bp_yes = 0x00000001
};
#endif /* __marb_bar_bp_defs_h */

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#ifndef __marb_foo_defs_h
#define __marb_foo_defs_h
/*
* This file is autogenerated from
* file: marb_foo.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope marb_foo */
#define STRIDE_marb_foo_rw_intm_slots 4
/* Register rw_intm_slots, scope marb_foo, type rw */
typedef struct {
unsigned int owner : 4;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_intm_slots;
#define REG_RD_ADDR_marb_foo_rw_intm_slots 0
#define REG_WR_ADDR_marb_foo_rw_intm_slots 0
#define STRIDE_marb_foo_rw_l2_slots 4
/* Register rw_l2_slots, scope marb_foo, type rw */
typedef struct {
unsigned int owner : 4;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_l2_slots;
#define REG_RD_ADDR_marb_foo_rw_l2_slots 256
#define REG_WR_ADDR_marb_foo_rw_l2_slots 256
#define STRIDE_marb_foo_rw_regs_slots 4
/* Register rw_regs_slots, scope marb_foo, type rw */
typedef struct {
unsigned int owner : 4;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_regs_slots;
#define REG_RD_ADDR_marb_foo_rw_regs_slots 512
#define REG_WR_ADDR_marb_foo_rw_regs_slots 512
/* Register rw_sclr_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_sclr_burst;
#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528
#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528
/* Register rw_dma0_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma0_burst;
#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532
#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532
/* Register rw_dma1_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma1_burst;
#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536
#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536
/* Register rw_dma2_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma2_burst;
#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540
#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540
/* Register rw_dma3_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma3_burst;
#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544
#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544
/* Register rw_dma4_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma4_burst;
#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548
#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548
/* Register rw_dma5_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma5_burst;
#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552
#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552
/* Register rw_dma6_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma6_burst;
#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556
#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556
/* Register rw_dma7_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma7_burst;
#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560
#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560
/* Register rw_dma9_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma9_burst;
#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564
#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564
/* Register rw_dma11_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_dma11_burst;
#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568
#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568
/* Register rw_cpui_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_cpui_burst;
#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572
#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572
/* Register rw_cpud_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_cpud_burst;
#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576
#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576
/* Register rw_iop_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_iop_burst;
#define REG_RD_ADDR_marb_foo_rw_iop_burst 580
#define REG_WR_ADDR_marb_foo_rw_iop_burst 580
/* Register rw_ccdstat_burst, scope marb_foo, type rw */
typedef struct {
unsigned int intm_bsize : 2;
unsigned int l2_bsize : 2;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_ccdstat_burst;
#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584
#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584
/* Register rw_intr_mask, scope marb_foo, type rw */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_intr_mask;
#define REG_RD_ADDR_marb_foo_rw_intr_mask 588
#define REG_WR_ADDR_marb_foo_rw_intr_mask 588
/* Register rw_ack_intr, scope marb_foo, type rw */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_foo_rw_ack_intr;
#define REG_RD_ADDR_marb_foo_rw_ack_intr 592
#define REG_WR_ADDR_marb_foo_rw_ack_intr 592
/* Register r_intr, scope marb_foo, type r */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_foo_r_intr;
#define REG_RD_ADDR_marb_foo_r_intr 596
/* Register r_masked_intr, scope marb_foo, type r */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_foo_r_masked_intr;
#define REG_RD_ADDR_marb_foo_r_masked_intr 600
/* Register rw_stop_mask, scope marb_foo, type rw */
typedef struct {
unsigned int sclr : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int ccdstat : 1;
unsigned int dummy1 : 17;
} reg_marb_foo_rw_stop_mask;
#define REG_RD_ADDR_marb_foo_rw_stop_mask 604
#define REG_WR_ADDR_marb_foo_rw_stop_mask 604
/* Register r_stopped, scope marb_foo, type r */
typedef struct {
unsigned int sclr : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int ccdstat : 1;
unsigned int dummy1 : 17;
} reg_marb_foo_r_stopped;
#define REG_RD_ADDR_marb_foo_r_stopped 608
/* Register rw_no_snoop, scope marb_foo, type rw */
typedef struct {
unsigned int sclr : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int ccdstat : 1;
unsigned int dummy1 : 17;
} reg_marb_foo_rw_no_snoop;
#define REG_RD_ADDR_marb_foo_rw_no_snoop 896
#define REG_WR_ADDR_marb_foo_rw_no_snoop 896
/* Register rw_no_snoop_rq, scope marb_foo, type rw */
typedef struct {
unsigned int dummy1 : 11;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int dummy2 : 19;
} reg_marb_foo_rw_no_snoop_rq;
#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900
#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900
/* Constants */
enum {
regk_marb_foo_ccdstat = 0x0000000e,
regk_marb_foo_cpud = 0x0000000c,
regk_marb_foo_cpui = 0x0000000b,
regk_marb_foo_dma0 = 0x00000001,
regk_marb_foo_dma1 = 0x00000002,
regk_marb_foo_dma11 = 0x0000000a,
regk_marb_foo_dma2 = 0x00000003,
regk_marb_foo_dma3 = 0x00000004,
regk_marb_foo_dma4 = 0x00000005,
regk_marb_foo_dma5 = 0x00000006,
regk_marb_foo_dma6 = 0x00000007,
regk_marb_foo_dma7 = 0x00000008,
regk_marb_foo_dma9 = 0x00000009,
regk_marb_foo_iop = 0x0000000d,
regk_marb_foo_no = 0x00000000,
regk_marb_foo_r_stopped_default = 0x00000000,
regk_marb_foo_rw_ccdstat_burst_default = 0x00000000,
regk_marb_foo_rw_cpud_burst_default = 0x00000000,
regk_marb_foo_rw_cpui_burst_default = 0x00000000,
regk_marb_foo_rw_dma0_burst_default = 0x00000000,
regk_marb_foo_rw_dma11_burst_default = 0x00000000,
regk_marb_foo_rw_dma1_burst_default = 0x00000000,
regk_marb_foo_rw_dma2_burst_default = 0x00000000,
regk_marb_foo_rw_dma3_burst_default = 0x00000000,
regk_marb_foo_rw_dma4_burst_default = 0x00000000,
regk_marb_foo_rw_dma5_burst_default = 0x00000000,
regk_marb_foo_rw_dma6_burst_default = 0x00000000,
regk_marb_foo_rw_dma7_burst_default = 0x00000000,
regk_marb_foo_rw_dma9_burst_default = 0x00000000,
regk_marb_foo_rw_intm_slots_default = 0x00000000,
regk_marb_foo_rw_intm_slots_size = 0x00000040,
regk_marb_foo_rw_intr_mask_default = 0x00000000,
regk_marb_foo_rw_iop_burst_default = 0x00000000,
regk_marb_foo_rw_l2_slots_default = 0x00000000,
regk_marb_foo_rw_l2_slots_size = 0x00000040,
regk_marb_foo_rw_no_snoop_default = 0x00000000,
regk_marb_foo_rw_no_snoop_rq_default = 0x00000000,
regk_marb_foo_rw_regs_slots_default = 0x00000000,
regk_marb_foo_rw_regs_slots_size = 0x00000004,
regk_marb_foo_rw_sclr_burst_default = 0x00000000,
regk_marb_foo_rw_stop_mask_default = 0x00000000,
regk_marb_foo_sclr = 0x00000000,
regk_marb_foo_yes = 0x00000001
};
#endif /* __marb_foo_defs_h */
#ifndef __marb_foo_bp_defs_h
#define __marb_foo_bp_defs_h
/*
* This file is autogenerated from
* file: marb_foo.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope marb_foo_bp */
/* Register rw_first_addr, scope marb_foo_bp, type rw */
typedef unsigned int reg_marb_foo_bp_rw_first_addr;
#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0
#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0
/* Register rw_last_addr, scope marb_foo_bp, type rw */
typedef unsigned int reg_marb_foo_bp_rw_last_addr;
#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4
#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4
/* Register rw_op, scope marb_foo_bp, type rw */
typedef struct {
unsigned int rd : 1;
unsigned int wr : 1;
unsigned int rd_excl : 1;
unsigned int pri_wr : 1;
unsigned int us_rd : 1;
unsigned int us_wr : 1;
unsigned int us_rd_excl : 1;
unsigned int us_pri_wr : 1;
unsigned int dummy1 : 24;
} reg_marb_foo_bp_rw_op;
#define REG_RD_ADDR_marb_foo_bp_rw_op 8
#define REG_WR_ADDR_marb_foo_bp_rw_op 8
/* Register rw_clients, scope marb_foo_bp, type rw */
typedef struct {
unsigned int sclr : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int ccdstat : 1;
unsigned int dummy1 : 17;
} reg_marb_foo_bp_rw_clients;
#define REG_RD_ADDR_marb_foo_bp_rw_clients 12
#define REG_WR_ADDR_marb_foo_bp_rw_clients 12
/* Register rw_options, scope marb_foo_bp, type rw */
typedef struct {
unsigned int wrap : 1;
unsigned int dummy1 : 31;
} reg_marb_foo_bp_rw_options;
#define REG_RD_ADDR_marb_foo_bp_rw_options 16
#define REG_WR_ADDR_marb_foo_bp_rw_options 16
/* Register r_brk_addr, scope marb_foo_bp, type r */
typedef unsigned int reg_marb_foo_bp_r_brk_addr;
#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20
/* Register r_brk_op, scope marb_foo_bp, type r */
typedef struct {
unsigned int rd : 1;
unsigned int wr : 1;
unsigned int rd_excl : 1;
unsigned int pri_wr : 1;
unsigned int us_rd : 1;
unsigned int us_wr : 1;
unsigned int us_rd_excl : 1;
unsigned int us_pri_wr : 1;
unsigned int dummy1 : 24;
} reg_marb_foo_bp_r_brk_op;
#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24
/* Register r_brk_clients, scope marb_foo_bp, type r */
typedef struct {
unsigned int sclr : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int ccdstat : 1;
unsigned int dummy1 : 17;
} reg_marb_foo_bp_r_brk_clients;
#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28
/* Register r_brk_first_client, scope marb_foo_bp, type r */
typedef struct {
unsigned int sclr : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma9 : 1;
unsigned int dma11 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int ccdstat : 1;
unsigned int dummy1 : 17;
} reg_marb_foo_bp_r_brk_first_client;
#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32
/* Register r_brk_size, scope marb_foo_bp, type r */
typedef unsigned int reg_marb_foo_bp_r_brk_size;
#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36
/* Register rw_ack, scope marb_foo_bp, type rw */
typedef unsigned int reg_marb_foo_bp_rw_ack;
#define REG_RD_ADDR_marb_foo_bp_rw_ack 40
#define REG_WR_ADDR_marb_foo_bp_rw_ack 40
/* Constants */
enum {
regk_marb_foo_bp_no = 0x00000000,
regk_marb_foo_bp_rw_op_default = 0x00000000,
regk_marb_foo_bp_rw_options_default = 0x00000000,
regk_marb_foo_bp_yes = 0x00000001
};
#endif /* __marb_foo_bp_defs_h */

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#ifndef __pinmux_defs_h
#define __pinmux_defs_h
/*
* This file is autogenerated from
* file: pinmux.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope pinmux */
/* Register rw_hwprot, scope pinmux, type rw */
typedef struct {
unsigned int eth : 1;
unsigned int eth_mdio : 1;
unsigned int geth : 1;
unsigned int tg : 1;
unsigned int tg_clk : 1;
unsigned int vout : 1;
unsigned int vout_sync : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int ser4 : 1;
unsigned int sser : 1;
unsigned int pwm0 : 1;
unsigned int pwm1 : 1;
unsigned int pwm2 : 1;
unsigned int timer0 : 1;
unsigned int timer1 : 1;
unsigned int pio : 1;
unsigned int i2c0 : 1;
unsigned int i2c1 : 1;
unsigned int i2c1_sda1 : 1;
unsigned int i2c1_sda2 : 1;
unsigned int i2c1_sda3 : 1;
unsigned int i2c1_sen : 1;
unsigned int dummy1 : 8;
} reg_pinmux_rw_hwprot;
#define REG_RD_ADDR_pinmux_rw_hwprot 0
#define REG_WR_ADDR_pinmux_rw_hwprot 0
/* Register rw_gio_pa, scope pinmux, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int pa8 : 1;
unsigned int pa9 : 1;
unsigned int pa10 : 1;
unsigned int pa11 : 1;
unsigned int pa12 : 1;
unsigned int pa13 : 1;
unsigned int pa14 : 1;
unsigned int pa15 : 1;
unsigned int pa16 : 1;
unsigned int pa17 : 1;
unsigned int pa18 : 1;
unsigned int pa19 : 1;
unsigned int pa20 : 1;
unsigned int pa21 : 1;
unsigned int pa22 : 1;
unsigned int pa23 : 1;
unsigned int pa24 : 1;
unsigned int pa25 : 1;
unsigned int pa26 : 1;
unsigned int pa27 : 1;
unsigned int pa28 : 1;
unsigned int pa29 : 1;
unsigned int pa30 : 1;
unsigned int pa31 : 1;
} reg_pinmux_rw_gio_pa;
#define REG_RD_ADDR_pinmux_rw_gio_pa 4
#define REG_WR_ADDR_pinmux_rw_gio_pa 4
/* Register rw_gio_pb, scope pinmux, type rw */
typedef struct {
unsigned int pb0 : 1;
unsigned int pb1 : 1;
unsigned int pb2 : 1;
unsigned int pb3 : 1;
unsigned int pb4 : 1;
unsigned int pb5 : 1;
unsigned int pb6 : 1;
unsigned int pb7 : 1;
unsigned int pb8 : 1;
unsigned int pb9 : 1;
unsigned int pb10 : 1;
unsigned int pb11 : 1;
unsigned int pb12 : 1;
unsigned int pb13 : 1;
unsigned int pb14 : 1;
unsigned int pb15 : 1;
unsigned int pb16 : 1;
unsigned int pb17 : 1;
unsigned int pb18 : 1;
unsigned int pb19 : 1;
unsigned int pb20 : 1;
unsigned int pb21 : 1;
unsigned int pb22 : 1;
unsigned int pb23 : 1;
unsigned int pb24 : 1;
unsigned int pb25 : 1;
unsigned int pb26 : 1;
unsigned int pb27 : 1;
unsigned int pb28 : 1;
unsigned int pb29 : 1;
unsigned int pb30 : 1;
unsigned int pb31 : 1;
} reg_pinmux_rw_gio_pb;
#define REG_RD_ADDR_pinmux_rw_gio_pb 8
#define REG_WR_ADDR_pinmux_rw_gio_pb 8
/* Register rw_gio_pc, scope pinmux, type rw */
typedef struct {
unsigned int pc0 : 1;
unsigned int pc1 : 1;
unsigned int pc2 : 1;
unsigned int pc3 : 1;
unsigned int pc4 : 1;
unsigned int pc5 : 1;
unsigned int pc6 : 1;
unsigned int pc7 : 1;
unsigned int pc8 : 1;
unsigned int pc9 : 1;
unsigned int pc10 : 1;
unsigned int pc11 : 1;
unsigned int pc12 : 1;
unsigned int pc13 : 1;
unsigned int pc14 : 1;
unsigned int pc15 : 1;
unsigned int dummy1 : 16;
} reg_pinmux_rw_gio_pc;
#define REG_RD_ADDR_pinmux_rw_gio_pc 12
#define REG_WR_ADDR_pinmux_rw_gio_pc 12
/* Register rw_iop_pa, scope pinmux, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int pa8 : 1;
unsigned int pa9 : 1;
unsigned int pa10 : 1;
unsigned int pa11 : 1;
unsigned int pa12 : 1;
unsigned int pa13 : 1;
unsigned int pa14 : 1;
unsigned int pa15 : 1;
unsigned int pa16 : 1;
unsigned int pa17 : 1;
unsigned int pa18 : 1;
unsigned int pa19 : 1;
unsigned int pa20 : 1;
unsigned int pa21 : 1;
unsigned int pa22 : 1;
unsigned int pa23 : 1;
unsigned int pa24 : 1;
unsigned int pa25 : 1;
unsigned int pa26 : 1;
unsigned int pa27 : 1;
unsigned int pa28 : 1;
unsigned int pa29 : 1;
unsigned int pa30 : 1;
unsigned int pa31 : 1;
} reg_pinmux_rw_iop_pa;
#define REG_RD_ADDR_pinmux_rw_iop_pa 16
#define REG_WR_ADDR_pinmux_rw_iop_pa 16
/* Register rw_iop_pb, scope pinmux, type rw */
typedef struct {
unsigned int pb0 : 1;
unsigned int pb1 : 1;
unsigned int pb2 : 1;
unsigned int pb3 : 1;
unsigned int pb4 : 1;
unsigned int pb5 : 1;
unsigned int pb6 : 1;
unsigned int pb7 : 1;
unsigned int dummy1 : 24;
} reg_pinmux_rw_iop_pb;
#define REG_RD_ADDR_pinmux_rw_iop_pb 20
#define REG_WR_ADDR_pinmux_rw_iop_pb 20
/* Register rw_iop_pio, scope pinmux, type rw */
typedef struct {
unsigned int d0 : 1;
unsigned int d1 : 1;
unsigned int d2 : 1;
unsigned int d3 : 1;
unsigned int d4 : 1;
unsigned int d5 : 1;
unsigned int d6 : 1;
unsigned int d7 : 1;
unsigned int rd_n : 1;
unsigned int wr_n : 1;
unsigned int a0 : 1;
unsigned int a1 : 1;
unsigned int ce0_n : 1;
unsigned int ce1_n : 1;
unsigned int ce2_n : 1;
unsigned int rdy : 1;
unsigned int dummy1 : 16;
} reg_pinmux_rw_iop_pio;
#define REG_RD_ADDR_pinmux_rw_iop_pio 24
#define REG_WR_ADDR_pinmux_rw_iop_pio 24
/* Register rw_iop_usb, scope pinmux, type rw */
typedef struct {
unsigned int usb0 : 1;
unsigned int dummy1 : 31;
} reg_pinmux_rw_iop_usb;
#define REG_RD_ADDR_pinmux_rw_iop_usb 28
#define REG_WR_ADDR_pinmux_rw_iop_usb 28
/* Constants */
enum {
regk_pinmux_no = 0x00000000,
regk_pinmux_rw_gio_pa_default = 0x00000000,
regk_pinmux_rw_gio_pb_default = 0x00000000,
regk_pinmux_rw_gio_pc_default = 0x00000000,
regk_pinmux_rw_hwprot_default = 0x00000000,
regk_pinmux_rw_iop_pa_default = 0x00000000,
regk_pinmux_rw_iop_pb_default = 0x00000000,
regk_pinmux_rw_iop_pio_default = 0x00000000,
regk_pinmux_rw_iop_usb_default = 0x00000001,
regk_pinmux_yes = 0x00000001
};
#endif /* __pinmux_defs_h */

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#ifndef __pio_defs_h
#define __pio_defs_h
/*
* This file is autogenerated from
* file: pio.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope pio */
/* Register rw_data, scope pio, type rw */
typedef unsigned int reg_pio_rw_data;
#define REG_RD_ADDR_pio_rw_data 64
#define REG_WR_ADDR_pio_rw_data 64
/* Register rw_io_access0, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access0;
#define REG_RD_ADDR_pio_rw_io_access0 0
#define REG_WR_ADDR_pio_rw_io_access0 0
/* Register rw_io_access1, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access1;
#define REG_RD_ADDR_pio_rw_io_access1 4
#define REG_WR_ADDR_pio_rw_io_access1 4
/* Register rw_io_access2, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access2;
#define REG_RD_ADDR_pio_rw_io_access2 8
#define REG_WR_ADDR_pio_rw_io_access2 8
/* Register rw_io_access3, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access3;
#define REG_RD_ADDR_pio_rw_io_access3 12
#define REG_WR_ADDR_pio_rw_io_access3 12
/* Register rw_io_access4, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access4;
#define REG_RD_ADDR_pio_rw_io_access4 16
#define REG_WR_ADDR_pio_rw_io_access4 16
/* Register rw_io_access5, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access5;
#define REG_RD_ADDR_pio_rw_io_access5 20
#define REG_WR_ADDR_pio_rw_io_access5 20
/* Register rw_io_access6, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access6;
#define REG_RD_ADDR_pio_rw_io_access6 24
#define REG_WR_ADDR_pio_rw_io_access6 24
/* Register rw_io_access7, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access7;
#define REG_RD_ADDR_pio_rw_io_access7 28
#define REG_WR_ADDR_pio_rw_io_access7 28
/* Register rw_io_access8, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access8;
#define REG_RD_ADDR_pio_rw_io_access8 32
#define REG_WR_ADDR_pio_rw_io_access8 32
/* Register rw_io_access9, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access9;
#define REG_RD_ADDR_pio_rw_io_access9 36
#define REG_WR_ADDR_pio_rw_io_access9 36
/* Register rw_io_access10, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access10;
#define REG_RD_ADDR_pio_rw_io_access10 40
#define REG_WR_ADDR_pio_rw_io_access10 40
/* Register rw_io_access11, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access11;
#define REG_RD_ADDR_pio_rw_io_access11 44
#define REG_WR_ADDR_pio_rw_io_access11 44
/* Register rw_io_access12, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access12;
#define REG_RD_ADDR_pio_rw_io_access12 48
#define REG_WR_ADDR_pio_rw_io_access12 48
/* Register rw_io_access13, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access13;
#define REG_RD_ADDR_pio_rw_io_access13 52
#define REG_WR_ADDR_pio_rw_io_access13 52
/* Register rw_io_access14, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access14;
#define REG_RD_ADDR_pio_rw_io_access14 56
#define REG_WR_ADDR_pio_rw_io_access14 56
/* Register rw_io_access15, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_pio_rw_io_access15;
#define REG_RD_ADDR_pio_rw_io_access15 60
#define REG_WR_ADDR_pio_rw_io_access15 60
/* Register rw_ce0_cfg, scope pio, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int mode : 2;
unsigned int dummy1 : 16;
} reg_pio_rw_ce0_cfg;
#define REG_RD_ADDR_pio_rw_ce0_cfg 68
#define REG_WR_ADDR_pio_rw_ce0_cfg 68
/* Register rw_ce1_cfg, scope pio, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int mode : 2;
unsigned int dummy1 : 16;
} reg_pio_rw_ce1_cfg;
#define REG_RD_ADDR_pio_rw_ce1_cfg 72
#define REG_WR_ADDR_pio_rw_ce1_cfg 72
/* Register rw_ce2_cfg, scope pio, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int mode : 2;
unsigned int dummy1 : 16;
} reg_pio_rw_ce2_cfg;
#define REG_RD_ADDR_pio_rw_ce2_cfg 76
#define REG_WR_ADDR_pio_rw_ce2_cfg 76
/* Register rw_dout, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int rd_n : 1;
unsigned int wr_n : 1;
unsigned int a0 : 1;
unsigned int a1 : 1;
unsigned int ce0_n : 1;
unsigned int ce1_n : 1;
unsigned int ce2_n : 1;
unsigned int rdy : 1;
unsigned int dummy1 : 16;
} reg_pio_rw_dout;
#define REG_RD_ADDR_pio_rw_dout 80
#define REG_WR_ADDR_pio_rw_dout 80
/* Register rw_oe, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int rd_n : 1;
unsigned int wr_n : 1;
unsigned int a0 : 1;
unsigned int a1 : 1;
unsigned int ce0_n : 1;
unsigned int ce1_n : 1;
unsigned int ce2_n : 1;
unsigned int rdy : 1;
unsigned int dummy1 : 16;
} reg_pio_rw_oe;
#define REG_RD_ADDR_pio_rw_oe 84
#define REG_WR_ADDR_pio_rw_oe 84
/* Register rw_man_ctrl, scope pio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int rd_n : 1;
unsigned int wr_n : 1;
unsigned int a0 : 1;
unsigned int a1 : 1;
unsigned int ce0_n : 1;
unsigned int ce1_n : 1;
unsigned int ce2_n : 1;
unsigned int rdy : 1;
unsigned int dummy1 : 16;
} reg_pio_rw_man_ctrl;
#define REG_RD_ADDR_pio_rw_man_ctrl 88
#define REG_WR_ADDR_pio_rw_man_ctrl 88
/* Register r_din, scope pio, type r */
typedef struct {
unsigned int data : 8;
unsigned int rd_n : 1;
unsigned int wr_n : 1;
unsigned int a0 : 1;
unsigned int a1 : 1;
unsigned int ce0_n : 1;
unsigned int ce1_n : 1;
unsigned int ce2_n : 1;
unsigned int rdy : 1;
unsigned int dummy1 : 16;
} reg_pio_r_din;
#define REG_RD_ADDR_pio_r_din 92
/* Register r_stat, scope pio, type r */
typedef struct {
unsigned int busy : 1;
unsigned int dummy1 : 31;
} reg_pio_r_stat;
#define REG_RD_ADDR_pio_r_stat 96
/* Register rw_intr_mask, scope pio, type rw */
typedef struct {
unsigned int rdy : 1;
unsigned int dummy1 : 31;
} reg_pio_rw_intr_mask;
#define REG_RD_ADDR_pio_rw_intr_mask 100
#define REG_WR_ADDR_pio_rw_intr_mask 100
/* Register rw_ack_intr, scope pio, type rw */
typedef struct {
unsigned int rdy : 1;
unsigned int dummy1 : 31;
} reg_pio_rw_ack_intr;
#define REG_RD_ADDR_pio_rw_ack_intr 104
#define REG_WR_ADDR_pio_rw_ack_intr 104
/* Register r_intr, scope pio, type r */
typedef struct {
unsigned int rdy : 1;
unsigned int dummy1 : 31;
} reg_pio_r_intr;
#define REG_RD_ADDR_pio_r_intr 108
/* Register r_masked_intr, scope pio, type r */
typedef struct {
unsigned int rdy : 1;
unsigned int dummy1 : 31;
} reg_pio_r_masked_intr;
#define REG_RD_ADDR_pio_r_masked_intr 112
/* Constants */
enum {
regk_pio_a2 = 0x00000003,
regk_pio_no = 0x00000000,
regk_pio_normal = 0x00000000,
regk_pio_rd = 0x00000001,
regk_pio_rw_ce0_cfg_default = 0x00000000,
regk_pio_rw_ce1_cfg_default = 0x00000000,
regk_pio_rw_ce2_cfg_default = 0x00000000,
regk_pio_rw_intr_mask_default = 0x00000000,
regk_pio_rw_man_ctrl_default = 0x00000000,
regk_pio_rw_oe_default = 0x00000000,
regk_pio_wr = 0x00000002,
regk_pio_wr_ce2 = 0x00000003,
regk_pio_yes = 0x00000001,
regk_pio_yes_all = 0x000000ff
};
#endif /* __pio_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h Normal file
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#ifndef __reg_map_h
#define __reg_map_h
/*
* This file is autogenerated from
* file: reg.rmap
*
* by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
typedef enum {
regi_ccd = 0xb0000000,
regi_ccd_top = 0xb0000000,
regi_ccd_dp = 0xb0000400,
regi_ccd_stat = 0xb0000800,
regi_ccd_tg = 0xb0001000,
regi_cfg = 0xb0002000,
regi_clkgen = 0xb0004000,
regi_ddr2_ctrl = 0xb0006000,
regi_dma0 = 0xb0008000,
regi_dma1 = 0xb000a000,
regi_dma11 = 0xb000c000,
regi_dma2 = 0xb000e000,
regi_dma3 = 0xb0010000,
regi_dma4 = 0xb0012000,
regi_dma5 = 0xb0014000,
regi_dma6 = 0xb0016000,
regi_dma7 = 0xb0018000,
regi_dma9 = 0xb001a000,
regi_eth = 0xb001c000,
regi_gio = 0xb0020000,
regi_h264 = 0xb0022000,
regi_hist = 0xb0026000,
regi_iop = 0xb0028000,
regi_iop_version = 0xb0028000,
regi_iop_fifo_in_extra = 0xb0028040,
regi_iop_fifo_out_extra = 0xb0028080,
regi_iop_trigger_grp0 = 0xb00280c0,
regi_iop_trigger_grp1 = 0xb0028100,
regi_iop_trigger_grp2 = 0xb0028140,
regi_iop_trigger_grp3 = 0xb0028180,
regi_iop_trigger_grp4 = 0xb00281c0,
regi_iop_trigger_grp5 = 0xb0028200,
regi_iop_trigger_grp6 = 0xb0028240,
regi_iop_trigger_grp7 = 0xb0028280,
regi_iop_crc_par = 0xb0028300,
regi_iop_dmc_in = 0xb0028380,
regi_iop_dmc_out = 0xb0028400,
regi_iop_fifo_in = 0xb0028480,
regi_iop_fifo_out = 0xb0028500,
regi_iop_scrc_in = 0xb0028580,
regi_iop_scrc_out = 0xb0028600,
regi_iop_timer_grp0 = 0xb0028680,
regi_iop_timer_grp1 = 0xb0028700,
regi_iop_sap_in = 0xb0028800,
regi_iop_sap_out = 0xb0028900,
regi_iop_spu = 0xb0028a00,
regi_iop_sw_cfg = 0xb0028b00,
regi_iop_sw_cpu = 0xb0028c00,
regi_iop_sw_mpu = 0xb0028d00,
regi_iop_sw_spu = 0xb0028e00,
regi_iop_mpu = 0xb0029000,
regi_irq = 0xb002a000,
regi_irq2 = 0xb006a000,
regi_jpeg = 0xb002c000,
regi_l2cache = 0xb0030000,
regi_marb_bar = 0xb0032000,
regi_marb_bar_bp0 = 0xb0032140,
regi_marb_bar_bp1 = 0xb0032180,
regi_marb_bar_bp2 = 0xb00321c0,
regi_marb_bar_bp3 = 0xb0032200,
regi_marb_foo = 0xb0034000,
regi_marb_foo_bp0 = 0xb0034280,
regi_marb_foo_bp1 = 0xb00342c0,
regi_marb_foo_bp2 = 0xb0034300,
regi_marb_foo_bp3 = 0xb0034340,
regi_pinmux = 0xb0038000,
regi_pio = 0xb0036000,
regi_sclr = 0xb003a000,
regi_sclr_fifo = 0xb003c000,
regi_ser0 = 0xb003e000,
regi_ser1 = 0xb0040000,
regi_ser2 = 0xb0042000,
regi_ser3 = 0xb0044000,
regi_ser4 = 0xb0046000,
regi_sser = 0xb0048000,
regi_strcop = 0xb004a000,
regi_strdma0 = 0xb004e000,
regi_strdma1 = 0xb0050000,
regi_strdma2 = 0xb0052000,
regi_strdma3 = 0xb0054000,
regi_strdma5 = 0xb0056000,
regi_strmux = 0xb004c000,
regi_timer0 = 0xb0058000,
regi_timer1 = 0xb005a000,
regi_timer2 = 0xb006e000,
regi_trace = 0xb005c000,
regi_vin = 0xb005e000,
regi_vout = 0xb0060000
} reg_scope_instances;
#endif /* __reg_map_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h Normal file
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#ifndef __strmux_defs_h
#define __strmux_defs_h
/*
* This file is autogenerated from
* file: strmux.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope strmux */
/* Register rw_cfg, scope strmux, type rw */
typedef struct {
unsigned int dma0 : 2;
unsigned int dma1 : 2;
unsigned int dma2 : 2;
unsigned int dma3 : 2;
unsigned int dma4 : 2;
unsigned int dma5 : 2;
unsigned int dma6 : 2;
unsigned int dma7 : 2;
unsigned int dummy1 : 2;
unsigned int dma9 : 2;
unsigned int dummy2 : 2;
unsigned int dma11 : 2;
unsigned int dummy3 : 8;
} reg_strmux_rw_cfg;
#define REG_RD_ADDR_strmux_rw_cfg 0
#define REG_WR_ADDR_strmux_rw_cfg 0
/* Constants */
enum {
regk_strmux_eth = 0x00000001,
regk_strmux_h264 = 0x00000001,
regk_strmux_iop = 0x00000001,
regk_strmux_jpeg = 0x00000001,
regk_strmux_off = 0x00000000,
regk_strmux_rw_cfg_default = 0x00000000,
regk_strmux_ser0 = 0x00000002,
regk_strmux_ser1 = 0x00000002,
regk_strmux_ser2 = 0x00000002,
regk_strmux_ser3 = 0x00000002,
regk_strmux_ser4 = 0x00000002,
regk_strmux_sser = 0x00000001,
regk_strmux_strcop = 0x00000001
};
#endif /* __strmux_defs_h */

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include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h Normal file
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#ifndef __timer_defs_h
#define __timer_defs_h
/*
* This file is autogenerated from
* file: timer.r
*
* by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope timer */
/* Register rw_tmr0_div, scope timer, type rw */
typedef unsigned int reg_timer_rw_tmr0_div;
#define REG_RD_ADDR_timer_rw_tmr0_div 0
#define REG_WR_ADDR_timer_rw_tmr0_div 0
/* Register r_tmr0_data, scope timer, type r */
typedef unsigned int reg_timer_r_tmr0_data;
#define REG_RD_ADDR_timer_r_tmr0_data 4
/* Register rw_tmr0_ctrl, scope timer, type rw */
typedef struct {
unsigned int op : 2;
unsigned int freq : 3;
unsigned int dummy1 : 27;
} reg_timer_rw_tmr0_ctrl;
#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
/* Register rw_tmr1_div, scope timer, type rw */
typedef unsigned int reg_timer_rw_tmr1_div;
#define REG_RD_ADDR_timer_rw_tmr1_div 16
#define REG_WR_ADDR_timer_rw_tmr1_div 16
/* Register r_tmr1_data, scope timer, type r */
typedef unsigned int reg_timer_r_tmr1_data;
#define REG_RD_ADDR_timer_r_tmr1_data 20
/* Register rw_tmr1_ctrl, scope timer, type rw */
typedef struct {
unsigned int op : 2;
unsigned int freq : 3;
unsigned int dummy1 : 27;
} reg_timer_rw_tmr1_ctrl;
#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
/* Register rs_cnt_data, scope timer, type rs */
typedef struct {
unsigned int tmr : 24;
unsigned int cnt : 8;
} reg_timer_rs_cnt_data;
#define REG_RD_ADDR_timer_rs_cnt_data 32
/* Register r_cnt_data, scope timer, type r */
typedef struct {
unsigned int tmr : 24;
unsigned int cnt : 8;
} reg_timer_r_cnt_data;
#define REG_RD_ADDR_timer_r_cnt_data 36
/* Register rw_cnt_cfg, scope timer, type rw */
typedef struct {
unsigned int clk : 2;
unsigned int dummy1 : 30;
} reg_timer_rw_cnt_cfg;
#define REG_RD_ADDR_timer_rw_cnt_cfg 40
#define REG_WR_ADDR_timer_rw_cnt_cfg 40
/* Register rw_trig, scope timer, type rw */
typedef unsigned int reg_timer_rw_trig;
#define REG_RD_ADDR_timer_rw_trig 48
#define REG_WR_ADDR_timer_rw_trig 48
/* Register rw_trig_cfg, scope timer, type rw */
typedef struct {
unsigned int tmr : 2;
unsigned int dummy1 : 30;
} reg_timer_rw_trig_cfg;
#define REG_RD_ADDR_timer_rw_trig_cfg 52
#define REG_WR_ADDR_timer_rw_trig_cfg 52
/* Register r_time, scope timer, type r */
typedef unsigned int reg_timer_r_time;
#define REG_RD_ADDR_timer_r_time 56
/* Register rw_out, scope timer, type rw */
typedef struct {
unsigned int tmr : 2;
unsigned int dummy1 : 30;
} reg_timer_rw_out;
#define REG_RD_ADDR_timer_rw_out 60
#define REG_WR_ADDR_timer_rw_out 60
/* Register rw_wd_ctrl, scope timer, type rw */
typedef struct {
unsigned int cnt : 8;
unsigned int cmd : 1;
unsigned int key : 7;
unsigned int dummy1 : 16;
} reg_timer_rw_wd_ctrl;
#define REG_RD_ADDR_timer_rw_wd_ctrl 64
#define REG_WR_ADDR_timer_rw_wd_ctrl 64
/* Register r_wd_stat, scope timer, type r */
typedef struct {
unsigned int cnt : 8;
unsigned int cmd : 1;
unsigned int dummy1 : 23;
} reg_timer_r_wd_stat;
#define REG_RD_ADDR_timer_r_wd_stat 68
/* Register rw_intr_mask, scope timer, type rw */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_rw_intr_mask;
#define REG_RD_ADDR_timer_rw_intr_mask 72
#define REG_WR_ADDR_timer_rw_intr_mask 72
/* Register rw_ack_intr, scope timer, type rw */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_rw_ack_intr;
#define REG_RD_ADDR_timer_rw_ack_intr 76
#define REG_WR_ADDR_timer_rw_ack_intr 76
/* Register r_intr, scope timer, type r */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_r_intr;
#define REG_RD_ADDR_timer_r_intr 80
/* Register r_masked_intr, scope timer, type r */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_r_masked_intr;
#define REG_RD_ADDR_timer_r_masked_intr 84
/* Register rw_test, scope timer, type rw */
typedef struct {
unsigned int dis : 1;
unsigned int en : 1;
unsigned int dummy1 : 30;
} reg_timer_rw_test;
#define REG_RD_ADDR_timer_rw_test 88
#define REG_WR_ADDR_timer_rw_test 88
/* Constants */
enum {
regk_timer_ext = 0x00000001,
regk_timer_f100 = 0x00000007,
regk_timer_f29_493 = 0x00000004,
regk_timer_f32 = 0x00000005,
regk_timer_f32_768 = 0x00000006,
regk_timer_f90 = 0x00000003,
regk_timer_hold = 0x00000001,
regk_timer_ld = 0x00000000,
regk_timer_no = 0x00000000,
regk_timer_off = 0x00000000,
regk_timer_run = 0x00000002,
regk_timer_rw_cnt_cfg_default = 0x00000000,
regk_timer_rw_intr_mask_default = 0x00000000,
regk_timer_rw_out_default = 0x00000000,
regk_timer_rw_test_default = 0x00000000,
regk_timer_rw_tmr0_ctrl_default = 0x00000000,
regk_timer_rw_tmr1_ctrl_default = 0x00000000,
regk_timer_rw_trig_cfg_default = 0x00000000,
regk_timer_start = 0x00000001,
regk_timer_stop = 0x00000000,
regk_timer_time = 0x00000001,
regk_timer_tmr0 = 0x00000002,
regk_timer_tmr1 = 0x00000003,
regk_timer_vclk = 0x00000002,
regk_timer_yes = 0x00000001
};
#endif /* __timer_defs_h */

10
include/asm-cris/arch-v32/mach-a3/memmap.h Normal file
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#ifndef _ASM_ARCH_MEMMAP_H
#define _ASM_ARCH_MEMMAP_H
#define MEM_INTMEM_START (0x38000000)
#define MEM_INTMEM_SIZE (0x00018000)
#define MEM_DRAM_START (0x40000000)
#define MEM_NON_CACHEABLE (0x80000000)
#endif

45
include/asm-cris/arch-v32/mach-a3/pinmux.h Normal file
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#ifndef _ASM_CRIS_ARCH_PINMUX_H
#define _ASM_CRIS_ARCH_PINMUX_H
#define PORT_A 0
#define PORT_B 1
#define PORT_C 2
enum pin_mode {
pinmux_none = 0,
pinmux_fixed,
pinmux_gpio,
pinmux_iop
};
enum fixed_function {
pinmux_eth,
pinmux_geth,
pinmux_tg_ccd,
pinmux_tg_cmos,
pinmux_vout,
pinmux_ser1,
pinmux_ser2,
pinmux_ser3,
pinmux_ser4,
pinmux_sser,
pinmux_pio,
pinmux_pwm0,
pinmux_pwm1,
pinmux_pwm2,
pinmux_i2c0,
pinmux_i2c1,
pinmux_i2c1_3wire,
pinmux_i2c1_sda1,
pinmux_i2c1_sda2,
pinmux_i2c1_sda3,
};
int crisv32_pinmux_init(void);
int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
int crisv32_pinmux_alloc_fixed(enum fixed_function function);
int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
void crisv32_pinmux_dump(void);
#endif

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include/asm-cris/arch-v32/mach-a3/startup.inc Normal file
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#include <hwregs/asm/reg_map_asm.h>
#include <hwregs/asm/gio_defs_asm.h>
#include <hwregs/asm/pio_defs_asm.h>
#include <hwregs/asm/clkgen_defs_asm.h>
#include <hwregs/asm/pinmux_defs_asm.h>
.macro GIO_INIT
move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
move.d $r0, [$r1]
move.d 0xFFFFFFFF, $r0
move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
move.d $r0, [$r1]
move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
move.d $r0, [$r1]
move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
move.d $r0, [$r1]
.endm
.macro START_CLOCKS
move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1
move.d [$r1], $r0
or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \
REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \
REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0
move.d $r0, [$r1]
.endm
.macro SETUP_WAIT_STATES
move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0
move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1
move.d $r1, [$r0]
move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0
move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1
move.d $r1, [$r0]
move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0
move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
move.d $r1, [$r0]
.endm

28
include/asm-cris/arch-v32/mach-fs/arbiter.h Normal file
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#ifndef _ASM_CRIS_ARCH_ARBITER_H
#define _ASM_CRIS_ARCH_ARBITER_H
#define EXT_REGION 0
#define INT_REGION 1
typedef void (watch_callback)(void);
enum {
arbiter_all_dmas = 0x3ff,
arbiter_cpu = 0xc00,
arbiter_all_clients = 0x3fff
};
enum {
arbiter_all_read = 0x55,
arbiter_all_write = 0xaa,
arbiter_all_accesses = 0xff
};
int crisv32_arbiter_allocate_bandwidth(int client, int region,
unsigned long bandwidth);
int crisv32_arbiter_watch(unsigned long start, unsigned long size,
unsigned long clients, unsigned long accesses,
watch_callback * cb);
int crisv32_arbiter_unwatch(int id);
#endif

319
include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h Normal file
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#ifndef __bif_core_defs_asm_h
#define __bif_core_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_core_regs.r
* id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
* last modfied: Mon Apr 11 16:06:33 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
* id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_grp1_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
#define reg_bif_core_rw_grp1_cfg___lw___width 6
#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
#define reg_bif_core_rw_grp1_cfg___ew___width 3
#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
#define reg_bif_core_rw_grp1_cfg___zw___width 3
#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
#define reg_bif_core_rw_grp1_cfg___aw___width 2
#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
#define reg_bif_core_rw_grp1_cfg___dw___width 2
#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp1_cfg___ewb___width 2
#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
#define reg_bif_core_rw_grp1_cfg___bw___width 1
#define reg_bif_core_rw_grp1_cfg___bw___bit 18
#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
#define reg_bif_core_rw_grp1_cfg___mode___width 1
#define reg_bif_core_rw_grp1_cfg___mode___bit 21
#define reg_bif_core_rw_grp1_cfg_offset 0
/* Register rw_grp2_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
#define reg_bif_core_rw_grp2_cfg___lw___width 6
#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
#define reg_bif_core_rw_grp2_cfg___ew___width 3
#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
#define reg_bif_core_rw_grp2_cfg___zw___width 3
#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
#define reg_bif_core_rw_grp2_cfg___aw___width 2
#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
#define reg_bif_core_rw_grp2_cfg___dw___width 2
#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp2_cfg___ewb___width 2
#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
#define reg_bif_core_rw_grp2_cfg___bw___width 1
#define reg_bif_core_rw_grp2_cfg___bw___bit 18
#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
#define reg_bif_core_rw_grp2_cfg___mode___width 1
#define reg_bif_core_rw_grp2_cfg___mode___bit 21
#define reg_bif_core_rw_grp2_cfg_offset 4
/* Register rw_grp3_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
#define reg_bif_core_rw_grp3_cfg___lw___width 6
#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
#define reg_bif_core_rw_grp3_cfg___ew___width 3
#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
#define reg_bif_core_rw_grp3_cfg___zw___width 3
#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
#define reg_bif_core_rw_grp3_cfg___aw___width 2
#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
#define reg_bif_core_rw_grp3_cfg___dw___width 2
#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp3_cfg___ewb___width 2
#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
#define reg_bif_core_rw_grp3_cfg___bw___width 1
#define reg_bif_core_rw_grp3_cfg___bw___bit 18
#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
#define reg_bif_core_rw_grp3_cfg___mode___width 1
#define reg_bif_core_rw_grp3_cfg___mode___bit 21
#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
#define reg_bif_core_rw_grp3_cfg_offset 8
/* Register rw_grp4_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
#define reg_bif_core_rw_grp4_cfg___lw___width 6
#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
#define reg_bif_core_rw_grp4_cfg___ew___width 3
#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
#define reg_bif_core_rw_grp4_cfg___zw___width 3
#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
#define reg_bif_core_rw_grp4_cfg___aw___width 2
#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
#define reg_bif_core_rw_grp4_cfg___dw___width 2
#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp4_cfg___ewb___width 2
#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
#define reg_bif_core_rw_grp4_cfg___bw___width 1
#define reg_bif_core_rw_grp4_cfg___bw___bit 18
#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
#define reg_bif_core_rw_grp4_cfg___mode___width 1
#define reg_bif_core_rw_grp4_cfg___mode___bit 21
#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
#define reg_bif_core_rw_grp4_cfg_offset 12
/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
/* Register rw_sdram_timing, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_timing___cl___lsb 0
#define reg_bif_core_rw_sdram_timing___cl___width 3
#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
#define reg_bif_core_rw_sdram_timing___rcd___width 3
#define reg_bif_core_rw_sdram_timing___rp___lsb 6
#define reg_bif_core_rw_sdram_timing___rp___width 3
#define reg_bif_core_rw_sdram_timing___rc___lsb 9
#define reg_bif_core_rw_sdram_timing___rc___width 2
#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
#define reg_bif_core_rw_sdram_timing___dpl___width 2
#define reg_bif_core_rw_sdram_timing___pde___lsb 13
#define reg_bif_core_rw_sdram_timing___pde___width 1
#define reg_bif_core_rw_sdram_timing___pde___bit 13
#define reg_bif_core_rw_sdram_timing___ref___lsb 14
#define reg_bif_core_rw_sdram_timing___ref___width 2
#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
#define reg_bif_core_rw_sdram_timing___cpd___width 1
#define reg_bif_core_rw_sdram_timing___cpd___bit 16
#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
#define reg_bif_core_rw_sdram_timing___sdcke___width 1
#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
#define reg_bif_core_rw_sdram_timing___sdclk___width 1
#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
#define reg_bif_core_rw_sdram_timing_offset 24
/* Register rw_sdram_cmd, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
#define reg_bif_core_rw_sdram_cmd___cmd___width 3
#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
#define reg_bif_core_rw_sdram_cmd_offset 28
/* Register rs_sdram_ref_stat, scope bif_core, type rs */
#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
#define reg_bif_core_rs_sdram_ref_stat_offset 32
/* Register r_sdram_ref_stat, scope bif_core, type r */
#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
#define reg_bif_core_r_sdram_ref_stat___ok___width 1
#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
#define reg_bif_core_r_sdram_ref_stat_offset 36
/* Constants */
#define regk_bif_core_bank2 0x00000000
#define regk_bif_core_bank4 0x00000001
#define regk_bif_core_bit10 0x0000000a
#define regk_bif_core_bit11 0x0000000b
#define regk_bif_core_bit12 0x0000000c
#define regk_bif_core_bit13 0x0000000d
#define regk_bif_core_bit14 0x0000000e
#define regk_bif_core_bit15 0x0000000f
#define regk_bif_core_bit16 0x00000010
#define regk_bif_core_bit17 0x00000011
#define regk_bif_core_bit18 0x00000012
#define regk_bif_core_bit19 0x00000013
#define regk_bif_core_bit20 0x00000014
#define regk_bif_core_bit21 0x00000015
#define regk_bif_core_bit22 0x00000016
#define regk_bif_core_bit23 0x00000017
#define regk_bif_core_bit24 0x00000018
#define regk_bif_core_bit25 0x00000019
#define regk_bif_core_bit26 0x0000001a
#define regk_bif_core_bit27 0x0000001b
#define regk_bif_core_bit28 0x0000001c
#define regk_bif_core_bit29 0x0000001d
#define regk_bif_core_bit9 0x00000009
#define regk_bif_core_bw16 0x00000001
#define regk_bif_core_bw32 0x00000000
#define regk_bif_core_bwe 0x00000000
#define regk_bif_core_cwe 0x00000001
#define regk_bif_core_e15us 0x00000001
#define regk_bif_core_e7800ns 0x00000002
#define regk_bif_core_grp0 0x00000000
#define regk_bif_core_grp1 0x00000001
#define regk_bif_core_mrs 0x00000003
#define regk_bif_core_no 0x00000000
#define regk_bif_core_none 0x00000000
#define regk_bif_core_nop 0x00000000
#define regk_bif_core_off 0x00000000
#define regk_bif_core_pre 0x00000002
#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
#define regk_bif_core_rd 0x00000002
#define regk_bif_core_ref 0x00000001
#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
#define regk_bif_core_slf 0x00000004
#define regk_bif_core_wr 0x00000001
#define regk_bif_core_yes 0x00000001
#endif /* __bif_core_defs_asm_h */

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#ifndef __config_defs_asm_h
#define __config_defs_asm_h
/*
* This file is autogenerated from
* file: ../../rtl/config_regs.r
* id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
* last modfied: Thu Mar 4 12:34:39 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
* id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_bootsel, scope config, type r */
#define reg_config_r_bootsel___boot_mode___lsb 0
#define reg_config_r_bootsel___boot_mode___width 3
#define reg_config_r_bootsel___full_duplex___lsb 3
#define reg_config_r_bootsel___full_duplex___width 1
#define reg_config_r_bootsel___full_duplex___bit 3
#define reg_config_r_bootsel___user___lsb 4
#define reg_config_r_bootsel___user___width 1
#define reg_config_r_bootsel___user___bit 4
#define reg_config_r_bootsel___pll___lsb 5
#define reg_config_r_bootsel___pll___width 1
#define reg_config_r_bootsel___pll___bit 5
#define reg_config_r_bootsel___flash_bw___lsb 6
#define reg_config_r_bootsel___flash_bw___width 1
#define reg_config_r_bootsel___flash_bw___bit 6
#define reg_config_r_bootsel_offset 0
/* Register rw_clk_ctrl, scope config, type rw */
#define reg_config_rw_clk_ctrl___pll___lsb 0
#define reg_config_rw_clk_ctrl___pll___width 1
#define reg_config_rw_clk_ctrl___pll___bit 0
#define reg_config_rw_clk_ctrl___cpu___lsb 1
#define reg_config_rw_clk_ctrl___cpu___width 1
#define reg_config_rw_clk_ctrl___cpu___bit 1
#define reg_config_rw_clk_ctrl___iop___lsb 2
#define reg_config_rw_clk_ctrl___iop___width 1
#define reg_config_rw_clk_ctrl___iop___bit 2
#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
#define reg_config_rw_clk_ctrl___dma23___lsb 4
#define reg_config_rw_clk_ctrl___dma23___width 1
#define reg_config_rw_clk_ctrl___dma23___bit 4
#define reg_config_rw_clk_ctrl___dma45___lsb 5
#define reg_config_rw_clk_ctrl___dma45___width 1
#define reg_config_rw_clk_ctrl___dma45___bit 5
#define reg_config_rw_clk_ctrl___dma67___lsb 6
#define reg_config_rw_clk_ctrl___dma67___width 1
#define reg_config_rw_clk_ctrl___dma67___bit 6
#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
#define reg_config_rw_clk_ctrl___bif___lsb 8
#define reg_config_rw_clk_ctrl___bif___width 1
#define reg_config_rw_clk_ctrl___bif___bit 8
#define reg_config_rw_clk_ctrl___fix_io___lsb 9
#define reg_config_rw_clk_ctrl___fix_io___width 1
#define reg_config_rw_clk_ctrl___fix_io___bit 9
#define reg_config_rw_clk_ctrl_offset 4
/* Register rw_pad_ctrl, scope config, type rw */
#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
#define reg_config_rw_pad_ctrl___usb_susp___width 1
#define reg_config_rw_pad_ctrl___usb_susp___bit 0
#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
#define reg_config_rw_pad_ctrl___phyrst_n___width 1
#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
#define reg_config_rw_pad_ctrl_offset 8
/* Constants */
#define regk_config_bw16 0x00000000
#define regk_config_bw32 0x00000001
#define regk_config_master 0x00000005
#define regk_config_nand 0x00000003
#define regk_config_net_rx 0x00000001
#define regk_config_net_tx_rx 0x00000002
#define regk_config_no 0x00000000
#define regk_config_none 0x00000007
#define regk_config_nor 0x00000000
#define regk_config_rw_clk_ctrl_default 0x00000002
#define regk_config_rw_pad_ctrl_default 0x00000000
#define regk_config_ser 0x00000004
#define regk_config_slave 0x00000006
#define regk_config_yes 0x00000001
#endif /* __config_defs_asm_h */

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#ifndef __gio_defs_asm_h
#define __gio_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/gio/rtl/gio_regs.r
* id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
* last modfied: Mon Apr 11 16:07:47 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
* id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_pa_dout, scope gio, type rw */
#define reg_gio_rw_pa_dout___data___lsb 0
#define reg_gio_rw_pa_dout___data___width 8
#define reg_gio_rw_pa_dout_offset 0
/* Register r_pa_din, scope gio, type r */
#define reg_gio_r_pa_din___data___lsb 0
#define reg_gio_r_pa_din___data___width 8
#define reg_gio_r_pa_din_offset 4
/* Register rw_pa_oe, scope gio, type rw */
#define reg_gio_rw_pa_oe___oe___lsb 0
#define reg_gio_rw_pa_oe___oe___width 8
#define reg_gio_rw_pa_oe_offset 8
/* Register rw_intr_cfg, scope gio, type rw */
#define reg_gio_rw_intr_cfg___pa0___lsb 0
#define reg_gio_rw_intr_cfg___pa0___width 3
#define reg_gio_rw_intr_cfg___pa1___lsb 3
#define reg_gio_rw_intr_cfg___pa1___width 3
#define reg_gio_rw_intr_cfg___pa2___lsb 6
#define reg_gio_rw_intr_cfg___pa2___width 3
#define reg_gio_rw_intr_cfg___pa3___lsb 9
#define reg_gio_rw_intr_cfg___pa3___width 3
#define reg_gio_rw_intr_cfg___pa4___lsb 12
#define reg_gio_rw_intr_cfg___pa4___width 3
#define reg_gio_rw_intr_cfg___pa5___lsb 15
#define reg_gio_rw_intr_cfg___pa5___width 3
#define reg_gio_rw_intr_cfg___pa6___lsb 18
#define reg_gio_rw_intr_cfg___pa6___width 3
#define reg_gio_rw_intr_cfg___pa7___lsb 21
#define reg_gio_rw_intr_cfg___pa7___width 3
#define reg_gio_rw_intr_cfg_offset 12
/* Register rw_intr_mask, scope gio, type rw */
#define reg_gio_rw_intr_mask___pa0___lsb 0
#define reg_gio_rw_intr_mask___pa0___width 1
#define reg_gio_rw_intr_mask___pa0___bit 0
#define reg_gio_rw_intr_mask___pa1___lsb 1
#define reg_gio_rw_intr_mask___pa1___width 1
#define reg_gio_rw_intr_mask___pa1___bit 1
#define reg_gio_rw_intr_mask___pa2___lsb 2
#define reg_gio_rw_intr_mask___pa2___width 1
#define reg_gio_rw_intr_mask___pa2___bit 2
#define reg_gio_rw_intr_mask___pa3___lsb 3
#define reg_gio_rw_intr_mask___pa3___width 1
#define reg_gio_rw_intr_mask___pa3___bit 3
#define reg_gio_rw_intr_mask___pa4___lsb 4
#define reg_gio_rw_intr_mask___pa4___width 1
#define reg_gio_rw_intr_mask___pa4___bit 4
#define reg_gio_rw_intr_mask___pa5___lsb 5
#define reg_gio_rw_intr_mask___pa5___width 1
#define reg_gio_rw_intr_mask___pa5___bit 5
#define reg_gio_rw_intr_mask___pa6___lsb 6
#define reg_gio_rw_intr_mask___pa6___width 1
#define reg_gio_rw_intr_mask___pa6___bit 6
#define reg_gio_rw_intr_mask___pa7___lsb 7
#define reg_gio_rw_intr_mask___pa7___width 1
#define reg_gio_rw_intr_mask___pa7___bit 7
#define reg_gio_rw_intr_mask_offset 16
/* Register rw_ack_intr, scope gio, type rw */
#define reg_gio_rw_ack_intr___pa0___lsb 0
#define reg_gio_rw_ack_intr___pa0___width 1
#define reg_gio_rw_ack_intr___pa0___bit 0
#define reg_gio_rw_ack_intr___pa1___lsb 1
#define reg_gio_rw_ack_intr___pa1___width 1
#define reg_gio_rw_ack_intr___pa1___bit 1
#define reg_gio_rw_ack_intr___pa2___lsb 2
#define reg_gio_rw_ack_intr___pa2___width 1
#define reg_gio_rw_ack_intr___pa2___bit 2
#define reg_gio_rw_ack_intr___pa3___lsb 3
#define reg_gio_rw_ack_intr___pa3___width 1
#define reg_gio_rw_ack_intr___pa3___bit 3
#define reg_gio_rw_ack_intr___pa4___lsb 4
#define reg_gio_rw_ack_intr___pa4___width 1
#define reg_gio_rw_ack_intr___pa4___bit 4
#define reg_gio_rw_ack_intr___pa5___lsb 5
#define reg_gio_rw_ack_intr___pa5___width 1
#define reg_gio_rw_ack_intr___pa5___bit 5
#define reg_gio_rw_ack_intr___pa6___lsb 6
#define reg_gio_rw_ack_intr___pa6___width 1
#define reg_gio_rw_ack_intr___pa6___bit 6
#define reg_gio_rw_ack_intr___pa7___lsb 7
#define reg_gio_rw_ack_intr___pa7___width 1
#define reg_gio_rw_ack_intr___pa7___bit 7
#define reg_gio_rw_ack_intr_offset 20
/* Register r_intr, scope gio, type r */
#define reg_gio_r_intr___pa0___lsb 0
#define reg_gio_r_intr___pa0___width 1
#define reg_gio_r_intr___pa0___bit 0
#define reg_gio_r_intr___pa1___lsb 1
#define reg_gio_r_intr___pa1___width 1
#define reg_gio_r_intr___pa1___bit 1
#define reg_gio_r_intr___pa2___lsb 2
#define reg_gio_r_intr___pa2___width 1
#define reg_gio_r_intr___pa2___bit 2
#define reg_gio_r_intr___pa3___lsb 3
#define reg_gio_r_intr___pa3___width 1
#define reg_gio_r_intr___pa3___bit 3
#define reg_gio_r_intr___pa4___lsb 4
#define reg_gio_r_intr___pa4___width 1
#define reg_gio_r_intr___pa4___bit 4
#define reg_gio_r_intr___pa5___lsb 5
#define reg_gio_r_intr___pa5___width 1
#define reg_gio_r_intr___pa5___bit 5
#define reg_gio_r_intr___pa6___lsb 6
#define reg_gio_r_intr___pa6___width 1
#define reg_gio_r_intr___pa6___bit 6
#define reg_gio_r_intr___pa7___lsb 7
#define reg_gio_r_intr___pa7___width 1
#define reg_gio_r_intr___pa7___bit 7
#define reg_gio_r_intr_offset 24
/* Register r_masked_intr, scope gio, type r */
#define reg_gio_r_masked_intr___pa0___lsb 0
#define reg_gio_r_masked_intr___pa0___width 1
#define reg_gio_r_masked_intr___pa0___bit 0
#define reg_gio_r_masked_intr___pa1___lsb 1
#define reg_gio_r_masked_intr___pa1___width 1
#define reg_gio_r_masked_intr___pa1___bit 1
#define reg_gio_r_masked_intr___pa2___lsb 2
#define reg_gio_r_masked_intr___pa2___width 1
#define reg_gio_r_masked_intr___pa2___bit 2
#define reg_gio_r_masked_intr___pa3___lsb 3
#define reg_gio_r_masked_intr___pa3___width 1
#define reg_gio_r_masked_intr___pa3___bit 3
#define reg_gio_r_masked_intr___pa4___lsb 4
#define reg_gio_r_masked_intr___pa4___width 1
#define reg_gio_r_masked_intr___pa4___bit 4
#define reg_gio_r_masked_intr___pa5___lsb 5
#define reg_gio_r_masked_intr___pa5___width 1
#define reg_gio_r_masked_intr___pa5___bit 5
#define reg_gio_r_masked_intr___pa6___lsb 6
#define reg_gio_r_masked_intr___pa6___width 1
#define reg_gio_r_masked_intr___pa6___bit 6
#define reg_gio_r_masked_intr___pa7___lsb 7
#define reg_gio_r_masked_intr___pa7___width 1
#define reg_gio_r_masked_intr___pa7___bit 7
#define reg_gio_r_masked_intr_offset 28
/* Register rw_pb_dout, scope gio, type rw */
#define reg_gio_rw_pb_dout___data___lsb 0
#define reg_gio_rw_pb_dout___data___width 18
#define reg_gio_rw_pb_dout_offset 32
/* Register r_pb_din, scope gio, type r */
#define reg_gio_r_pb_din___data___lsb 0
#define reg_gio_r_pb_din___data___width 18
#define reg_gio_r_pb_din_offset 36
/* Register rw_pb_oe, scope gio, type rw */
#define reg_gio_rw_pb_oe___oe___lsb 0
#define reg_gio_rw_pb_oe___oe___width 18
#define reg_gio_rw_pb_oe_offset 40
/* Register rw_pc_dout, scope gio, type rw */
#define reg_gio_rw_pc_dout___data___lsb 0
#define reg_gio_rw_pc_dout___data___width 18
#define reg_gio_rw_pc_dout_offset 48
/* Register r_pc_din, scope gio, type r */
#define reg_gio_r_pc_din___data___lsb 0
#define reg_gio_r_pc_din___data___width 18
#define reg_gio_r_pc_din_offset 52
/* Register rw_pc_oe, scope gio, type rw */
#define reg_gio_rw_pc_oe___oe___lsb 0
#define reg_gio_rw_pc_oe___oe___width 18
#define reg_gio_rw_pc_oe_offset 56
/* Register rw_pd_dout, scope gio, type rw */
#define reg_gio_rw_pd_dout___data___lsb 0
#define reg_gio_rw_pd_dout___data___width 18
#define reg_gio_rw_pd_dout_offset 64
/* Register r_pd_din, scope gio, type r */
#define reg_gio_r_pd_din___data___lsb 0
#define reg_gio_r_pd_din___data___width 18
#define reg_gio_r_pd_din_offset 68
/* Register rw_pd_oe, scope gio, type rw */
#define reg_gio_rw_pd_oe___oe___lsb 0
#define reg_gio_rw_pd_oe___oe___width 18
#define reg_gio_rw_pd_oe_offset 72
/* Register rw_pe_dout, scope gio, type rw */
#define reg_gio_rw_pe_dout___data___lsb 0
#define reg_gio_rw_pe_dout___data___width 18
#define reg_gio_rw_pe_dout_offset 80
/* Register r_pe_din, scope gio, type r */
#define reg_gio_r_pe_din___data___lsb 0
#define reg_gio_r_pe_din___data___width 18
#define reg_gio_r_pe_din_offset 84
/* Register rw_pe_oe, scope gio, type rw */
#define reg_gio_rw_pe_oe___oe___lsb 0
#define reg_gio_rw_pe_oe___oe___width 18
#define reg_gio_rw_pe_oe_offset 88
/* Constants */
#define regk_gio_anyedge 0x00000007
#define regk_gio_hi 0x00000001
#define regk_gio_lo 0x00000002
#define regk_gio_negedge 0x00000006
#define regk_gio_no 0x00000000
#define regk_gio_off 0x00000000
#define regk_gio_posedge 0x00000005
#define regk_gio_rw_intr_cfg_default 0x00000000
#define regk_gio_rw_intr_mask_default 0x00000000
#define regk_gio_rw_pa_oe_default 0x00000000
#define regk_gio_rw_pb_oe_default 0x00000000
#define regk_gio_rw_pc_oe_default 0x00000000
#define regk_gio_rw_pd_oe_default 0x00000000
#define regk_gio_rw_pe_oe_default 0x00000000
#define regk_gio_set 0x00000003
#define regk_gio_yes 0x00000001
#endif /* __gio_defs_asm_h */

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#ifndef __pinmux_defs_asm_h
#define __pinmux_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
* last modfied: Mon Apr 11 16:09:11 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_pa, scope pinmux, type rw */
#define reg_pinmux_rw_pa___pa0___lsb 0
#define reg_pinmux_rw_pa___pa0___width 1
#define reg_pinmux_rw_pa___pa0___bit 0
#define reg_pinmux_rw_pa___pa1___lsb 1
#define reg_pinmux_rw_pa___pa1___width 1
#define reg_pinmux_rw_pa___pa1___bit 1
#define reg_pinmux_rw_pa___pa2___lsb 2
#define reg_pinmux_rw_pa___pa2___width 1
#define reg_pinmux_rw_pa___pa2___bit 2
#define reg_pinmux_rw_pa___pa3___lsb 3
#define reg_pinmux_rw_pa___pa3___width 1
#define reg_pinmux_rw_pa___pa3___bit 3
#define reg_pinmux_rw_pa___pa4___lsb 4
#define reg_pinmux_rw_pa___pa4___width 1
#define reg_pinmux_rw_pa___pa4___bit 4
#define reg_pinmux_rw_pa___pa5___lsb 5
#define reg_pinmux_rw_pa___pa5___width 1
#define reg_pinmux_rw_pa___pa5___bit 5
#define reg_pinmux_rw_pa___pa6___lsb 6
#define reg_pinmux_rw_pa___pa6___width 1
#define reg_pinmux_rw_pa___pa6___bit 6
#define reg_pinmux_rw_pa___pa7___lsb 7
#define reg_pinmux_rw_pa___pa7___width 1
#define reg_pinmux_rw_pa___pa7___bit 7
#define reg_pinmux_rw_pa___csp2_n___lsb 8
#define reg_pinmux_rw_pa___csp2_n___width 1
#define reg_pinmux_rw_pa___csp2_n___bit 8
#define reg_pinmux_rw_pa___csp3_n___lsb 9
#define reg_pinmux_rw_pa___csp3_n___width 1
#define reg_pinmux_rw_pa___csp3_n___bit 9
#define reg_pinmux_rw_pa___csp5_n___lsb 10
#define reg_pinmux_rw_pa___csp5_n___width 1
#define reg_pinmux_rw_pa___csp5_n___bit 10
#define reg_pinmux_rw_pa___csp6_n___lsb 11
#define reg_pinmux_rw_pa___csp6_n___width 1
#define reg_pinmux_rw_pa___csp6_n___bit 11
#define reg_pinmux_rw_pa___hsh4___lsb 12
#define reg_pinmux_rw_pa___hsh4___width 1
#define reg_pinmux_rw_pa___hsh4___bit 12
#define reg_pinmux_rw_pa___hsh5___lsb 13
#define reg_pinmux_rw_pa___hsh5___width 1
#define reg_pinmux_rw_pa___hsh5___bit 13
#define reg_pinmux_rw_pa___hsh6___lsb 14
#define reg_pinmux_rw_pa___hsh6___width 1
#define reg_pinmux_rw_pa___hsh6___bit 14
#define reg_pinmux_rw_pa___hsh7___lsb 15
#define reg_pinmux_rw_pa___hsh7___width 1
#define reg_pinmux_rw_pa___hsh7___bit 15
#define reg_pinmux_rw_pa_offset 0
/* Register rw_hwprot, scope pinmux, type rw */
#define reg_pinmux_rw_hwprot___ser1___lsb 0
#define reg_pinmux_rw_hwprot___ser1___width 1
#define reg_pinmux_rw_hwprot___ser1___bit 0
#define reg_pinmux_rw_hwprot___ser2___lsb 1
#define reg_pinmux_rw_hwprot___ser2___width 1
#define reg_pinmux_rw_hwprot___ser2___bit 1
#define reg_pinmux_rw_hwprot___ser3___lsb 2
#define reg_pinmux_rw_hwprot___ser3___width 1
#define reg_pinmux_rw_hwprot___ser3___bit 2
#define reg_pinmux_rw_hwprot___sser0___lsb 3
#define reg_pinmux_rw_hwprot___sser0___width 1
#define reg_pinmux_rw_hwprot___sser0___bit 3
#define reg_pinmux_rw_hwprot___sser1___lsb 4
#define reg_pinmux_rw_hwprot___sser1___width 1
#define reg_pinmux_rw_hwprot___sser1___bit 4
#define reg_pinmux_rw_hwprot___ata0___lsb 5
#define reg_pinmux_rw_hwprot___ata0___width 1
#define reg_pinmux_rw_hwprot___ata0___bit 5
#define reg_pinmux_rw_hwprot___ata1___lsb 6
#define reg_pinmux_rw_hwprot___ata1___width 1
#define reg_pinmux_rw_hwprot___ata1___bit 6
#define reg_pinmux_rw_hwprot___ata2___lsb 7
#define reg_pinmux_rw_hwprot___ata2___width 1
#define reg_pinmux_rw_hwprot___ata2___bit 7
#define reg_pinmux_rw_hwprot___ata3___lsb 8
#define reg_pinmux_rw_hwprot___ata3___width 1
#define reg_pinmux_rw_hwprot___ata3___bit 8
#define reg_pinmux_rw_hwprot___ata___lsb 9
#define reg_pinmux_rw_hwprot___ata___width 1
#define reg_pinmux_rw_hwprot___ata___bit 9
#define reg_pinmux_rw_hwprot___eth1___lsb 10
#define reg_pinmux_rw_hwprot___eth1___width 1
#define reg_pinmux_rw_hwprot___eth1___bit 10
#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
#define reg_pinmux_rw_hwprot___timer___lsb 12
#define reg_pinmux_rw_hwprot___timer___width 1
#define reg_pinmux_rw_hwprot___timer___bit 12
#define reg_pinmux_rw_hwprot___p21___lsb 13
#define reg_pinmux_rw_hwprot___p21___width 1
#define reg_pinmux_rw_hwprot___p21___bit 13
#define reg_pinmux_rw_hwprot_offset 4
/* Register rw_pb_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pb_gio___pb0___lsb 0
#define reg_pinmux_rw_pb_gio___pb0___width 1
#define reg_pinmux_rw_pb_gio___pb0___bit 0
#define reg_pinmux_rw_pb_gio___pb1___lsb 1
#define reg_pinmux_rw_pb_gio___pb1___width 1
#define reg_pinmux_rw_pb_gio___pb1___bit 1
#define reg_pinmux_rw_pb_gio___pb2___lsb 2
#define reg_pinmux_rw_pb_gio___pb2___width 1
#define reg_pinmux_rw_pb_gio___pb2___bit 2
#define reg_pinmux_rw_pb_gio___pb3___lsb 3
#define reg_pinmux_rw_pb_gio___pb3___width 1
#define reg_pinmux_rw_pb_gio___pb3___bit 3
#define reg_pinmux_rw_pb_gio___pb4___lsb 4
#define reg_pinmux_rw_pb_gio___pb4___width 1
#define reg_pinmux_rw_pb_gio___pb4___bit 4
#define reg_pinmux_rw_pb_gio___pb5___lsb 5
#define reg_pinmux_rw_pb_gio___pb5___width 1
#define reg_pinmux_rw_pb_gio___pb5___bit 5
#define reg_pinmux_rw_pb_gio___pb6___lsb 6
#define reg_pinmux_rw_pb_gio___pb6___width 1
#define reg_pinmux_rw_pb_gio___pb6___bit 6
#define reg_pinmux_rw_pb_gio___pb7___lsb 7
#define reg_pinmux_rw_pb_gio___pb7___width 1
#define reg_pinmux_rw_pb_gio___pb7___bit 7
#define reg_pinmux_rw_pb_gio___pb8___lsb 8
#define reg_pinmux_rw_pb_gio___pb8___width 1
#define reg_pinmux_rw_pb_gio___pb8___bit 8
#define reg_pinmux_rw_pb_gio___pb9___lsb 9
#define reg_pinmux_rw_pb_gio___pb9___width 1
#define reg_pinmux_rw_pb_gio___pb9___bit 9
#define reg_pinmux_rw_pb_gio___pb10___lsb 10
#define reg_pinmux_rw_pb_gio___pb10___width 1
#define reg_pinmux_rw_pb_gio___pb10___bit 10
#define reg_pinmux_rw_pb_gio___pb11___lsb 11
#define reg_pinmux_rw_pb_gio___pb11___width 1
#define reg_pinmux_rw_pb_gio___pb11___bit 11
#define reg_pinmux_rw_pb_gio___pb12___lsb 12
#define reg_pinmux_rw_pb_gio___pb12___width 1
#define reg_pinmux_rw_pb_gio___pb12___bit 12
#define reg_pinmux_rw_pb_gio___pb13___lsb 13
#define reg_pinmux_rw_pb_gio___pb13___width 1
#define reg_pinmux_rw_pb_gio___pb13___bit 13
#define reg_pinmux_rw_pb_gio___pb14___lsb 14
#define reg_pinmux_rw_pb_gio___pb14___width 1
#define reg_pinmux_rw_pb_gio___pb14___bit 14
#define reg_pinmux_rw_pb_gio___pb15___lsb 15
#define reg_pinmux_rw_pb_gio___pb15___width 1
#define reg_pinmux_rw_pb_gio___pb15___bit 15
#define reg_pinmux_rw_pb_gio___pb16___lsb 16
#define reg_pinmux_rw_pb_gio___pb16___width 1
#define reg_pinmux_rw_pb_gio___pb16___bit 16
#define reg_pinmux_rw_pb_gio___pb17___lsb 17
#define reg_pinmux_rw_pb_gio___pb17___width 1
#define reg_pinmux_rw_pb_gio___pb17___bit 17
#define reg_pinmux_rw_pb_gio_offset 8
/* Register rw_pb_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pb_iop___pb0___lsb 0
#define reg_pinmux_rw_pb_iop___pb0___width 1
#define reg_pinmux_rw_pb_iop___pb0___bit 0
#define reg_pinmux_rw_pb_iop___pb1___lsb 1
#define reg_pinmux_rw_pb_iop___pb1___width 1
#define reg_pinmux_rw_pb_iop___pb1___bit 1
#define reg_pinmux_rw_pb_iop___pb2___lsb 2
#define reg_pinmux_rw_pb_iop___pb2___width 1
#define reg_pinmux_rw_pb_iop___pb2___bit 2
#define reg_pinmux_rw_pb_iop___pb3___lsb 3
#define reg_pinmux_rw_pb_iop___pb3___width 1
#define reg_pinmux_rw_pb_iop___pb3___bit 3
#define reg_pinmux_rw_pb_iop___pb4___lsb 4
#define reg_pinmux_rw_pb_iop___pb4___width 1
#define reg_pinmux_rw_pb_iop___pb4___bit 4
#define reg_pinmux_rw_pb_iop___pb5___lsb 5
#define reg_pinmux_rw_pb_iop___pb5___width 1
#define reg_pinmux_rw_pb_iop___pb5___bit 5
#define reg_pinmux_rw_pb_iop___pb6___lsb 6
#define reg_pinmux_rw_pb_iop___pb6___width 1
#define reg_pinmux_rw_pb_iop___pb6___bit 6
#define reg_pinmux_rw_pb_iop___pb7___lsb 7
#define reg_pinmux_rw_pb_iop___pb7___width 1
#define reg_pinmux_rw_pb_iop___pb7___bit 7
#define reg_pinmux_rw_pb_iop___pb8___lsb 8
#define reg_pinmux_rw_pb_iop___pb8___width 1
#define reg_pinmux_rw_pb_iop___pb8___bit 8
#define reg_pinmux_rw_pb_iop___pb9___lsb 9
#define reg_pinmux_rw_pb_iop___pb9___width 1
#define reg_pinmux_rw_pb_iop___pb9___bit 9
#define reg_pinmux_rw_pb_iop___pb10___lsb 10
#define reg_pinmux_rw_pb_iop___pb10___width 1
#define reg_pinmux_rw_pb_iop___pb10___bit 10
#define reg_pinmux_rw_pb_iop___pb11___lsb 11
#define reg_pinmux_rw_pb_iop___pb11___width 1
#define reg_pinmux_rw_pb_iop___pb11___bit 11
#define reg_pinmux_rw_pb_iop___pb12___lsb 12
#define reg_pinmux_rw_pb_iop___pb12___width 1
#define reg_pinmux_rw_pb_iop___pb12___bit 12
#define reg_pinmux_rw_pb_iop___pb13___lsb 13
#define reg_pinmux_rw_pb_iop___pb13___width 1
#define reg_pinmux_rw_pb_iop___pb13___bit 13
#define reg_pinmux_rw_pb_iop___pb14___lsb 14
#define reg_pinmux_rw_pb_iop___pb14___width 1
#define reg_pinmux_rw_pb_iop___pb14___bit 14
#define reg_pinmux_rw_pb_iop___pb15___lsb 15
#define reg_pinmux_rw_pb_iop___pb15___width 1
#define reg_pinmux_rw_pb_iop___pb15___bit 15
#define reg_pinmux_rw_pb_iop___pb16___lsb 16
#define reg_pinmux_rw_pb_iop___pb16___width 1
#define reg_pinmux_rw_pb_iop___pb16___bit 16
#define reg_pinmux_rw_pb_iop___pb17___lsb 17
#define reg_pinmux_rw_pb_iop___pb17___width 1
#define reg_pinmux_rw_pb_iop___pb17___bit 17
#define reg_pinmux_rw_pb_iop_offset 12
/* Register rw_pc_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pc_gio___pc0___lsb 0
#define reg_pinmux_rw_pc_gio___pc0___width 1
#define reg_pinmux_rw_pc_gio___pc0___bit 0
#define reg_pinmux_rw_pc_gio___pc1___lsb 1
#define reg_pinmux_rw_pc_gio___pc1___width 1
#define reg_pinmux_rw_pc_gio___pc1___bit 1
#define reg_pinmux_rw_pc_gio___pc2___lsb 2
#define reg_pinmux_rw_pc_gio___pc2___width 1
#define reg_pinmux_rw_pc_gio___pc2___bit 2
#define reg_pinmux_rw_pc_gio___pc3___lsb 3
#define reg_pinmux_rw_pc_gio___pc3___width 1
#define reg_pinmux_rw_pc_gio___pc3___bit 3
#define reg_pinmux_rw_pc_gio___pc4___lsb 4
#define reg_pinmux_rw_pc_gio___pc4___width 1
#define reg_pinmux_rw_pc_gio___pc4___bit 4
#define reg_pinmux_rw_pc_gio___pc5___lsb 5
#define reg_pinmux_rw_pc_gio___pc5___width 1
#define reg_pinmux_rw_pc_gio___pc5___bit 5
#define reg_pinmux_rw_pc_gio___pc6___lsb 6
#define reg_pinmux_rw_pc_gio___pc6___width 1
#define reg_pinmux_rw_pc_gio___pc6___bit 6
#define reg_pinmux_rw_pc_gio___pc7___lsb 7
#define reg_pinmux_rw_pc_gio___pc7___width 1
#define reg_pinmux_rw_pc_gio___pc7___bit 7
#define reg_pinmux_rw_pc_gio___pc8___lsb 8
#define reg_pinmux_rw_pc_gio___pc8___width 1
#define reg_pinmux_rw_pc_gio___pc8___bit 8
#define reg_pinmux_rw_pc_gio___pc9___lsb 9
#define reg_pinmux_rw_pc_gio___pc9___width 1
#define reg_pinmux_rw_pc_gio___pc9___bit 9
#define reg_pinmux_rw_pc_gio___pc10___lsb 10
#define reg_pinmux_rw_pc_gio___pc10___width 1
#define reg_pinmux_rw_pc_gio___pc10___bit 10
#define reg_pinmux_rw_pc_gio___pc11___lsb 11
#define reg_pinmux_rw_pc_gio___pc11___width 1
#define reg_pinmux_rw_pc_gio___pc11___bit 11
#define reg_pinmux_rw_pc_gio___pc12___lsb 12
#define reg_pinmux_rw_pc_gio___pc12___width 1
#define reg_pinmux_rw_pc_gio___pc12___bit 12
#define reg_pinmux_rw_pc_gio___pc13___lsb 13
#define reg_pinmux_rw_pc_gio___pc13___width 1
#define reg_pinmux_rw_pc_gio___pc13___bit 13
#define reg_pinmux_rw_pc_gio___pc14___lsb 14
#define reg_pinmux_rw_pc_gio___pc14___width 1
#define reg_pinmux_rw_pc_gio___pc14___bit 14
#define reg_pinmux_rw_pc_gio___pc15___lsb 15
#define reg_pinmux_rw_pc_gio___pc15___width 1
#define reg_pinmux_rw_pc_gio___pc15___bit 15
#define reg_pinmux_rw_pc_gio___pc16___lsb 16
#define reg_pinmux_rw_pc_gio___pc16___width 1
#define reg_pinmux_rw_pc_gio___pc16___bit 16
#define reg_pinmux_rw_pc_gio___pc17___lsb 17
#define reg_pinmux_rw_pc_gio___pc17___width 1
#define reg_pinmux_rw_pc_gio___pc17___bit 17
#define reg_pinmux_rw_pc_gio_offset 16
/* Register rw_pc_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pc_iop___pc0___lsb 0
#define reg_pinmux_rw_pc_iop___pc0___width 1
#define reg_pinmux_rw_pc_iop___pc0___bit 0
#define reg_pinmux_rw_pc_iop___pc1___lsb 1
#define reg_pinmux_rw_pc_iop___pc1___width 1
#define reg_pinmux_rw_pc_iop___pc1___bit 1
#define reg_pinmux_rw_pc_iop___pc2___lsb 2
#define reg_pinmux_rw_pc_iop___pc2___width 1
#define reg_pinmux_rw_pc_iop___pc2___bit 2
#define reg_pinmux_rw_pc_iop___pc3___lsb 3
#define reg_pinmux_rw_pc_iop___pc3___width 1
#define reg_pinmux_rw_pc_iop___pc3___bit 3
#define reg_pinmux_rw_pc_iop___pc4___lsb 4
#define reg_pinmux_rw_pc_iop___pc4___width 1
#define reg_pinmux_rw_pc_iop___pc4___bit 4
#define reg_pinmux_rw_pc_iop___pc5___lsb 5
#define reg_pinmux_rw_pc_iop___pc5___width 1
#define reg_pinmux_rw_pc_iop___pc5___bit 5
#define reg_pinmux_rw_pc_iop___pc6___lsb 6
#define reg_pinmux_rw_pc_iop___pc6___width 1
#define reg_pinmux_rw_pc_iop___pc6___bit 6
#define reg_pinmux_rw_pc_iop___pc7___lsb 7
#define reg_pinmux_rw_pc_iop___pc7___width 1
#define reg_pinmux_rw_pc_iop___pc7___bit 7
#define reg_pinmux_rw_pc_iop___pc8___lsb 8
#define reg_pinmux_rw_pc_iop___pc8___width 1
#define reg_pinmux_rw_pc_iop___pc8___bit 8
#define reg_pinmux_rw_pc_iop___pc9___lsb 9
#define reg_pinmux_rw_pc_iop___pc9___width 1
#define reg_pinmux_rw_pc_iop___pc9___bit 9
#define reg_pinmux_rw_pc_iop___pc10___lsb 10
#define reg_pinmux_rw_pc_iop___pc10___width 1
#define reg_pinmux_rw_pc_iop___pc10___bit 10
#define reg_pinmux_rw_pc_iop___pc11___lsb 11
#define reg_pinmux_rw_pc_iop___pc11___width 1
#define reg_pinmux_rw_pc_iop___pc11___bit 11
#define reg_pinmux_rw_pc_iop___pc12___lsb 12
#define reg_pinmux_rw_pc_iop___pc12___width 1
#define reg_pinmux_rw_pc_iop___pc12___bit 12
#define reg_pinmux_rw_pc_iop___pc13___lsb 13
#define reg_pinmux_rw_pc_iop___pc13___width 1
#define reg_pinmux_rw_pc_iop___pc13___bit 13
#define reg_pinmux_rw_pc_iop___pc14___lsb 14
#define reg_pinmux_rw_pc_iop___pc14___width 1
#define reg_pinmux_rw_pc_iop___pc14___bit 14
#define reg_pinmux_rw_pc_iop___pc15___lsb 15
#define reg_pinmux_rw_pc_iop___pc15___width 1
#define reg_pinmux_rw_pc_iop___pc15___bit 15
#define reg_pinmux_rw_pc_iop___pc16___lsb 16
#define reg_pinmux_rw_pc_iop___pc16___width 1
#define reg_pinmux_rw_pc_iop___pc16___bit 16
#define reg_pinmux_rw_pc_iop___pc17___lsb 17
#define reg_pinmux_rw_pc_iop___pc17___width 1
#define reg_pinmux_rw_pc_iop___pc17___bit 17
#define reg_pinmux_rw_pc_iop_offset 20
/* Register rw_pd_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pd_gio___pd0___lsb 0
#define reg_pinmux_rw_pd_gio___pd0___width 1
#define reg_pinmux_rw_pd_gio___pd0___bit 0
#define reg_pinmux_rw_pd_gio___pd1___lsb 1
#define reg_pinmux_rw_pd_gio___pd1___width 1
#define reg_pinmux_rw_pd_gio___pd1___bit 1
#define reg_pinmux_rw_pd_gio___pd2___lsb 2
#define reg_pinmux_rw_pd_gio___pd2___width 1
#define reg_pinmux_rw_pd_gio___pd2___bit 2
#define reg_pinmux_rw_pd_gio___pd3___lsb 3
#define reg_pinmux_rw_pd_gio___pd3___width 1
#define reg_pinmux_rw_pd_gio___pd3___bit 3
#define reg_pinmux_rw_pd_gio___pd4___lsb 4
#define reg_pinmux_rw_pd_gio___pd4___width 1
#define reg_pinmux_rw_pd_gio___pd4___bit 4
#define reg_pinmux_rw_pd_gio___pd5___lsb 5
#define reg_pinmux_rw_pd_gio___pd5___width 1
#define reg_pinmux_rw_pd_gio___pd5___bit 5
#define reg_pinmux_rw_pd_gio___pd6___lsb 6
#define reg_pinmux_rw_pd_gio___pd6___width 1
#define reg_pinmux_rw_pd_gio___pd6___bit 6
#define reg_pinmux_rw_pd_gio___pd7___lsb 7
#define reg_pinmux_rw_pd_gio___pd7___width 1
#define reg_pinmux_rw_pd_gio___pd7___bit 7
#define reg_pinmux_rw_pd_gio___pd8___lsb 8
#define reg_pinmux_rw_pd_gio___pd8___width 1
#define reg_pinmux_rw_pd_gio___pd8___bit 8
#define reg_pinmux_rw_pd_gio___pd9___lsb 9
#define reg_pinmux_rw_pd_gio___pd9___width 1
#define reg_pinmux_rw_pd_gio___pd9___bit 9
#define reg_pinmux_rw_pd_gio___pd10___lsb 10
#define reg_pinmux_rw_pd_gio___pd10___width 1
#define reg_pinmux_rw_pd_gio___pd10___bit 10
#define reg_pinmux_rw_pd_gio___pd11___lsb 11
#define reg_pinmux_rw_pd_gio___pd11___width 1
#define reg_pinmux_rw_pd_gio___pd11___bit 11
#define reg_pinmux_rw_pd_gio___pd12___lsb 12
#define reg_pinmux_rw_pd_gio___pd12___width 1
#define reg_pinmux_rw_pd_gio___pd12___bit 12
#define reg_pinmux_rw_pd_gio___pd13___lsb 13
#define reg_pinmux_rw_pd_gio___pd13___width 1
#define reg_pinmux_rw_pd_gio___pd13___bit 13
#define reg_pinmux_rw_pd_gio___pd14___lsb 14
#define reg_pinmux_rw_pd_gio___pd14___width 1
#define reg_pinmux_rw_pd_gio___pd14___bit 14
#define reg_pinmux_rw_pd_gio___pd15___lsb 15
#define reg_pinmux_rw_pd_gio___pd15___width 1
#define reg_pinmux_rw_pd_gio___pd15___bit 15
#define reg_pinmux_rw_pd_gio___pd16___lsb 16
#define reg_pinmux_rw_pd_gio___pd16___width 1
#define reg_pinmux_rw_pd_gio___pd16___bit 16
#define reg_pinmux_rw_pd_gio___pd17___lsb 17
#define reg_pinmux_rw_pd_gio___pd17___width 1
#define reg_pinmux_rw_pd_gio___pd17___bit 17
#define reg_pinmux_rw_pd_gio_offset 24
/* Register rw_pd_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pd_iop___pd0___lsb 0
#define reg_pinmux_rw_pd_iop___pd0___width 1
#define reg_pinmux_rw_pd_iop___pd0___bit 0
#define reg_pinmux_rw_pd_iop___pd1___lsb 1
#define reg_pinmux_rw_pd_iop___pd1___width 1
#define reg_pinmux_rw_pd_iop___pd1___bit 1
#define reg_pinmux_rw_pd_iop___pd2___lsb 2
#define reg_pinmux_rw_pd_iop___pd2___width 1
#define reg_pinmux_rw_pd_iop___pd2___bit 2
#define reg_pinmux_rw_pd_iop___pd3___lsb 3
#define reg_pinmux_rw_pd_iop___pd3___width 1
#define reg_pinmux_rw_pd_iop___pd3___bit 3
#define reg_pinmux_rw_pd_iop___pd4___lsb 4
#define reg_pinmux_rw_pd_iop___pd4___width 1
#define reg_pinmux_rw_pd_iop___pd4___bit 4
#define reg_pinmux_rw_pd_iop___pd5___lsb 5
#define reg_pinmux_rw_pd_iop___pd5___width 1
#define reg_pinmux_rw_pd_iop___pd5___bit 5
#define reg_pinmux_rw_pd_iop___pd6___lsb 6
#define reg_pinmux_rw_pd_iop___pd6___width 1
#define reg_pinmux_rw_pd_iop___pd6___bit 6
#define reg_pinmux_rw_pd_iop___pd7___lsb 7
#define reg_pinmux_rw_pd_iop___pd7___width 1
#define reg_pinmux_rw_pd_iop___pd7___bit 7
#define reg_pinmux_rw_pd_iop___pd8___lsb 8
#define reg_pinmux_rw_pd_iop___pd8___width 1
#define reg_pinmux_rw_pd_iop___pd8___bit 8
#define reg_pinmux_rw_pd_iop___pd9___lsb 9
#define reg_pinmux_rw_pd_iop___pd9___width 1
#define reg_pinmux_rw_pd_iop___pd9___bit 9
#define reg_pinmux_rw_pd_iop___pd10___lsb 10
#define reg_pinmux_rw_pd_iop___pd10___width 1
#define reg_pinmux_rw_pd_iop___pd10___bit 10
#define reg_pinmux_rw_pd_iop___pd11___lsb 11
#define reg_pinmux_rw_pd_iop___pd11___width 1
#define reg_pinmux_rw_pd_iop___pd11___bit 11
#define reg_pinmux_rw_pd_iop___pd12___lsb 12
#define reg_pinmux_rw_pd_iop___pd12___width 1
#define reg_pinmux_rw_pd_iop___pd12___bit 12
#define reg_pinmux_rw_pd_iop___pd13___lsb 13
#define reg_pinmux_rw_pd_iop___pd13___width 1
#define reg_pinmux_rw_pd_iop___pd13___bit 13
#define reg_pinmux_rw_pd_iop___pd14___lsb 14
#define reg_pinmux_rw_pd_iop___pd14___width 1
#define reg_pinmux_rw_pd_iop___pd14___bit 14
#define reg_pinmux_rw_pd_iop___pd15___lsb 15
#define reg_pinmux_rw_pd_iop___pd15___width 1
#define reg_pinmux_rw_pd_iop___pd15___bit 15
#define reg_pinmux_rw_pd_iop___pd16___lsb 16
#define reg_pinmux_rw_pd_iop___pd16___width 1
#define reg_pinmux_rw_pd_iop___pd16___bit 16
#define reg_pinmux_rw_pd_iop___pd17___lsb 17
#define reg_pinmux_rw_pd_iop___pd17___width 1
#define reg_pinmux_rw_pd_iop___pd17___bit 17
#define reg_pinmux_rw_pd_iop_offset 28
/* Register rw_pe_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pe_gio___pe0___lsb 0
#define reg_pinmux_rw_pe_gio___pe0___width 1
#define reg_pinmux_rw_pe_gio___pe0___bit 0
#define reg_pinmux_rw_pe_gio___pe1___lsb 1
#define reg_pinmux_rw_pe_gio___pe1___width 1
#define reg_pinmux_rw_pe_gio___pe1___bit 1
#define reg_pinmux_rw_pe_gio___pe2___lsb 2
#define reg_pinmux_rw_pe_gio___pe2___width 1
#define reg_pinmux_rw_pe_gio___pe2___bit 2
#define reg_pinmux_rw_pe_gio___pe3___lsb 3
#define reg_pinmux_rw_pe_gio___pe3___width 1
#define reg_pinmux_rw_pe_gio___pe3___bit 3
#define reg_pinmux_rw_pe_gio___pe4___lsb 4
#define reg_pinmux_rw_pe_gio___pe4___width 1
#define reg_pinmux_rw_pe_gio___pe4___bit 4
#define reg_pinmux_rw_pe_gio___pe5___lsb 5
#define reg_pinmux_rw_pe_gio___pe5___width 1
#define reg_pinmux_rw_pe_gio___pe5___bit 5
#define reg_pinmux_rw_pe_gio___pe6___lsb 6
#define reg_pinmux_rw_pe_gio___pe6___width 1
#define reg_pinmux_rw_pe_gio___pe6___bit 6
#define reg_pinmux_rw_pe_gio___pe7___lsb 7
#define reg_pinmux_rw_pe_gio___pe7___width 1
#define reg_pinmux_rw_pe_gio___pe7___bit 7
#define reg_pinmux_rw_pe_gio___pe8___lsb 8
#define reg_pinmux_rw_pe_gio___pe8___width 1
#define reg_pinmux_rw_pe_gio___pe8___bit 8
#define reg_pinmux_rw_pe_gio___pe9___lsb 9
#define reg_pinmux_rw_pe_gio___pe9___width 1
#define reg_pinmux_rw_pe_gio___pe9___bit 9
#define reg_pinmux_rw_pe_gio___pe10___lsb 10
#define reg_pinmux_rw_pe_gio___pe10___width 1
#define reg_pinmux_rw_pe_gio___pe10___bit 10
#define reg_pinmux_rw_pe_gio___pe11___lsb 11
#define reg_pinmux_rw_pe_gio___pe11___width 1
#define reg_pinmux_rw_pe_gio___pe11___bit 11
#define reg_pinmux_rw_pe_gio___pe12___lsb 12
#define reg_pinmux_rw_pe_gio___pe12___width 1
#define reg_pinmux_rw_pe_gio___pe12___bit 12
#define reg_pinmux_rw_pe_gio___pe13___lsb 13
#define reg_pinmux_rw_pe_gio___pe13___width 1
#define reg_pinmux_rw_pe_gio___pe13___bit 13
#define reg_pinmux_rw_pe_gio___pe14___lsb 14
#define reg_pinmux_rw_pe_gio___pe14___width 1
#define reg_pinmux_rw_pe_gio___pe14___bit 14
#define reg_pinmux_rw_pe_gio___pe15___lsb 15
#define reg_pinmux_rw_pe_gio___pe15___width 1
#define reg_pinmux_rw_pe_gio___pe15___bit 15
#define reg_pinmux_rw_pe_gio___pe16___lsb 16
#define reg_pinmux_rw_pe_gio___pe16___width 1
#define reg_pinmux_rw_pe_gio___pe16___bit 16
#define reg_pinmux_rw_pe_gio___pe17___lsb 17
#define reg_pinmux_rw_pe_gio___pe17___width 1
#define reg_pinmux_rw_pe_gio___pe17___bit 17
#define reg_pinmux_rw_pe_gio_offset 32
/* Register rw_pe_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pe_iop___pe0___lsb 0
#define reg_pinmux_rw_pe_iop___pe0___width 1
#define reg_pinmux_rw_pe_iop___pe0___bit 0
#define reg_pinmux_rw_pe_iop___pe1___lsb 1
#define reg_pinmux_rw_pe_iop___pe1___width 1
#define reg_pinmux_rw_pe_iop___pe1___bit 1
#define reg_pinmux_rw_pe_iop___pe2___lsb 2
#define reg_pinmux_rw_pe_iop___pe2___width 1
#define reg_pinmux_rw_pe_iop___pe2___bit 2
#define reg_pinmux_rw_pe_iop___pe3___lsb 3
#define reg_pinmux_rw_pe_iop___pe3___width 1
#define reg_pinmux_rw_pe_iop___pe3___bit 3
#define reg_pinmux_rw_pe_iop___pe4___lsb 4
#define reg_pinmux_rw_pe_iop___pe4___width 1
#define reg_pinmux_rw_pe_iop___pe4___bit 4
#define reg_pinmux_rw_pe_iop___pe5___lsb 5
#define reg_pinmux_rw_pe_iop___pe5___width 1
#define reg_pinmux_rw_pe_iop___pe5___bit 5
#define reg_pinmux_rw_pe_iop___pe6___lsb 6
#define reg_pinmux_rw_pe_iop___pe6___width 1
#define reg_pinmux_rw_pe_iop___pe6___bit 6
#define reg_pinmux_rw_pe_iop___pe7___lsb 7
#define reg_pinmux_rw_pe_iop___pe7___width 1
#define reg_pinmux_rw_pe_iop___pe7___bit 7
#define reg_pinmux_rw_pe_iop___pe8___lsb 8
#define reg_pinmux_rw_pe_iop___pe8___width 1
#define reg_pinmux_rw_pe_iop___pe8___bit 8
#define reg_pinmux_rw_pe_iop___pe9___lsb 9
#define reg_pinmux_rw_pe_iop___pe9___width 1
#define reg_pinmux_rw_pe_iop___pe9___bit 9
#define reg_pinmux_rw_pe_iop___pe10___lsb 10
#define reg_pinmux_rw_pe_iop___pe10___width 1
#define reg_pinmux_rw_pe_iop___pe10___bit 10
#define reg_pinmux_rw_pe_iop___pe11___lsb 11
#define reg_pinmux_rw_pe_iop___pe11___width 1
#define reg_pinmux_rw_pe_iop___pe11___bit 11
#define reg_pinmux_rw_pe_iop___pe12___lsb 12
#define reg_pinmux_rw_pe_iop___pe12___width 1
#define reg_pinmux_rw_pe_iop___pe12___bit 12
#define reg_pinmux_rw_pe_iop___pe13___lsb 13
#define reg_pinmux_rw_pe_iop___pe13___width 1
#define reg_pinmux_rw_pe_iop___pe13___bit 13
#define reg_pinmux_rw_pe_iop___pe14___lsb 14
#define reg_pinmux_rw_pe_iop___pe14___width 1
#define reg_pinmux_rw_pe_iop___pe14___bit 14
#define reg_pinmux_rw_pe_iop___pe15___lsb 15
#define reg_pinmux_rw_pe_iop___pe15___width 1
#define reg_pinmux_rw_pe_iop___pe15___bit 15
#define reg_pinmux_rw_pe_iop___pe16___lsb 16
#define reg_pinmux_rw_pe_iop___pe16___width 1
#define reg_pinmux_rw_pe_iop___pe16___bit 16
#define reg_pinmux_rw_pe_iop___pe17___lsb 17
#define reg_pinmux_rw_pe_iop___pe17___width 1
#define reg_pinmux_rw_pe_iop___pe17___bit 17
#define reg_pinmux_rw_pe_iop_offset 36
/* Register rw_usb_phy, scope pinmux, type rw */
#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
#define reg_pinmux_rw_usb_phy___en_usb0___width 1
#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
#define reg_pinmux_rw_usb_phy___en_usb1___width 1
#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
#define reg_pinmux_rw_usb_phy_offset 40
/* Constants */
#define regk_pinmux_no 0x00000000
#define regk_pinmux_rw_hwprot_default 0x00000000
#define regk_pinmux_rw_pa_default 0x00000000
#define regk_pinmux_rw_pb_gio_default 0x00000000
#define regk_pinmux_rw_pb_iop_default 0x00000000
#define regk_pinmux_rw_pc_gio_default 0x00000000
#define regk_pinmux_rw_pc_iop_default 0x00000000
#define regk_pinmux_rw_pd_gio_default 0x00000000
#define regk_pinmux_rw_pd_iop_default 0x00000000
#define regk_pinmux_rw_pe_gio_default 0x00000000
#define regk_pinmux_rw_pe_iop_default 0x00000000
#define regk_pinmux_rw_usb_phy_default 0x00000000
#define regk_pinmux_yes 0x00000001
#endif /* __pinmux_defs_asm_h */

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include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h Normal file
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#ifndef __reg_map_h
#define __reg_map_h
/*
* This file is autogenerated from
* file: ../../mod/fakereg.rmap
* id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
* last modified: Wed Feb 11 20:53:25 2004
* file: ../../rtl/global.rmap
* id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
* last modified: Mon Aug 18 17:08:23 2003
* file: ../../mod/modreg.rmap
* id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
* last modified: Fri Feb 20 16:40:04 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
* id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#define regi_artpec_mod 0xb7044000
#define regi_ata 0xb0032000
#define regi_ata_mod 0xb7006000
#define regi_barber 0xb701a000
#define regi_bif_core 0xb0014000
#define regi_bif_dma 0xb0016000
#define regi_bif_slave 0xb0018000
#define regi_bif_slave_ext 0xac000000
#define regi_bus_master 0xb703c000
#define regi_config 0xb003c000
#define regi_dma0 0xb0000000
#define regi_dma1 0xb0002000
#define regi_dma2 0xb0004000
#define regi_dma3 0xb0006000
#define regi_dma4 0xb0008000
#define regi_dma5 0xb000a000
#define regi_dma6 0xb000c000
#define regi_dma7 0xb000e000
#define regi_dma8 0xb0010000
#define regi_dma9 0xb0012000
#define regi_eth0 0xb0034000
#define regi_eth1 0xb0036000
#define regi_eth_mod 0xb7004000
#define regi_eth_mod1 0xb701c000
#define regi_eth_strmod 0xb7008000
#define regi_eth_strmod1 0xb7032000
#define regi_ext_dma 0xb703a000
#define regi_ext_mem 0xb7046000
#define regi_gen_io 0xb7016000
#define regi_gio 0xb001a000
#define regi_hook 0xb7000000
#define regi_iop 0xb0020000
#define regi_irq 0xb001c000
#define regi_irq_nmi 0xb701e000
#define regi_marb 0xb003e000
#define regi_marb_bp0 0xb003e240
#define regi_marb_bp1 0xb003e280
#define regi_marb_bp2 0xb003e2c0
#define regi_marb_bp3 0xb003e300
#define regi_nand_mod 0xb7014000
#define regi_p21 0xb002e000
#define regi_p21_mod 0xb7042000
#define regi_pci_mod 0xb7010000
#define regi_pin_test 0xb7018000
#define regi_pinmux 0xb0038000
#define regi_sdram_chk 0xb703e000
#define regi_sdram_mod 0xb7012000
#define regi_ser0 0xb0026000
#define regi_ser1 0xb0028000
#define regi_ser2 0xb002a000
#define regi_ser3 0xb002c000
#define regi_ser_mod0 0xb7020000
#define regi_ser_mod1 0xb7022000
#define regi_ser_mod2 0xb7024000
#define regi_ser_mod3 0xb7026000
#define regi_smif_stat 0xb700e000
#define regi_sser0 0xb0022000
#define regi_sser1 0xb0024000
#define regi_sser_mod0 0xb700a000
#define regi_sser_mod1 0xb700c000
#define regi_strcop 0xb0030000
#define regi_strmux 0xb003a000
#define regi_strmux_tst 0xb7040000
#define regi_tap 0xb7002000
#define regi_timer 0xb001e000
#define regi_timer_mod 0xb7034000
#define regi_trace 0xb0040000
#define regi_usb0 0xb7028000
#define regi_usb1 0xb702a000
#define regi_usb2 0xb702c000
#define regi_usb3 0xb702e000
#define regi_usb_dev 0xb7030000
#define regi_utmi_mod0 0xb7036000
#define regi_utmi_mod1 0xb7038000
#endif /* __reg_map_h */

229
include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h Normal file
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#ifndef __timer_defs_asm_h
#define __timer_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/timer/rtl/timer_regs.r
* id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
* last modfied: Mon Apr 11 16:09:53 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
* id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_tmr0_div, scope timer, type rw */
#define reg_timer_rw_tmr0_div_offset 0
/* Register r_tmr0_data, scope timer, type r */
#define reg_timer_r_tmr0_data_offset 4
/* Register rw_tmr0_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr0_ctrl___op___lsb 0
#define reg_timer_rw_tmr0_ctrl___op___width 2
#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
#define reg_timer_rw_tmr0_ctrl___freq___width 3
#define reg_timer_rw_tmr0_ctrl_offset 8
/* Register rw_tmr1_div, scope timer, type rw */
#define reg_timer_rw_tmr1_div_offset 16
/* Register r_tmr1_data, scope timer, type r */
#define reg_timer_r_tmr1_data_offset 20
/* Register rw_tmr1_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr1_ctrl___op___lsb 0
#define reg_timer_rw_tmr1_ctrl___op___width 2
#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
#define reg_timer_rw_tmr1_ctrl___freq___width 3
#define reg_timer_rw_tmr1_ctrl_offset 24
/* Register rs_cnt_data, scope timer, type rs */
#define reg_timer_rs_cnt_data___tmr___lsb 0
#define reg_timer_rs_cnt_data___tmr___width 24
#define reg_timer_rs_cnt_data___cnt___lsb 24
#define reg_timer_rs_cnt_data___cnt___width 8
#define reg_timer_rs_cnt_data_offset 32
/* Register r_cnt_data, scope timer, type r */
#define reg_timer_r_cnt_data___tmr___lsb 0
#define reg_timer_r_cnt_data___tmr___width 24
#define reg_timer_r_cnt_data___cnt___lsb 24
#define reg_timer_r_cnt_data___cnt___width 8
#define reg_timer_r_cnt_data_offset 36
/* Register rw_cnt_cfg, scope timer, type rw */
#define reg_timer_rw_cnt_cfg___clk___lsb 0
#define reg_timer_rw_cnt_cfg___clk___width 2
#define reg_timer_rw_cnt_cfg_offset 40
/* Register rw_trig, scope timer, type rw */
#define reg_timer_rw_trig_offset 48
/* Register rw_trig_cfg, scope timer, type rw */
#define reg_timer_rw_trig_cfg___tmr___lsb 0
#define reg_timer_rw_trig_cfg___tmr___width 2
#define reg_timer_rw_trig_cfg_offset 52
/* Register r_time, scope timer, type r */
#define reg_timer_r_time_offset 56
/* Register rw_out, scope timer, type rw */
#define reg_timer_rw_out___tmr___lsb 0
#define reg_timer_rw_out___tmr___width 2
#define reg_timer_rw_out_offset 60
/* Register rw_wd_ctrl, scope timer, type rw */
#define reg_timer_rw_wd_ctrl___cnt___lsb 0
#define reg_timer_rw_wd_ctrl___cnt___width 8
#define reg_timer_rw_wd_ctrl___cmd___lsb 8
#define reg_timer_rw_wd_ctrl___cmd___width 1
#define reg_timer_rw_wd_ctrl___cmd___bit 8
#define reg_timer_rw_wd_ctrl___key___lsb 9
#define reg_timer_rw_wd_ctrl___key___width 7
#define reg_timer_rw_wd_ctrl_offset 64
/* Register r_wd_stat, scope timer, type r */
#define reg_timer_r_wd_stat___cnt___lsb 0
#define reg_timer_r_wd_stat___cnt___width 8
#define reg_timer_r_wd_stat___cmd___lsb 8
#define reg_timer_r_wd_stat___cmd___width 1
#define reg_timer_r_wd_stat___cmd___bit 8
#define reg_timer_r_wd_stat_offset 68
/* Register rw_intr_mask, scope timer, type rw */
#define reg_timer_rw_intr_mask___tmr0___lsb 0
#define reg_timer_rw_intr_mask___tmr0___width 1
#define reg_timer_rw_intr_mask___tmr0___bit 0
#define reg_timer_rw_intr_mask___tmr1___lsb 1
#define reg_timer_rw_intr_mask___tmr1___width 1
#define reg_timer_rw_intr_mask___tmr1___bit 1
#define reg_timer_rw_intr_mask___cnt___lsb 2
#define reg_timer_rw_intr_mask___cnt___width 1
#define reg_timer_rw_intr_mask___cnt___bit 2
#define reg_timer_rw_intr_mask___trig___lsb 3
#define reg_timer_rw_intr_mask___trig___width 1
#define reg_timer_rw_intr_mask___trig___bit 3
#define reg_timer_rw_intr_mask_offset 72
/* Register rw_ack_intr, scope timer, type rw */
#define reg_timer_rw_ack_intr___tmr0___lsb 0
#define reg_timer_rw_ack_intr___tmr0___width 1
#define reg_timer_rw_ack_intr___tmr0___bit 0
#define reg_timer_rw_ack_intr___tmr1___lsb 1
#define reg_timer_rw_ack_intr___tmr1___width 1
#define reg_timer_rw_ack_intr___tmr1___bit 1
#define reg_timer_rw_ack_intr___cnt___lsb 2
#define reg_timer_rw_ack_intr___cnt___width 1
#define reg_timer_rw_ack_intr___cnt___bit 2
#define reg_timer_rw_ack_intr___trig___lsb 3
#define reg_timer_rw_ack_intr___trig___width 1
#define reg_timer_rw_ack_intr___trig___bit 3
#define reg_timer_rw_ack_intr_offset 76
/* Register r_intr, scope timer, type r */
#define reg_timer_r_intr___tmr0___lsb 0
#define reg_timer_r_intr___tmr0___width 1
#define reg_timer_r_intr___tmr0___bit 0
#define reg_timer_r_intr___tmr1___lsb 1
#define reg_timer_r_intr___tmr1___width 1
#define reg_timer_r_intr___tmr1___bit 1
#define reg_timer_r_intr___cnt___lsb 2
#define reg_timer_r_intr___cnt___width 1
#define reg_timer_r_intr___cnt___bit 2
#define reg_timer_r_intr___trig___lsb 3
#define reg_timer_r_intr___trig___width 1
#define reg_timer_r_intr___trig___bit 3
#define reg_timer_r_intr_offset 80
/* Register r_masked_intr, scope timer, type r */
#define reg_timer_r_masked_intr___tmr0___lsb 0
#define reg_timer_r_masked_intr___tmr0___width 1
#define reg_timer_r_masked_intr___tmr0___bit 0
#define reg_timer_r_masked_intr___tmr1___lsb 1
#define reg_timer_r_masked_intr___tmr1___width 1
#define reg_timer_r_masked_intr___tmr1___bit 1
#define reg_timer_r_masked_intr___cnt___lsb 2
#define reg_timer_r_masked_intr___cnt___width 1
#define reg_timer_r_masked_intr___cnt___bit 2
#define reg_timer_r_masked_intr___trig___lsb 3
#define reg_timer_r_masked_intr___trig___width 1
#define reg_timer_r_masked_intr___trig___bit 3
#define reg_timer_r_masked_intr_offset 84
/* Register rw_test, scope timer, type rw */
#define reg_timer_rw_test___dis___lsb 0
#define reg_timer_rw_test___dis___width 1
#define reg_timer_rw_test___dis___bit 0
#define reg_timer_rw_test___en___lsb 1
#define reg_timer_rw_test___en___width 1
#define reg_timer_rw_test___en___bit 1
#define reg_timer_rw_test_offset 88
/* Constants */
#define regk_timer_ext 0x00000001
#define regk_timer_f100 0x00000007
#define regk_timer_f29_493 0x00000004
#define regk_timer_f32 0x00000005
#define regk_timer_f32_768 0x00000006
#define regk_timer_hold 0x00000001
#define regk_timer_ld 0x00000000
#define regk_timer_no 0x00000000
#define regk_timer_off 0x00000000
#define regk_timer_run 0x00000002
#define regk_timer_rw_cnt_cfg_default 0x00000000
#define regk_timer_rw_intr_mask_default 0x00000000
#define regk_timer_rw_out_default 0x00000000
#define regk_timer_rw_test_default 0x00000000
#define regk_timer_rw_tmr0_ctrl_default 0x00000000
#define regk_timer_rw_tmr1_ctrl_default 0x00000000
#define regk_timer_rw_trig_cfg_default 0x00000000
#define regk_timer_start 0x00000001
#define regk_timer_stop 0x00000000
#define regk_timer_time 0x00000001
#define regk_timer_tmr0 0x00000002
#define regk_timer_tmr1 0x00000003
#define regk_timer_yes 0x00000001
#endif /* __timer_defs_asm_h */

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#ifndef __bif_core_defs_h
#define __bif_core_defs_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_core_regs.r
* id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
* last modfied: Mon Apr 11 16:06:33 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
* id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope bif_core */
/* Register rw_grp1_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 10;
} reg_bif_core_rw_grp1_cfg;
#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
/* Register rw_grp2_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 10;
} reg_bif_core_rw_grp2_cfg;
#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
/* Register rw_grp3_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 2;
unsigned int gated_csp0 : 2;
unsigned int gated_csp1 : 2;
unsigned int gated_csp2 : 2;
unsigned int gated_csp3 : 2;
} reg_bif_core_rw_grp3_cfg;
#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
/* Register rw_grp4_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 4;
unsigned int gated_csp4 : 2;
unsigned int gated_csp5 : 2;
unsigned int gated_csp6 : 2;
} reg_bif_core_rw_grp4_cfg;
#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
typedef struct {
unsigned int bank_sel : 5;
unsigned int ca : 3;
unsigned int type : 1;
unsigned int bw : 1;
unsigned int sh : 3;
unsigned int wmm : 1;
unsigned int sh16 : 1;
unsigned int grp_sel : 5;
unsigned int dummy1 : 12;
} reg_bif_core_rw_sdram_cfg_grp0;
#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
typedef struct {
unsigned int bank_sel : 5;
unsigned int ca : 3;
unsigned int type : 1;
unsigned int bw : 1;
unsigned int sh : 3;
unsigned int wmm : 1;
unsigned int sh16 : 1;
unsigned int dummy1 : 17;
} reg_bif_core_rw_sdram_cfg_grp1;
#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
/* Register rw_sdram_timing, scope bif_core, type rw */
typedef struct {
unsigned int cl : 3;
unsigned int rcd : 3;
unsigned int rp : 3;
unsigned int rc : 2;
unsigned int dpl : 2;
unsigned int pde : 1;
unsigned int ref : 2;
unsigned int cpd : 1;
unsigned int sdcke : 1;
unsigned int sdclk : 1;
unsigned int dummy1 : 13;
} reg_bif_core_rw_sdram_timing;
#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
/* Register rw_sdram_cmd, scope bif_core, type rw */
typedef struct {
unsigned int cmd : 3;
unsigned int mrs_data : 15;
unsigned int dummy1 : 14;
} reg_bif_core_rw_sdram_cmd;
#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
/* Register rs_sdram_ref_stat, scope bif_core, type rs */
typedef struct {
unsigned int ok : 1;
unsigned int dummy1 : 31;
} reg_bif_core_rs_sdram_ref_stat;
#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
/* Register r_sdram_ref_stat, scope bif_core, type r */
typedef struct {
unsigned int ok : 1;
unsigned int dummy1 : 31;
} reg_bif_core_r_sdram_ref_stat;
#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
/* Constants */
enum {
regk_bif_core_bank2 = 0x00000000,
regk_bif_core_bank4 = 0x00000001,
regk_bif_core_bit10 = 0x0000000a,
regk_bif_core_bit11 = 0x0000000b,
regk_bif_core_bit12 = 0x0000000c,
regk_bif_core_bit13 = 0x0000000d,
regk_bif_core_bit14 = 0x0000000e,
regk_bif_core_bit15 = 0x0000000f,
regk_bif_core_bit16 = 0x00000010,
regk_bif_core_bit17 = 0x00000011,
regk_bif_core_bit18 = 0x00000012,
regk_bif_core_bit19 = 0x00000013,
regk_bif_core_bit20 = 0x00000014,
regk_bif_core_bit21 = 0x00000015,
regk_bif_core_bit22 = 0x00000016,
regk_bif_core_bit23 = 0x00000017,
regk_bif_core_bit24 = 0x00000018,
regk_bif_core_bit25 = 0x00000019,
regk_bif_core_bit26 = 0x0000001a,
regk_bif_core_bit27 = 0x0000001b,
regk_bif_core_bit28 = 0x0000001c,
regk_bif_core_bit29 = 0x0000001d,
regk_bif_core_bit9 = 0x00000009,
regk_bif_core_bw16 = 0x00000001,
regk_bif_core_bw32 = 0x00000000,
regk_bif_core_bwe = 0x00000000,
regk_bif_core_cwe = 0x00000001,
regk_bif_core_e15us = 0x00000001,
regk_bif_core_e7800ns = 0x00000002,
regk_bif_core_grp0 = 0x00000000,
regk_bif_core_grp1 = 0x00000001,
regk_bif_core_mrs = 0x00000003,
regk_bif_core_no = 0x00000000,
regk_bif_core_none = 0x00000000,
regk_bif_core_nop = 0x00000000,
regk_bif_core_off = 0x00000000,
regk_bif_core_pre = 0x00000002,
regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
regk_bif_core_rd = 0x00000002,
regk_bif_core_ref = 0x00000001,
regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
regk_bif_core_slf = 0x00000004,
regk_bif_core_wr = 0x00000001,
regk_bif_core_yes = 0x00000001
};
#endif /* __bif_core_defs_h */

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#ifndef __bif_dma_defs_h
#define __bif_dma_defs_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_dma_regs.r
* id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
* last modfied: Mon Apr 11 16:06:33 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
* id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope bif_dma */
/* Register rw_ch0_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_pad : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int wr_all : 1;
unsigned int dummy1 : 12;
} reg_bif_dma_rw_ch0_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
/* Register rw_ch0_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch0_addr;
#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
/* Register rw_ch0_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch0_start;
#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
/* Register rw_ch0_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch0_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
/* Register r_ch0_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch0_stat;
#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
/* Register rw_ch1_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_discard : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int dummy1 : 13;
} reg_bif_dma_rw_ch1_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
/* Register rw_ch1_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch1_addr;
#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
/* Register rw_ch1_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch1_start;
#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
/* Register rw_ch1_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch1_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
/* Register r_ch1_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch1_stat;
#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
/* Register rw_ch2_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_pad : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int wr_all : 1;
unsigned int dummy1 : 12;
} reg_bif_dma_rw_ch2_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
/* Register rw_ch2_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch2_addr;
#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
/* Register rw_ch2_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch2_start;
#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
/* Register rw_ch2_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch2_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
/* Register r_ch2_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch2_stat;
#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
/* Register rw_ch3_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_discard : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int dummy1 : 13;
} reg_bif_dma_rw_ch3_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
/* Register rw_ch3_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch3_addr;
#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
/* Register rw_ch3_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch3_start;
#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
/* Register rw_ch3_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch3_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
/* Register r_ch3_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch3_stat;
#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
/* Register rw_intr_mask, scope bif_dma, type rw */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_rw_intr_mask;
#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
/* Register rw_ack_intr, scope bif_dma, type rw */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_rw_ack_intr;
#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
/* Register r_intr, scope bif_dma, type r */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_r_intr;
#define REG_RD_ADDR_bif_dma_r_intr 136
/* Register r_masked_intr, scope bif_dma, type r */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_r_masked_intr;
#define REG_RD_ADDR_bif_dma_r_masked_intr 140
/* Register rw_pin0_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin0_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
/* Register rw_pin1_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin1_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
/* Register rw_pin2_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin2_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
/* Register rw_pin3_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin3_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
/* Register rw_pin4_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin4_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
/* Register rw_pin5_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin5_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
/* Register rw_pin6_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin6_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
/* Register rw_pin7_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin7_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
/* Register r_pin_stat, scope bif_dma, type r */
typedef struct {
unsigned int pin0 : 1;
unsigned int pin1 : 1;
unsigned int pin2 : 1;
unsigned int pin3 : 1;
unsigned int pin4 : 1;
unsigned int pin5 : 1;
unsigned int pin6 : 1;
unsigned int pin7 : 1;
unsigned int dummy1 : 24;
} reg_bif_dma_r_pin_stat;
#define REG_RD_ADDR_bif_dma_r_pin_stat 192
/* Constants */
enum {
regk_bif_dma_as_master = 0x00000001,
regk_bif_dma_as_slave = 0x00000001,
regk_bif_dma_burst1 = 0x00000000,
regk_bif_dma_burst8 = 0x00000001,
regk_bif_dma_bw16 = 0x00000001,
regk_bif_dma_bw32 = 0x00000002,
regk_bif_dma_bw8 = 0x00000000,
regk_bif_dma_dack = 0x00000006,
regk_bif_dma_dack_inv = 0x00000007,
regk_bif_dma_force = 0x00000001,
regk_bif_dma_hi = 0x00000003,
regk_bif_dma_inv = 0x00000003,
regk_bif_dma_lo = 0x00000002,
regk_bif_dma_master = 0x00000001,
regk_bif_dma_no = 0x00000000,
regk_bif_dma_norm = 0x00000002,
regk_bif_dma_off = 0x00000000,
regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch0_start_default = 0x00000000,
regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch1_start_default = 0x00000000,
regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch2_start_default = 0x00000000,
regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch3_start_default = 0x00000000,
regk_bif_dma_rw_intr_mask_default = 0x00000000,
regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
regk_bif_dma_slave = 0x00000002,
regk_bif_dma_sreq = 0x00000006,
regk_bif_dma_sreq_inv = 0x00000007,
regk_bif_dma_tc = 0x00000004,
regk_bif_dma_tc_inv = 0x00000005,
regk_bif_dma_yes = 0x00000001
};
#endif /* __bif_dma_defs_h */

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#ifndef __bif_slave_defs_h
#define __bif_slave_defs_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_slave_regs.r
* id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
* last modfied: Mon Apr 11 16:06:34 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
* id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope bif_slave */
/* Register rw_slave_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int slave_id : 3;
unsigned int use_slave_id : 1;
unsigned int boot_rdy : 1;
unsigned int loopback : 1;
unsigned int dis : 1;
unsigned int dummy1 : 25;
} reg_bif_slave_rw_slave_cfg;
#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
/* Register r_slave_mode, scope bif_slave, type r */
typedef struct {
unsigned int ch0_mode : 1;
unsigned int ch1_mode : 1;
unsigned int ch2_mode : 1;
unsigned int ch3_mode : 1;
unsigned int dummy1 : 28;
} reg_bif_slave_r_slave_mode;
#define REG_RD_ADDR_bif_slave_r_slave_mode 4
/* Register rw_ch0_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch0_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
/* Register rw_ch1_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch1_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
/* Register rw_ch2_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch2_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
/* Register rw_ch3_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch3_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
/* Register rw_arb_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int brin_mode : 1;
unsigned int brout_mode : 3;
unsigned int bg_mode : 3;
unsigned int release : 2;
unsigned int acquire : 1;
unsigned int settle_time : 2;
unsigned int dram_ctrl : 1;
unsigned int dummy1 : 19;
} reg_bif_slave_rw_arb_cfg;
#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
/* Register r_arb_stat, scope bif_slave, type r */
typedef struct {
unsigned int init_mode : 1;
unsigned int mode : 1;
unsigned int brin : 1;
unsigned int brout : 1;
unsigned int bg : 1;
unsigned int dummy1 : 27;
} reg_bif_slave_r_arb_stat;
#define REG_RD_ADDR_bif_slave_r_arb_stat 36
/* Register rw_intr_mask, scope bif_slave, type rw */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_rw_intr_mask;
#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
/* Register rw_ack_intr, scope bif_slave, type rw */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_rw_ack_intr;
#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
/* Register r_intr, scope bif_slave, type r */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_r_intr;
#define REG_RD_ADDR_bif_slave_r_intr 72
/* Register r_masked_intr, scope bif_slave, type r */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_r_masked_intr;
#define REG_RD_ADDR_bif_slave_r_masked_intr 76
/* Constants */
enum {
regk_bif_slave_active_hi = 0x00000003,
regk_bif_slave_active_lo = 0x00000002,
regk_bif_slave_addr = 0x00000000,
regk_bif_slave_always = 0x00000001,
regk_bif_slave_at_idle = 0x00000002,
regk_bif_slave_burst_end = 0x00000003,
regk_bif_slave_dma = 0x00000001,
regk_bif_slave_hi = 0x00000003,
regk_bif_slave_inv = 0x00000001,
regk_bif_slave_lo = 0x00000002,
regk_bif_slave_local = 0x00000001,
regk_bif_slave_master = 0x00000000,
regk_bif_slave_mode_reg = 0x00000001,
regk_bif_slave_no = 0x00000000,
regk_bif_slave_norm = 0x00000000,
regk_bif_slave_on_access = 0x00000000,
regk_bif_slave_rw_arb_cfg_default = 0x00000000,
regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
regk_bif_slave_rw_intr_mask_default = 0x00000000,
regk_bif_slave_rw_slave_cfg_default = 0x00000000,
regk_bif_slave_shared = 0x00000000,
regk_bif_slave_slave = 0x00000001,
regk_bif_slave_t0ns = 0x00000003,
regk_bif_slave_t10ns = 0x00000002,
regk_bif_slave_t20ns = 0x00000003,
regk_bif_slave_t30ns = 0x00000002,
regk_bif_slave_t40ns = 0x00000001,
regk_bif_slave_t50ns = 0x00000000,
regk_bif_slave_yes = 0x00000001,
regk_bif_slave_z = 0x00000004
};
#endif /* __bif_slave_defs_h */

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#ifndef __config_defs_h
#define __config_defs_h
/*
* This file is autogenerated from
* file: ../../rtl/config_regs.r
* id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
* last modfied: Thu Mar 4 12:34:39 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
* id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope config */
/* Register r_bootsel, scope config, type r */
typedef struct {
unsigned int boot_mode : 3;
unsigned int full_duplex : 1;
unsigned int user : 1;
unsigned int pll : 1;
unsigned int flash_bw : 1;
unsigned int dummy1 : 25;
} reg_config_r_bootsel;
#define REG_RD_ADDR_config_r_bootsel 0
/* Register rw_clk_ctrl, scope config, type rw */
typedef struct {
unsigned int pll : 1;
unsigned int cpu : 1;
unsigned int iop : 1;
unsigned int dma01_eth0 : 1;
unsigned int dma23 : 1;
unsigned int dma45 : 1;
unsigned int dma67 : 1;
unsigned int dma89_strcop : 1;
unsigned int bif : 1;
unsigned int fix_io : 1;
unsigned int dummy1 : 22;
} reg_config_rw_clk_ctrl;
#define REG_RD_ADDR_config_rw_clk_ctrl 4
#define REG_WR_ADDR_config_rw_clk_ctrl 4
/* Register rw_pad_ctrl, scope config, type rw */
typedef struct {
unsigned int usb_susp : 1;
unsigned int phyrst_n : 1;
unsigned int dummy1 : 30;
} reg_config_rw_pad_ctrl;
#define REG_RD_ADDR_config_rw_pad_ctrl 8
#define REG_WR_ADDR_config_rw_pad_ctrl 8
/* Constants */
enum {
regk_config_bw16 = 0x00000000,
regk_config_bw32 = 0x00000001,
regk_config_master = 0x00000005,
regk_config_nand = 0x00000003,
regk_config_net_rx = 0x00000001,
regk_config_net_tx_rx = 0x00000002,
regk_config_no = 0x00000000,
regk_config_none = 0x00000007,
regk_config_nor = 0x00000000,
regk_config_rw_clk_ctrl_default = 0x00000002,
regk_config_rw_pad_ctrl_default = 0x00000000,
regk_config_ser = 0x00000004,
regk_config_slave = 0x00000006,
regk_config_yes = 0x00000001
};
#endif /* __config_defs_h */

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#ifndef __gio_defs_h
#define __gio_defs_h
/*
* This file is autogenerated from
* file: ../../inst/gio/rtl/gio_regs.r
* id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
* last modfied: Mon Apr 11 16:07:47 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
* id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope gio */
/* Register rw_pa_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_dout;
#define REG_RD_ADDR_gio_rw_pa_dout 0
#define REG_WR_ADDR_gio_rw_pa_dout 0
/* Register r_pa_din, scope gio, type r */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_r_pa_din;
#define REG_RD_ADDR_gio_r_pa_din 4
/* Register rw_pa_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_oe;
#define REG_RD_ADDR_gio_rw_pa_oe 8
#define REG_WR_ADDR_gio_rw_pa_oe 8
/* Register rw_intr_cfg, scope gio, type rw */
typedef struct {
unsigned int pa0 : 3;
unsigned int pa1 : 3;
unsigned int pa2 : 3;
unsigned int pa3 : 3;
unsigned int pa4 : 3;
unsigned int pa5 : 3;
unsigned int pa6 : 3;
unsigned int pa7 : 3;
unsigned int dummy1 : 8;
} reg_gio_rw_intr_cfg;
#define REG_RD_ADDR_gio_rw_intr_cfg 12
#define REG_WR_ADDR_gio_rw_intr_cfg 12
/* Register rw_intr_mask, scope gio, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_rw_intr_mask;
#define REG_RD_ADDR_gio_rw_intr_mask 16
#define REG_WR_ADDR_gio_rw_intr_mask 16
/* Register rw_ack_intr, scope gio, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_rw_ack_intr;
#define REG_RD_ADDR_gio_rw_ack_intr 20
#define REG_WR_ADDR_gio_rw_ack_intr 20
/* Register r_intr, scope gio, type r */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_r_intr;
#define REG_RD_ADDR_gio_r_intr 24
/* Register r_masked_intr, scope gio, type r */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_r_masked_intr;
#define REG_RD_ADDR_gio_r_masked_intr 28
/* Register rw_pb_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pb_dout;
#define REG_RD_ADDR_gio_rw_pb_dout 32
#define REG_WR_ADDR_gio_rw_pb_dout 32
/* Register r_pb_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pb_din;
#define REG_RD_ADDR_gio_r_pb_din 36
/* Register rw_pb_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pb_oe;
#define REG_RD_ADDR_gio_rw_pb_oe 40
#define REG_WR_ADDR_gio_rw_pb_oe 40
/* Register rw_pc_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pc_dout;
#define REG_RD_ADDR_gio_rw_pc_dout 48
#define REG_WR_ADDR_gio_rw_pc_dout 48
/* Register r_pc_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pc_din;
#define REG_RD_ADDR_gio_r_pc_din 52
/* Register rw_pc_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pc_oe;
#define REG_RD_ADDR_gio_rw_pc_oe 56
#define REG_WR_ADDR_gio_rw_pc_oe 56
/* Register rw_pd_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pd_dout;
#define REG_RD_ADDR_gio_rw_pd_dout 64
#define REG_WR_ADDR_gio_rw_pd_dout 64
/* Register r_pd_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pd_din;
#define REG_RD_ADDR_gio_r_pd_din 68
/* Register rw_pd_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pd_oe;
#define REG_RD_ADDR_gio_rw_pd_oe 72
#define REG_WR_ADDR_gio_rw_pd_oe 72
/* Register rw_pe_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pe_dout;
#define REG_RD_ADDR_gio_rw_pe_dout 80
#define REG_WR_ADDR_gio_rw_pe_dout 80
/* Register r_pe_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pe_din;
#define REG_RD_ADDR_gio_r_pe_din 84
/* Register rw_pe_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pe_oe;
#define REG_RD_ADDR_gio_rw_pe_oe 88
#define REG_WR_ADDR_gio_rw_pe_oe 88
/* Constants */
enum {
regk_gio_anyedge = 0x00000007,
regk_gio_hi = 0x00000001,
regk_gio_lo = 0x00000002,
regk_gio_negedge = 0x00000006,
regk_gio_no = 0x00000000,
regk_gio_off = 0x00000000,
regk_gio_posedge = 0x00000005,
regk_gio_rw_intr_cfg_default = 0x00000000,
regk_gio_rw_intr_mask_default = 0x00000000,
regk_gio_rw_pa_oe_default = 0x00000000,
regk_gio_rw_pb_oe_default = 0x00000000,
regk_gio_rw_pc_oe_default = 0x00000000,
regk_gio_rw_pd_oe_default = 0x00000000,
regk_gio_rw_pe_oe_default = 0x00000000,
regk_gio_set = 0x00000003,
regk_gio_yes = 0x00000001
};
#endif /* __gio_defs_h */

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/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
version . */
#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define MEMARB_INTR_VECT 0x31
#define GEN_IO_INTR_VECT 0x32
#define GIO_INTR_VECT GEN_IO_INTR_VECT
#define IOP0_INTR_VECT 0x33
#define IOP1_INTR_VECT 0x34
#define IOP2_INTR_VECT 0x35
#define IOP3_INTR_VECT 0x36
#define DMA0_INTR_VECT 0x37
#define DMA1_INTR_VECT 0x38
#define DMA2_INTR_VECT 0x39
#define DMA3_INTR_VECT 0x3a
#define DMA4_INTR_VECT 0x3b
#define DMA5_INTR_VECT 0x3c
#define DMA6_INTR_VECT 0x3d
#define DMA7_INTR_VECT 0x3e
#define DMA8_INTR_VECT 0x3f
#define DMA9_INTR_VECT 0x40
#define ATA_INTR_VECT 0x41
#define SSER0_INTR_VECT 0x42
#define SSER1_INTR_VECT 0x43
#define SER0_INTR_VECT 0x44
#define SER1_INTR_VECT 0x45
#define SER2_INTR_VECT 0x46
#define SER3_INTR_VECT 0x47
#define P21_INTR_VECT 0x48
#define ETH0_INTR_VECT 0x49
#define ETH1_INTR_VECT 0x4a
#define TIMER_INTR_VECT 0x4b
#define TIMER0_INTR_VECT TIMER_INTR_VECT
#define BIF_ARB_INTR_VECT 0x4c
#define BIF_DMA_INTR_VECT 0x4d
#define EXT_INTR_VECT 0x4e
#define IPI_INTR_VECT 0x4f
#define NBR_INTR_VECT 0x50
#endif

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#ifndef __intr_vect_defs_h
#define __intr_vect_defs_h
/*
* This file is autogenerated from
* file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
* id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
* last modfied: Mon Apr 11 16:08:03 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
* id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope intr_vect */
#define STRIDE_intr_vect_rw_mask 0
/* Register rw_mask, scope intr_vect, type rw */
typedef struct {
unsigned int memarb : 1;
unsigned int gen_io : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int iop2 : 1;
unsigned int iop3 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int ata : 1;
unsigned int sser0 : 1;
unsigned int sser1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int p21 : 1;
unsigned int eth0 : 1;
unsigned int eth1 : 1;
unsigned int timer0 : 1;
unsigned int bif_arb : 1;
unsigned int bif_dma : 1;
unsigned int ext : 1;
unsigned int dummy1 : 2;
} reg_intr_vect_rw_mask;
#define REG_RD_ADDR_intr_vect_rw_mask 0
#define REG_WR_ADDR_intr_vect_rw_mask 0
#define STRIDE_intr_vect_r_vect 0
/* Register r_vect, scope intr_vect, type r */
typedef struct {
unsigned int memarb : 1;
unsigned int gen_io : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int iop2 : 1;
unsigned int iop3 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int ata : 1;
unsigned int sser0 : 1;
unsigned int sser1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int p21 : 1;
unsigned int eth0 : 1;
unsigned int eth1 : 1;
unsigned int timer : 1;
unsigned int bif_arb : 1;
unsigned int bif_dma : 1;
unsigned int ext : 1;
unsigned int dummy1 : 2;
} reg_intr_vect_r_vect;
#define REG_RD_ADDR_intr_vect_r_vect 4
#define STRIDE_intr_vect_r_masked_vect 0
/* Register r_masked_vect, scope intr_vect, type r */
typedef struct {
unsigned int memarb : 1;
unsigned int gen_io : 1;
unsigned int iop0 : 1;
unsigned int iop1 : 1;
unsigned int iop2 : 1;
unsigned int iop3 : 1;
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int ata : 1;
unsigned int sser0 : 1;
unsigned int sser1 : 1;
unsigned int ser0 : 1;
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int p21 : 1;
unsigned int eth0 : 1;
unsigned int eth1 : 1;
unsigned int timer : 1;
unsigned int bif_arb : 1;
unsigned int bif_dma : 1;
unsigned int ext : 1;
unsigned int dummy1 : 2;
} reg_intr_vect_r_masked_vect;
#define REG_RD_ADDR_intr_vect_r_masked_vect 8
/* Register r_nmi, scope intr_vect, type r */
typedef struct {
unsigned int ext : 1;
unsigned int watchdog : 1;
unsigned int dummy1 : 30;
} reg_intr_vect_r_nmi;
#define REG_RD_ADDR_intr_vect_r_nmi 12
/* Register r_guru, scope intr_vect, type r */
typedef struct {
unsigned int jtag : 1;
unsigned int dummy1 : 31;
} reg_intr_vect_r_guru;
#define REG_RD_ADDR_intr_vect_r_guru 16
/* Register rw_ipi, scope intr_vect, type rw */
typedef struct
{
unsigned int vector;
} reg_intr_vect_rw_ipi;
#define REG_RD_ADDR_intr_vect_rw_ipi 20
#define REG_WR_ADDR_intr_vect_rw_ipi 20
/* Constants */
enum {
regk_intr_vect_off = 0x00000000,
regk_intr_vect_on = 0x00000001,
regk_intr_vect_rw_mask_default = 0x00000000
};
#endif /* __intr_vect_defs_h */

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#ifndef __marb_bp_defs_h
#define __marb_bp_defs_h
/*
* This file is autogenerated from
* file: ../../inst/memarb/rtl/guinness/marb_top.r
* id: <not found>
* last modfied: Fri Nov 7 15:36:04 2003
*
* by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
* id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
/* C-code for register scope marb_bp */
/* Register rw_first_addr, scope marb_bp, type rw */
typedef unsigned int reg_marb_bp_rw_first_addr;
#define REG_RD_ADDR_marb_bp_rw_first_addr 0
#define REG_WR_ADDR_marb_bp_rw_first_addr 0
/* Register rw_last_addr, scope marb_bp, type rw */
typedef unsigned int reg_marb_bp_rw_last_addr;
#define REG_RD_ADDR_marb_bp_rw_last_addr 4
#define REG_WR_ADDR_marb_bp_rw_last_addr 4
/* Register rw_op, scope marb_bp, type rw */
typedef struct {
unsigned int read : 1;
unsigned int write : 1;
unsigned int read_excl : 1;
unsigned int pri_write : 1;
unsigned int us_read : 1;
unsigned int us_write : 1;
unsigned int us_read_excl : 1;
unsigned int us_pri_write : 1;
unsigned int dummy1 : 24;
} reg_marb_bp_rw_op;
#define REG_RD_ADDR_marb_bp_rw_op 8
#define REG_WR_ADDR_marb_bp_rw_op 8
/* Register rw_clients, scope marb_bp, type rw */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_bp_rw_clients;
#define REG_RD_ADDR_marb_bp_rw_clients 12
#define REG_WR_ADDR_marb_bp_rw_clients 12
/* Register rw_options, scope marb_bp, type rw */
typedef struct {
unsigned int wrap : 1;
unsigned int dummy1 : 31;
} reg_marb_bp_rw_options;
#define REG_RD_ADDR_marb_bp_rw_options 16
#define REG_WR_ADDR_marb_bp_rw_options 16
/* Register r_break_addr, scope marb_bp, type r */
typedef unsigned int reg_marb_bp_r_break_addr;
#define REG_RD_ADDR_marb_bp_r_break_addr 20
/* Register r_break_op, scope marb_bp, type r */
typedef struct {
unsigned int read : 1;
unsigned int write : 1;
unsigned int read_excl : 1;
unsigned int pri_write : 1;
unsigned int us_read : 1;
unsigned int us_write : 1;
unsigned int us_read_excl : 1;
unsigned int us_pri_write : 1;
unsigned int dummy1 : 24;
} reg_marb_bp_r_break_op;
#define REG_RD_ADDR_marb_bp_r_break_op 24
/* Register r_break_clients, scope marb_bp, type r */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_bp_r_break_clients;
#define REG_RD_ADDR_marb_bp_r_break_clients 28
/* Register r_break_first_client, scope marb_bp, type r */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_bp_r_break_first_client;
#define REG_RD_ADDR_marb_bp_r_break_first_client 32
/* Register r_break_size, scope marb_bp, type r */
typedef unsigned int reg_marb_bp_r_break_size;
#define REG_RD_ADDR_marb_bp_r_break_size 36
/* Register rw_ack, scope marb_bp, type rw */
typedef unsigned int reg_marb_bp_rw_ack;
#define REG_RD_ADDR_marb_bp_rw_ack 40
#define REG_WR_ADDR_marb_bp_rw_ack 40
/* Constants */
enum {
regk_marb_bp_no = 0x00000000,
regk_marb_bp_rw_op_default = 0x00000000,
regk_marb_bp_rw_options_default = 0x00000000,
regk_marb_bp_yes = 0x00000001
};
#endif /* __marb_bp_defs_h */

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#ifndef __marb_defs_h
#define __marb_defs_h
/*
* This file is autogenerated from
* file: ../../inst/memarb/rtl/guinness/marb_top.r
* id: <not found>
* last modfied: Mon Apr 11 16:12:16 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
* id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope marb */
#define STRIDE_marb_rw_int_slots 4
/* Register rw_int_slots, scope marb, type rw */
typedef struct {
unsigned int owner : 4;
unsigned int dummy1 : 28;
} reg_marb_rw_int_slots;
#define REG_RD_ADDR_marb_rw_int_slots 0
#define REG_WR_ADDR_marb_rw_int_slots 0
#define STRIDE_marb_rw_ext_slots 4
/* Register rw_ext_slots, scope marb, type rw */
typedef struct {
unsigned int owner : 4;
unsigned int dummy1 : 28;
} reg_marb_rw_ext_slots;
#define REG_RD_ADDR_marb_rw_ext_slots 256
#define REG_WR_ADDR_marb_rw_ext_slots 256
#define STRIDE_marb_rw_regs_slots 4
/* Register rw_regs_slots, scope marb, type rw */
typedef struct {
unsigned int owner : 4;
unsigned int dummy1 : 28;
} reg_marb_rw_regs_slots;
#define REG_RD_ADDR_marb_rw_regs_slots 512
#define REG_WR_ADDR_marb_rw_regs_slots 512
/* Register rw_intr_mask, scope marb, type rw */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_rw_intr_mask;
#define REG_RD_ADDR_marb_rw_intr_mask 528
#define REG_WR_ADDR_marb_rw_intr_mask 528
/* Register rw_ack_intr, scope marb, type rw */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_rw_ack_intr;
#define REG_RD_ADDR_marb_rw_ack_intr 532
#define REG_WR_ADDR_marb_rw_ack_intr 532
/* Register r_intr, scope marb, type r */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_r_intr;
#define REG_RD_ADDR_marb_r_intr 536
/* Register r_masked_intr, scope marb, type r */
typedef struct {
unsigned int bp0 : 1;
unsigned int bp1 : 1;
unsigned int bp2 : 1;
unsigned int bp3 : 1;
unsigned int dummy1 : 28;
} reg_marb_r_masked_intr;
#define REG_RD_ADDR_marb_r_masked_intr 540
/* Register rw_stop_mask, scope marb, type rw */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_rw_stop_mask;
#define REG_RD_ADDR_marb_rw_stop_mask 544
#define REG_WR_ADDR_marb_rw_stop_mask 544
/* Register r_stopped, scope marb, type r */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_r_stopped;
#define REG_RD_ADDR_marb_r_stopped 548
/* Register rw_no_snoop, scope marb, type rw */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_rw_no_snoop;
#define REG_RD_ADDR_marb_rw_no_snoop 832
#define REG_WR_ADDR_marb_rw_no_snoop 832
/* Register rw_no_snoop_rq, scope marb, type rw */
typedef struct {
unsigned int dummy1 : 10;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int dummy2 : 20;
} reg_marb_rw_no_snoop_rq;
#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
/* Constants */
enum {
regk_marb_cpud = 0x0000000b,
regk_marb_cpui = 0x0000000a,
regk_marb_dma0 = 0x00000000,
regk_marb_dma1 = 0x00000001,
regk_marb_dma2 = 0x00000002,
regk_marb_dma3 = 0x00000003,
regk_marb_dma4 = 0x00000004,
regk_marb_dma5 = 0x00000005,
regk_marb_dma6 = 0x00000006,
regk_marb_dma7 = 0x00000007,
regk_marb_dma8 = 0x00000008,
regk_marb_dma9 = 0x00000009,
regk_marb_iop = 0x0000000c,
regk_marb_no = 0x00000000,
regk_marb_r_stopped_default = 0x00000000,
regk_marb_rw_ext_slots_default = 0x00000000,
regk_marb_rw_ext_slots_size = 0x00000040,
regk_marb_rw_int_slots_default = 0x00000000,
regk_marb_rw_int_slots_size = 0x00000040,
regk_marb_rw_intr_mask_default = 0x00000000,
regk_marb_rw_no_snoop_default = 0x00000000,
regk_marb_rw_no_snoop_rq_default = 0x00000000,
regk_marb_rw_regs_slots_default = 0x00000000,
regk_marb_rw_regs_slots_size = 0x00000004,
regk_marb_rw_stop_mask_default = 0x00000000,
regk_marb_slave = 0x0000000d,
regk_marb_yes = 0x00000001
};
#endif /* __marb_defs_h */
#ifndef __marb_bp_defs_h
#define __marb_bp_defs_h
/*
* This file is autogenerated from
* file: ../../inst/memarb/rtl/guinness/marb_top.r
* id: <not found>
* last modfied: Mon Apr 11 16:12:16 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
* id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope marb_bp */
/* Register rw_first_addr, scope marb_bp, type rw */
typedef unsigned int reg_marb_bp_rw_first_addr;
#define REG_RD_ADDR_marb_bp_rw_first_addr 0
#define REG_WR_ADDR_marb_bp_rw_first_addr 0
/* Register rw_last_addr, scope marb_bp, type rw */
typedef unsigned int reg_marb_bp_rw_last_addr;
#define REG_RD_ADDR_marb_bp_rw_last_addr 4
#define REG_WR_ADDR_marb_bp_rw_last_addr 4
/* Register rw_op, scope marb_bp, type rw */
typedef struct {
unsigned int rd : 1;
unsigned int wr : 1;
unsigned int rd_excl : 1;
unsigned int pri_wr : 1;
unsigned int us_rd : 1;
unsigned int us_wr : 1;
unsigned int us_rd_excl : 1;
unsigned int us_pri_wr : 1;
unsigned int dummy1 : 24;
} reg_marb_bp_rw_op;
#define REG_RD_ADDR_marb_bp_rw_op 8
#define REG_WR_ADDR_marb_bp_rw_op 8
/* Register rw_clients, scope marb_bp, type rw */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_bp_rw_clients;
#define REG_RD_ADDR_marb_bp_rw_clients 12
#define REG_WR_ADDR_marb_bp_rw_clients 12
/* Register rw_options, scope marb_bp, type rw */
typedef struct {
unsigned int wrap : 1;
unsigned int dummy1 : 31;
} reg_marb_bp_rw_options;
#define REG_RD_ADDR_marb_bp_rw_options 16
#define REG_WR_ADDR_marb_bp_rw_options 16
/* Register r_brk_addr, scope marb_bp, type r */
typedef unsigned int reg_marb_bp_r_brk_addr;
#define REG_RD_ADDR_marb_bp_r_brk_addr 20
/* Register r_brk_op, scope marb_bp, type r */
typedef struct {
unsigned int rd : 1;
unsigned int wr : 1;
unsigned int rd_excl : 1;
unsigned int pri_wr : 1;
unsigned int us_rd : 1;
unsigned int us_wr : 1;
unsigned int us_rd_excl : 1;
unsigned int us_pri_wr : 1;
unsigned int dummy1 : 24;
} reg_marb_bp_r_brk_op;
#define REG_RD_ADDR_marb_bp_r_brk_op 24
/* Register r_brk_clients, scope marb_bp, type r */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_bp_r_brk_clients;
#define REG_RD_ADDR_marb_bp_r_brk_clients 28
/* Register r_brk_first_client, scope marb_bp, type r */
typedef struct {
unsigned int dma0 : 1;
unsigned int dma1 : 1;
unsigned int dma2 : 1;
unsigned int dma3 : 1;
unsigned int dma4 : 1;
unsigned int dma5 : 1;
unsigned int dma6 : 1;
unsigned int dma7 : 1;
unsigned int dma8 : 1;
unsigned int dma9 : 1;
unsigned int cpui : 1;
unsigned int cpud : 1;
unsigned int iop : 1;
unsigned int slave : 1;
unsigned int dummy1 : 18;
} reg_marb_bp_r_brk_first_client;
#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
/* Register r_brk_size, scope marb_bp, type r */
typedef unsigned int reg_marb_bp_r_brk_size;
#define REG_RD_ADDR_marb_bp_r_brk_size 36
/* Register rw_ack, scope marb_bp, type rw */
typedef unsigned int reg_marb_bp_rw_ack;
#define REG_RD_ADDR_marb_bp_rw_ack 40
#define REG_WR_ADDR_marb_bp_rw_ack 40
/* Constants */
enum {
regk_marb_bp_no = 0x00000000,
regk_marb_bp_rw_op_default = 0x00000000,
regk_marb_bp_rw_options_default = 0x00000000,
regk_marb_bp_yes = 0x00000001
};
#endif /* __marb_bp_defs_h */

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#ifndef __pinmux_defs_h
#define __pinmux_defs_h
/*
* This file is autogenerated from
* file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
* last modfied: Mon Apr 11 16:09:11 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope pinmux */
/* Register rw_pa, scope pinmux, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int csp2_n : 1;
unsigned int csp3_n : 1;
unsigned int csp5_n : 1;
unsigned int csp6_n : 1;
unsigned int hsh4 : 1;
unsigned int hsh5 : 1;
unsigned int hsh6 : 1;
unsigned int hsh7 : 1;
unsigned int dummy1 : 16;
} reg_pinmux_rw_pa;
#define REG_RD_ADDR_pinmux_rw_pa 0
#define REG_WR_ADDR_pinmux_rw_pa 0
/* Register rw_hwprot, scope pinmux, type rw */
typedef struct {
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int sser0 : 1;
unsigned int sser1 : 1;
unsigned int ata0 : 1;
unsigned int ata1 : 1;
unsigned int ata2 : 1;
unsigned int ata3 : 1;
unsigned int ata : 1;
unsigned int eth1 : 1;
unsigned int eth1_mgm : 1;
unsigned int timer : 1;
unsigned int p21 : 1;
unsigned int dummy1 : 18;
} reg_pinmux_rw_hwprot;
#define REG_RD_ADDR_pinmux_rw_hwprot 4
#define REG_WR_ADDR_pinmux_rw_hwprot 4
/* Register rw_pb_gio, scope pinmux, type rw */
typedef struct {
unsigned int pb0 : 1;
unsigned int pb1 : 1;
unsigned int pb2 : 1;
unsigned int pb3 : 1;
unsigned int pb4 : 1;
unsigned int pb5 : 1;
unsigned int pb6 : 1;
unsigned int pb7 : 1;
unsigned int pb8 : 1;
unsigned int pb9 : 1;
unsigned int pb10 : 1;
unsigned int pb11 : 1;
unsigned int pb12 : 1;
unsigned int pb13 : 1;
unsigned int pb14 : 1;
unsigned int pb15 : 1;
unsigned int pb16 : 1;
unsigned int pb17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pb_gio;
#define REG_RD_ADDR_pinmux_rw_pb_gio 8
#define REG_WR_ADDR_pinmux_rw_pb_gio 8
/* Register rw_pb_iop, scope pinmux, type rw */
typedef struct {
unsigned int pb0 : 1;
unsigned int pb1 : 1;
unsigned int pb2 : 1;
unsigned int pb3 : 1;
unsigned int pb4 : 1;
unsigned int pb5 : 1;
unsigned int pb6 : 1;
unsigned int pb7 : 1;
unsigned int pb8 : 1;
unsigned int pb9 : 1;
unsigned int pb10 : 1;
unsigned int pb11 : 1;
unsigned int pb12 : 1;
unsigned int pb13 : 1;
unsigned int pb14 : 1;
unsigned int pb15 : 1;
unsigned int pb16 : 1;
unsigned int pb17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pb_iop;
#define REG_RD_ADDR_pinmux_rw_pb_iop 12
#define REG_WR_ADDR_pinmux_rw_pb_iop 12
/* Register rw_pc_gio, scope pinmux, type rw */
typedef struct {
unsigned int pc0 : 1;
unsigned int pc1 : 1;
unsigned int pc2 : 1;
unsigned int pc3 : 1;
unsigned int pc4 : 1;
unsigned int pc5 : 1;
unsigned int pc6 : 1;
unsigned int pc7 : 1;
unsigned int pc8 : 1;
unsigned int pc9 : 1;
unsigned int pc10 : 1;
unsigned int pc11 : 1;
unsigned int pc12 : 1;
unsigned int pc13 : 1;
unsigned int pc14 : 1;
unsigned int pc15 : 1;
unsigned int pc16 : 1;
unsigned int pc17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pc_gio;
#define REG_RD_ADDR_pinmux_rw_pc_gio 16
#define REG_WR_ADDR_pinmux_rw_pc_gio 16
/* Register rw_pc_iop, scope pinmux, type rw */
typedef struct {
unsigned int pc0 : 1;
unsigned int pc1 : 1;
unsigned int pc2 : 1;
unsigned int pc3 : 1;
unsigned int pc4 : 1;
unsigned int pc5 : 1;
unsigned int pc6 : 1;
unsigned int pc7 : 1;
unsigned int pc8 : 1;
unsigned int pc9 : 1;
unsigned int pc10 : 1;
unsigned int pc11 : 1;
unsigned int pc12 : 1;
unsigned int pc13 : 1;
unsigned int pc14 : 1;
unsigned int pc15 : 1;
unsigned int pc16 : 1;
unsigned int pc17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pc_iop;
#define REG_RD_ADDR_pinmux_rw_pc_iop 20
#define REG_WR_ADDR_pinmux_rw_pc_iop 20
/* Register rw_pd_gio, scope pinmux, type rw */
typedef struct {
unsigned int pd0 : 1;
unsigned int pd1 : 1;
unsigned int pd2 : 1;
unsigned int pd3 : 1;
unsigned int pd4 : 1;
unsigned int pd5 : 1;
unsigned int pd6 : 1;
unsigned int pd7 : 1;
unsigned int pd8 : 1;
unsigned int pd9 : 1;
unsigned int pd10 : 1;
unsigned int pd11 : 1;
unsigned int pd12 : 1;
unsigned int pd13 : 1;
unsigned int pd14 : 1;
unsigned int pd15 : 1;
unsigned int pd16 : 1;
unsigned int pd17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pd_gio;
#define REG_RD_ADDR_pinmux_rw_pd_gio 24
#define REG_WR_ADDR_pinmux_rw_pd_gio 24
/* Register rw_pd_iop, scope pinmux, type rw */
typedef struct {
unsigned int pd0 : 1;
unsigned int pd1 : 1;
unsigned int pd2 : 1;
unsigned int pd3 : 1;
unsigned int pd4 : 1;
unsigned int pd5 : 1;
unsigned int pd6 : 1;
unsigned int pd7 : 1;
unsigned int pd8 : 1;
unsigned int pd9 : 1;
unsigned int pd10 : 1;
unsigned int pd11 : 1;
unsigned int pd12 : 1;
unsigned int pd13 : 1;
unsigned int pd14 : 1;
unsigned int pd15 : 1;
unsigned int pd16 : 1;
unsigned int pd17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pd_iop;
#define REG_RD_ADDR_pinmux_rw_pd_iop 28
#define REG_WR_ADDR_pinmux_rw_pd_iop 28
/* Register rw_pe_gio, scope pinmux, type rw */
typedef struct {
unsigned int pe0 : 1;
unsigned int pe1 : 1;
unsigned int pe2 : 1;
unsigned int pe3 : 1;
unsigned int pe4 : 1;
unsigned int pe5 : 1;
unsigned int pe6 : 1;
unsigned int pe7 : 1;
unsigned int pe8 : 1;
unsigned int pe9 : 1;
unsigned int pe10 : 1;
unsigned int pe11 : 1;
unsigned int pe12 : 1;
unsigned int pe13 : 1;
unsigned int pe14 : 1;
unsigned int pe15 : 1;
unsigned int pe16 : 1;
unsigned int pe17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pe_gio;
#define REG_RD_ADDR_pinmux_rw_pe_gio 32
#define REG_WR_ADDR_pinmux_rw_pe_gio 32
/* Register rw_pe_iop, scope pinmux, type rw */
typedef struct {
unsigned int pe0 : 1;
unsigned int pe1 : 1;
unsigned int pe2 : 1;
unsigned int pe3 : 1;
unsigned int pe4 : 1;
unsigned int pe5 : 1;
unsigned int pe6 : 1;
unsigned int pe7 : 1;
unsigned int pe8 : 1;
unsigned int pe9 : 1;
unsigned int pe10 : 1;
unsigned int pe11 : 1;
unsigned int pe12 : 1;
unsigned int pe13 : 1;
unsigned int pe14 : 1;
unsigned int pe15 : 1;
unsigned int pe16 : 1;
unsigned int pe17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pe_iop;
#define REG_RD_ADDR_pinmux_rw_pe_iop 36
#define REG_WR_ADDR_pinmux_rw_pe_iop 36
/* Register rw_usb_phy, scope pinmux, type rw */
typedef struct {
unsigned int en_usb0 : 1;
unsigned int en_usb1 : 1;
unsigned int dummy1 : 30;
} reg_pinmux_rw_usb_phy;
#define REG_RD_ADDR_pinmux_rw_usb_phy 40
#define REG_WR_ADDR_pinmux_rw_usb_phy 40
/* Constants */
enum {
regk_pinmux_no = 0x00000000,
regk_pinmux_rw_hwprot_default = 0x00000000,
regk_pinmux_rw_pa_default = 0x00000000,
regk_pinmux_rw_pb_gio_default = 0x00000000,
regk_pinmux_rw_pb_iop_default = 0x00000000,
regk_pinmux_rw_pc_gio_default = 0x00000000,
regk_pinmux_rw_pc_iop_default = 0x00000000,
regk_pinmux_rw_pd_gio_default = 0x00000000,
regk_pinmux_rw_pd_iop_default = 0x00000000,
regk_pinmux_rw_pe_gio_default = 0x00000000,
regk_pinmux_rw_pe_iop_default = 0x00000000,
regk_pinmux_rw_usb_phy_default = 0x00000000,
regk_pinmux_yes = 0x00000001
};
#endif /* __pinmux_defs_h */

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include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h Normal file
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#ifndef __reg_map_h
#define __reg_map_h
/*
* This file is autogenerated from
* file: ../../mod/fakereg.rmap
* id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
* last modified: Wed Feb 11 20:53:25 2004
* file: ../../rtl/global.rmap
* id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
* last modified: Mon Aug 18 17:08:23 2003
* file: ../../mod/modreg.rmap
* id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
* last modified: Fri Feb 20 16:40:04 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
* id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
typedef enum {
regi_ata = 0xb0032000,
regi_bif_core = 0xb0014000,
regi_bif_dma = 0xb0016000,
regi_bif_slave = 0xb0018000,
regi_config = 0xb003c000,
regi_dma0 = 0xb0000000,
regi_dma1 = 0xb0002000,
regi_dma2 = 0xb0004000,
regi_dma3 = 0xb0006000,
regi_dma4 = 0xb0008000,
regi_dma5 = 0xb000a000,
regi_dma6 = 0xb000c000,
regi_dma7 = 0xb000e000,
regi_dma8 = 0xb0010000,
regi_dma9 = 0xb0012000,
regi_eth0 = 0xb0034000,
regi_eth1 = 0xb0036000,
regi_gio = 0xb001a000,
regi_iop = 0xb0020000,
regi_iop_version = 0xb0020000,
regi_iop_fifo_in0_extra = 0xb0020040,
regi_iop_fifo_in1_extra = 0xb0020080,
regi_iop_fifo_out0_extra = 0xb00200c0,
regi_iop_fifo_out1_extra = 0xb0020100,
regi_iop_trigger_grp0 = 0xb0020140,
regi_iop_trigger_grp1 = 0xb0020180,
regi_iop_trigger_grp2 = 0xb00201c0,
regi_iop_trigger_grp3 = 0xb0020200,
regi_iop_trigger_grp4 = 0xb0020240,
regi_iop_trigger_grp5 = 0xb0020280,
regi_iop_trigger_grp6 = 0xb00202c0,
regi_iop_trigger_grp7 = 0xb0020300,
regi_iop_crc_par0 = 0xb0020380,
regi_iop_crc_par1 = 0xb0020400,
regi_iop_dmc_in0 = 0xb0020480,
regi_iop_dmc_in1 = 0xb0020500,
regi_iop_dmc_out0 = 0xb0020580,
regi_iop_dmc_out1 = 0xb0020600,
regi_iop_fifo_in0 = 0xb0020680,
regi_iop_fifo_in1 = 0xb0020700,
regi_iop_fifo_out0 = 0xb0020780,
regi_iop_fifo_out1 = 0xb0020800,
regi_iop_scrc_in0 = 0xb0020880,
regi_iop_scrc_in1 = 0xb0020900,
regi_iop_scrc_out0 = 0xb0020980,
regi_iop_scrc_out1 = 0xb0020a00,
regi_iop_timer_grp0 = 0xb0020a80,
regi_iop_timer_grp1 = 0xb0020b00,
regi_iop_timer_grp2 = 0xb0020b80,
regi_iop_timer_grp3 = 0xb0020c00,
regi_iop_sap_in = 0xb0020d00,
regi_iop_sap_out = 0xb0020e00,
regi_iop_spu0 = 0xb0020f00,
regi_iop_spu1 = 0xb0021000,
regi_iop_sw_cfg = 0xb0021100,
regi_iop_sw_cpu = 0xb0021200,
regi_iop_sw_mpu = 0xb0021300,
regi_iop_sw_spu0 = 0xb0021400,
regi_iop_sw_spu1 = 0xb0021500,
regi_iop_mpu = 0xb0021600,
regi_irq = 0xb001c000,
regi_irq2 = 0xb005c000,
regi_marb = 0xb003e000,
regi_marb_bp0 = 0xb003e240,
regi_marb_bp1 = 0xb003e280,
regi_marb_bp2 = 0xb003e2c0,
regi_marb_bp3 = 0xb003e300,
regi_pinmux = 0xb0038000,
regi_ser0 = 0xb0026000,
regi_ser1 = 0xb0028000,
regi_ser2 = 0xb002a000,
regi_ser3 = 0xb002c000,
regi_sser0 = 0xb0022000,
regi_sser1 = 0xb0024000,
regi_strcop = 0xb0030000,
regi_strmux = 0xb003a000,
regi_timer = 0xb001e000,
regi_timer0 = 0xb001e000,
regi_timer2 = 0xb005e000,
regi_trace = 0xb0040000,
} reg_scope_instances;
#endif /* __reg_map_h */

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#ifndef __strmux_defs_h
#define __strmux_defs_h
/*
* This file is autogenerated from
* file: ../../inst/strmux/rtl/guinness/strmux_regs.r
* id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
* last modfied: Mon Apr 11 16:09:43 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
* id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope strmux */
/* Register rw_cfg, scope strmux, type rw */
typedef struct {
unsigned int dma0 : 3;
unsigned int dma1 : 3;
unsigned int dma2 : 3;
unsigned int dma3 : 3;
unsigned int dma4 : 3;
unsigned int dma5 : 3;
unsigned int dma6 : 3;
unsigned int dma7 : 3;
unsigned int dma8 : 3;
unsigned int dma9 : 3;
unsigned int dummy1 : 2;
} reg_strmux_rw_cfg;
#define REG_RD_ADDR_strmux_rw_cfg 0
#define REG_WR_ADDR_strmux_rw_cfg 0
/* Constants */
enum {
regk_strmux_ata = 0x00000003,
regk_strmux_eth0 = 0x00000001,
regk_strmux_eth1 = 0x00000004,
regk_strmux_ext0 = 0x00000001,
regk_strmux_ext1 = 0x00000001,
regk_strmux_ext2 = 0x00000001,
regk_strmux_ext3 = 0x00000001,
regk_strmux_iop0 = 0x00000002,
regk_strmux_iop1 = 0x00000001,
regk_strmux_off = 0x00000000,
regk_strmux_p21 = 0x00000004,
regk_strmux_rw_cfg_default = 0x00000000,
regk_strmux_ser0 = 0x00000002,
regk_strmux_ser1 = 0x00000002,
regk_strmux_ser2 = 0x00000004,
regk_strmux_ser3 = 0x00000003,
regk_strmux_sser0 = 0x00000003,
regk_strmux_sser1 = 0x00000003,
regk_strmux_strcop = 0x00000002
};
#endif /* __strmux_defs_h */

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#ifndef __timer_defs_h
#define __timer_defs_h
/*
* This file is autogenerated from
* file: ../../inst/timer/rtl/timer_regs.r
* id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
* last modfied: Mon Apr 11 16:09:53 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
* id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope timer */
/* Register rw_tmr0_div, scope timer, type rw */
typedef unsigned int reg_timer_rw_tmr0_div;
#define REG_RD_ADDR_timer_rw_tmr0_div 0
#define REG_WR_ADDR_timer_rw_tmr0_div 0
/* Register r_tmr0_data, scope timer, type r */
typedef unsigned int reg_timer_r_tmr0_data;
#define REG_RD_ADDR_timer_r_tmr0_data 4
/* Register rw_tmr0_ctrl, scope timer, type rw */
typedef struct {
unsigned int op : 2;
unsigned int freq : 3;
unsigned int dummy1 : 27;
} reg_timer_rw_tmr0_ctrl;
#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
/* Register rw_tmr1_div, scope timer, type rw */
typedef unsigned int reg_timer_rw_tmr1_div;
#define REG_RD_ADDR_timer_rw_tmr1_div 16
#define REG_WR_ADDR_timer_rw_tmr1_div 16
/* Register r_tmr1_data, scope timer, type r */
typedef unsigned int reg_timer_r_tmr1_data;
#define REG_RD_ADDR_timer_r_tmr1_data 20
/* Register rw_tmr1_ctrl, scope timer, type rw */
typedef struct {
unsigned int op : 2;
unsigned int freq : 3;
unsigned int dummy1 : 27;
} reg_timer_rw_tmr1_ctrl;
#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
/* Register rs_cnt_data, scope timer, type rs */
typedef struct {
unsigned int tmr : 24;
unsigned int cnt : 8;
} reg_timer_rs_cnt_data;
#define REG_RD_ADDR_timer_rs_cnt_data 32
/* Register r_cnt_data, scope timer, type r */
typedef struct {
unsigned int tmr : 24;
unsigned int cnt : 8;
} reg_timer_r_cnt_data;
#define REG_RD_ADDR_timer_r_cnt_data 36
/* Register rw_cnt_cfg, scope timer, type rw */
typedef struct {
unsigned int clk : 2;
unsigned int dummy1 : 30;
} reg_timer_rw_cnt_cfg;
#define REG_RD_ADDR_timer_rw_cnt_cfg 40
#define REG_WR_ADDR_timer_rw_cnt_cfg 40
/* Register rw_trig, scope timer, type rw */
typedef unsigned int reg_timer_rw_trig;
#define REG_RD_ADDR_timer_rw_trig 48
#define REG_WR_ADDR_timer_rw_trig 48
/* Register rw_trig_cfg, scope timer, type rw */
typedef struct {
unsigned int tmr : 2;
unsigned int dummy1 : 30;
} reg_timer_rw_trig_cfg;
#define REG_RD_ADDR_timer_rw_trig_cfg 52
#define REG_WR_ADDR_timer_rw_trig_cfg 52
/* Register r_time, scope timer, type r */
typedef unsigned int reg_timer_r_time;
#define REG_RD_ADDR_timer_r_time 56
/* Register rw_out, scope timer, type rw */
typedef struct {
unsigned int tmr : 2;
unsigned int dummy1 : 30;
} reg_timer_rw_out;
#define REG_RD_ADDR_timer_rw_out 60
#define REG_WR_ADDR_timer_rw_out 60
/* Register rw_wd_ctrl, scope timer, type rw */
typedef struct {
unsigned int cnt : 8;
unsigned int cmd : 1;
unsigned int key : 7;
unsigned int dummy1 : 16;
} reg_timer_rw_wd_ctrl;
#define REG_RD_ADDR_timer_rw_wd_ctrl 64
#define REG_WR_ADDR_timer_rw_wd_ctrl 64
/* Register r_wd_stat, scope timer, type r */
typedef struct {
unsigned int cnt : 8;
unsigned int cmd : 1;
unsigned int dummy1 : 23;
} reg_timer_r_wd_stat;
#define REG_RD_ADDR_timer_r_wd_stat 68
/* Register rw_intr_mask, scope timer, type rw */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_rw_intr_mask;
#define REG_RD_ADDR_timer_rw_intr_mask 72
#define REG_WR_ADDR_timer_rw_intr_mask 72
/* Register rw_ack_intr, scope timer, type rw */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_rw_ack_intr;
#define REG_RD_ADDR_timer_rw_ack_intr 76
#define REG_WR_ADDR_timer_rw_ack_intr 76
/* Register r_intr, scope timer, type r */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_r_intr;
#define REG_RD_ADDR_timer_r_intr 80
/* Register r_masked_intr, scope timer, type r */
typedef struct {
unsigned int tmr0 : 1;
unsigned int tmr1 : 1;
unsigned int cnt : 1;
unsigned int trig : 1;
unsigned int dummy1 : 28;
} reg_timer_r_masked_intr;
#define REG_RD_ADDR_timer_r_masked_intr 84
/* Register rw_test, scope timer, type rw */
typedef struct {
unsigned int dis : 1;
unsigned int en : 1;
unsigned int dummy1 : 30;
} reg_timer_rw_test;
#define REG_RD_ADDR_timer_rw_test 88
#define REG_WR_ADDR_timer_rw_test 88
/* Constants */
enum {
regk_timer_ext = 0x00000001,
regk_timer_f100 = 0x00000007,
regk_timer_f29_493 = 0x00000004,
regk_timer_f32 = 0x00000005,
regk_timer_f32_768 = 0x00000006,
regk_timer_hold = 0x00000001,
regk_timer_ld = 0x00000000,
regk_timer_no = 0x00000000,
regk_timer_off = 0x00000000,
regk_timer_run = 0x00000002,
regk_timer_rw_cnt_cfg_default = 0x00000000,
regk_timer_rw_intr_mask_default = 0x00000000,
regk_timer_rw_out_default = 0x00000000,
regk_timer_rw_test_default = 0x00000000,
regk_timer_rw_tmr0_ctrl_default = 0x00000000,
regk_timer_rw_tmr1_ctrl_default = 0x00000000,
regk_timer_rw_trig_cfg_default = 0x00000000,
regk_timer_start = 0x00000001,
regk_timer_stop = 0x00000000,
regk_timer_time = 0x00000001,
regk_timer_tmr0 = 0x00000002,
regk_timer_tmr1 = 0x00000003,
regk_timer_yes = 0x00000001
};
#endif /* __timer_defs_h */

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#ifndef _ASM_CRIS_ARCH_PINMUX_H
#define _ASM_CRIS_ARCH_PINMUX_H
#define PORT_B 0
#define PORT_C 1
#define PORT_D 2
#define PORT_E 3
enum pin_mode {
pinmux_none = 0,
pinmux_fixed,
pinmux_gpio,
pinmux_iop
};
enum fixed_function {
pinmux_ser1,
pinmux_ser2,
pinmux_ser3,
pinmux_sser0,
pinmux_sser1,
pinmux_ata0,
pinmux_ata1,
pinmux_ata2,
pinmux_ata3,
pinmux_ata,
pinmux_eth1,
pinmux_timer
};
int crisv32_pinmux_init(void);
int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
int crisv32_pinmux_alloc_fixed(enum fixed_function function);
int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
void crisv32_pinmux_dump(void);
#endif

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include/asm-cris/arch-v32/mach-fs/startup.inc Normal file
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#include <hwregs/asm/reg_map_asm.h>
#include <hwregs/asm/bif_core_defs_asm.h>
#include <hwregs/asm/gio_defs_asm.h>
#include <hwregs/asm/config_defs_asm.h>
.macro GIO_INIT
move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0
move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1
move.d $r0, [$r1]
move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0
move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1
move.d $r0, [$r1]
.endm
.macro START_CLOCKS
move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
move.d [$r1], $r0
or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
REG_STATE(config, rw_clk_ctrl, bif, yes) | \
REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
move.d $r0, [$r1]
.endm
.macro SETUP_WAIT_STATES
;; Set up waitstates etc
move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
move.d $r1, [$r0]
move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
move.d $r1, [$r0]
move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
move.d $r1, [$r0]
move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
move.d $r1, [$r0]
#ifdef CONFIG_ETRAX_VCS_SIM
;; Set up minimal flash waitstates
move.d 0, $r10
move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11
move.d $r10, [$r11]
#endif
.endm