Merge branch 'pci/betty-aer-v3' into next
* pci/betty-aer-v3: PCI/AER: Reset link for devices below Root Port or Downstream Port ACPI / APEI: Force fatal AER severity when component has been reset PCI/AER: Remove "extern" from function declarations PCI/AER: Move AER severity defines to aer.h PCI/AER: Set dev->__aer_firmware_first only for matching devices PCI/AER: Factor out HEST device type matching PCI/AER: Don't parse HEST table for non-PCIe devices
This commit is contained in:
commit
5899309c90
5 changed files with 55 additions and 43 deletions
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@ -449,9 +449,19 @@ static void ghes_do_proc(struct ghes *ghes,
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pcie_err->validation_bits & CPER_PCIE_VALID_AER_INFO) {
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unsigned int devfn;
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int aer_severity;
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devfn = PCI_DEVFN(pcie_err->device_id.device,
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pcie_err->device_id.function);
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aer_severity = cper_severity_to_aer(sev);
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/*
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* If firmware reset the component to contain
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* the error, we must reinitialize it before
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* use, so treat it as a fatal AER error.
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*/
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if (gdata->flags & CPER_SEC_RESET)
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aer_severity = AER_FATAL;
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aer_recover_queue(pcie_err->device_id.segment,
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pcie_err->device_id.bus,
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devfn, aer_severity);
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@ -13,10 +13,6 @@
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#include <linux/aer.h>
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#include <linux/interrupt.h>
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#define AER_NONFATAL 0
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#define AER_FATAL 1
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#define AER_CORRECTABLE 2
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#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
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PCI_EXP_RTCTL_SENFEE| \
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PCI_EXP_RTCTL_SEFEE)
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@ -29,6 +29,22 @@ static inline int hest_match_pci(struct acpi_hest_aer_common *p,
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p->function == PCI_FUNC(pci->devfn));
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}
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static inline bool hest_match_type(struct acpi_hest_header *hest_hdr,
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struct pci_dev *dev)
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{
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u16 hest_type = hest_hdr->type;
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u8 pcie_type = pci_pcie_type(dev);
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if ((hest_type == ACPI_HEST_TYPE_AER_ROOT_PORT &&
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pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||
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(hest_type == ACPI_HEST_TYPE_AER_ENDPOINT &&
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pcie_type == PCI_EXP_TYPE_ENDPOINT) ||
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(hest_type == ACPI_HEST_TYPE_AER_BRIDGE &&
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(dev->class >> 16) == PCI_BASE_CLASS_BRIDGE))
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return true;
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return false;
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}
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struct aer_hest_parse_info {
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struct pci_dev *pci_dev;
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int firmware_first;
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@ -38,34 +54,16 @@ static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
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{
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struct aer_hest_parse_info *info = data;
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struct acpi_hest_aer_common *p;
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u8 pcie_type = 0;
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u8 bridge = 0;
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int ff = 0;
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switch (hest_hdr->type) {
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case ACPI_HEST_TYPE_AER_ROOT_PORT:
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pcie_type = PCI_EXP_TYPE_ROOT_PORT;
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break;
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case ACPI_HEST_TYPE_AER_ENDPOINT:
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pcie_type = PCI_EXP_TYPE_ENDPOINT;
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break;
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case ACPI_HEST_TYPE_AER_BRIDGE:
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if ((info->pci_dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
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bridge = 1;
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break;
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default:
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return 0;
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}
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int ff;
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p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
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ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
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if (p->flags & ACPI_HEST_GLOBAL) {
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if ((pci_is_pcie(info->pci_dev) &&
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pci_pcie_type(info->pci_dev) == pcie_type) || bridge)
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ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
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if (hest_match_type(hest_hdr, info->pci_dev))
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info->firmware_first = ff;
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} else
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if (hest_match_pci(p, info->pci_dev))
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ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
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info->firmware_first = ff;
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info->firmware_first = ff;
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return 0;
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}
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@ -89,6 +87,9 @@ static void aer_set_firmware_first(struct pci_dev *pci_dev)
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int pcie_aer_get_firmware_first(struct pci_dev *dev)
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{
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if (!pci_is_pcie(dev))
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return 0;
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if (!dev->__aer_firmware_first_valid)
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aer_set_firmware_first(dev);
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return dev->__aer_firmware_first;
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@ -400,16 +400,16 @@ void aer_do_secondary_bus_reset(struct pci_dev *dev)
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}
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/**
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* default_downstream_reset_link - default reset function for Downstream Port
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* @dev: pointer to downstream port's pci_dev data structure
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* default_reset_link - default reset function
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* @dev: pointer to pci_dev data structure
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*
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* Invoked when performing link reset at Downstream Port w/ no aer driver.
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* Invoked when performing link reset on a Downstream Port or a
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* Root Port with no aer driver.
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*/
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static pci_ers_result_t default_downstream_reset_link(struct pci_dev *dev)
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static pci_ers_result_t default_reset_link(struct pci_dev *dev)
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{
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aer_do_secondary_bus_reset(dev);
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dev_printk(KERN_DEBUG, &dev->dev,
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"Downstream Port link has been reset\n");
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dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n");
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return PCI_ERS_RESULT_RECOVERED;
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}
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@ -458,8 +458,9 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
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if (driver && driver->reset_link) {
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status = driver->reset_link(udev);
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} else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM) {
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status = default_downstream_reset_link(udev);
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} else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM ||
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pci_pcie_type(udev) == PCI_EXP_TYPE_ROOT_PORT) {
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status = default_reset_link(udev);
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} else {
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dev_printk(KERN_DEBUG, &dev->dev,
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"no link-reset support at upstream device %s\n",
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@ -7,6 +7,10 @@
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#ifndef _AER_H_
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#define _AER_H_
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#define AER_NONFATAL 0
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#define AER_FATAL 1
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#define AER_CORRECTABLE 2
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struct aer_header_log_regs {
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unsigned int dw0;
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unsigned int dw1;
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@ -31,9 +35,9 @@ struct aer_capability_regs {
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#if defined(CONFIG_PCIEAER)
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/* pci-e port driver needs this function to enable aer */
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extern int pci_enable_pcie_error_reporting(struct pci_dev *dev);
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extern int pci_disable_pcie_error_reporting(struct pci_dev *dev);
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extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
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int pci_enable_pcie_error_reporting(struct pci_dev *dev);
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int pci_disable_pcie_error_reporting(struct pci_dev *dev);
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int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
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#else
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static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)
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{
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@ -49,10 +53,10 @@ static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
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}
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#endif
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extern void cper_print_aer(const char *prefix, struct pci_dev *dev,
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int cper_severity, struct aer_capability_regs *aer);
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extern int cper_severity_to_aer(int cper_severity);
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extern void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
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int severity);
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void cper_print_aer(const char *prefix, struct pci_dev *dev, int cper_severity,
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struct aer_capability_regs *aer);
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int cper_severity_to_aer(int cper_severity);
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void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
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int severity);
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#endif //_AER_H_
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