MIPS: Netlogic: XLP2XX CPU and PIC frequency
Add code to calculate the CPU and PIC frequency for XLP2XX SoCs. Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Ganesan Ramalingam <ganesanr@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ganesan Ramalingam
Ralf Baechle
parent
5b6ff35d33
commit
57ceb4b020
5 changed files with 152 additions and 10 deletions
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@ -208,13 +208,14 @@
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#define PIC_LOCAL_SCHEDULING 1
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#define PIC_GLOBAL_SCHEDULING 0
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#define PIC_CLK_HZ 133333333
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#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
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#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
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#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
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#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
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/* We use PIC on node 0 as a timer */
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#define pic_timer_freq() nlm_get_pic_frequency(0)
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/* IRT and h/w interrupt routines */
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static inline int
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nlm_pic_read_irt(uint64_t base, int irt_index)
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@ -117,6 +117,36 @@
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#define SYS_SCRTCH2 0x4b
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#define SYS_SCRTCH3 0x4c
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/* PLL registers XLP2XX */
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#define SYS_PLL_CTRL0 0x240
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#define SYS_PLL_CTRL1 0x241
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#define SYS_PLL_CTRL2 0x242
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#define SYS_PLL_CTRL3 0x243
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#define SYS_DMC_PLL_CTRL0 0x244
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#define SYS_DMC_PLL_CTRL1 0x245
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#define SYS_DMC_PLL_CTRL2 0x246
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#define SYS_DMC_PLL_CTRL3 0x247
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#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4)
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#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4)
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#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4)
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#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4)
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#define SYS_CPU_PLL_CHG_CTRL 0x288
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#define SYS_PLL_CHG_CTRL 0x289
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#define SYS_CLK_DEV_DIS 0x28a
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#define SYS_CLK_DEV_SEL 0x28b
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#define SYS_CLK_DEV_DIV 0x28c
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#define SYS_CLK_DEV_CHG 0x28d
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#define SYS_CLK_DEV_SEL_REG 0x28e
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#define SYS_CLK_DEV_DIV_REG 0x28f
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#define SYS_CPU_PLL_LOCK 0x29f
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#define SYS_SYS_PLL_LOCK 0x2a0
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#define SYS_PLL_MEM_CMD 0x2a1
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#define SYS_CPU_PLL_MEM_REQ 0x2a2
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#define SYS_SYS_PLL_MEM_REQ 0x2a3
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#define SYS_PLL_MEM_STAT 0x2a4
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#ifndef __ASSEMBLY__
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#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
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@ -124,5 +154,6 @@
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#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
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#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
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unsigned int nlm_get_pic_frequency(int node);
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#endif
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#endif
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@ -36,6 +36,8 @@
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#define _ASM_NLM_XLR_PIC_H
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#define PIC_CLK_HZ 66666666
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#define pic_timer_freq() PIC_CLK_HZ
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/* PIC hardware interrupt numbers */
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#define PIC_IRT_WD_INDEX 0
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#define PIC_IRT_TIMER_0_INDEX 1
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@ -45,6 +45,7 @@
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#if defined(CONFIG_CPU_XLP)
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#elif defined(CONFIG_CPU_XLR)
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#include <asm/netlogic/xlr/iomap.h>
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@ -91,7 +92,7 @@ static void nlm_init_pic_timer(void)
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csrc_pic.read = nlm_get_pic_timer;
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}
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csrc_pic.rating = 1000;
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clocksource_register_hz(&csrc_pic, PIC_CLK_HZ);
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clocksource_register_hz(&csrc_pic, pic_timer_freq());
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}
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void __init plat_time_init(void)
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@ -127,18 +127,125 @@ unsigned int nlm_get_core_frequency(int node, int core)
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sysbase = nlm_get_node(node)->sysbase;
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rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
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dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
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pll_divf = ((rstval >> 10) & 0x7f) + 1;
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pll_divr = ((rstval >> 8) & 0x3) + 1;
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ext_div = ((rstval >> 30) & 0x3) + 1;
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dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
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if (cpu_is_xlpii()) {
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num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
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denom = 3;
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} else {
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dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
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pll_divf = ((rstval >> 10) & 0x7f) + 1;
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pll_divr = ((rstval >> 8) & 0x3) + 1;
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ext_div = ((rstval >> 30) & 0x3) + 1;
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dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
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num = 800000000ULL * pll_divf;
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denom = 3 * pll_divr * ext_div * dfs_div;
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num = 800000000ULL * pll_divf;
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denom = 3 * pll_divr * ext_div * dfs_div;
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}
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do_div(num, denom);
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return (unsigned int)num;
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}
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/* Calculate Frequency to the PIC from PLL.
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* freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
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* ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
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*/
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static unsigned int nlm_2xx_get_pic_frequency(int node)
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{
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u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
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u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
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u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
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sysbase = nlm_get_node(node)->sysbase;
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/* Find ref_clk_base */
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ref_clk_select =
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(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
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switch (ref_clk_select) {
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case 0:
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ref_clk = 200000000ULL;
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ref_div = 3;
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break;
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case 1:
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ref_clk = 100000000ULL;
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ref_div = 1;
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break;
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case 2:
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ref_clk = 125000000ULL;
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ref_div = 1;
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break;
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case 3:
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ref_clk = 400000000ULL;
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ref_div = 3;
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break;
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}
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/* Find the clock source PLL device for PIC */
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reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
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switch (reg_select) {
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case 0:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
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break;
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case 1:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
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break;
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case 2:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
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break;
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case 3:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
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break;
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}
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vco_post_div = (ctrl_val0 >> 5) & 0x7;
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pll_post_div = (ctrl_val0 >> 24) & 0x7;
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mdiv = ctrl_val2 & 0xff;
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fdiv = (ctrl_val2 >> 8) & 0xfff;
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/* Find PLL post divider value */
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switch (pll_post_div) {
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case 1:
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pll_post_div = 2;
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break;
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case 3:
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pll_post_div = 4;
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break;
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case 7:
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pll_post_div = 8;
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break;
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case 6:
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pll_post_div = 16;
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break;
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case 0:
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default:
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pll_post_div = 1;
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break;
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}
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fdiv = fdiv/(1 << 13);
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pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
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pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
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if (pll_out_freq_den > 0)
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do_div(pll_out_freq_num, pll_out_freq_den);
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/* PIC post divider, which happens after PLL */
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pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
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do_div(pll_out_freq_num, 1 << pic_div);
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return pll_out_freq_num;
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}
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unsigned int nlm_get_pic_frequency(int node)
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{
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if (cpu_is_xlpii())
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return nlm_2xx_get_pic_frequency(node);
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else
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return 133333333;
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}
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unsigned int nlm_get_cpu_frequency(void)
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{
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return nlm_get_core_frequency(0, 0);
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