PHY: Add driver for Pistachio USB2.0 PHY
Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley <james.hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker
Ralf Baechle
parent
90bc35c5da
commit
57991ebaf9
3 changed files with 214 additions and 0 deletions
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@ -247,6 +247,13 @@ config PHY_EXYNOS5_USBDRD
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This driver provides PHY interface for USB 3.0 DRD controller
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present on Exynos5 SoC series.
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config PHY_PISTACHIO_USB
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tristate "IMG Pistachio USB2.0 PHY driver"
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depends on MACH_PISTACHIO
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select GENERIC_PHY
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help
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Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
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config PHY_QCOM_APQ8064_SATA
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tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
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depends on ARCH_QCOM
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@ -40,3 +40,4 @@ obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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206
drivers/phy/phy-pistachio-usb.c
Normal file
206
drivers/phy/phy-pistachio-usb.c
Normal file
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@ -0,0 +1,206 @@
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/*
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* IMG Pistachio USB PHY driver
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*
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* Copyright (C) 2015 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/phy/phy-pistachio-usb.h>
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#define USB_PHY_CONTROL1 0x04
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#define USB_PHY_CONTROL1_FSEL_SHIFT 2
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#define USB_PHY_CONTROL1_FSEL_MASK 0x7
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#define USB_PHY_STRAP_CONTROL 0x10
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#define USB_PHY_STRAP_CONTROL_REFCLK_SHIFT 4
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#define USB_PHY_STRAP_CONTROL_REFCLK_MASK 0x3
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#define USB_PHY_STATUS 0x14
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#define USB_PHY_STATUS_RX_PHY_CLK BIT(9)
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#define USB_PHY_STATUS_RX_UTMI_CLK BIT(8)
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#define USB_PHY_STATUS_VBUS_FAULT BIT(7)
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struct pistachio_usb_phy {
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struct device *dev;
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struct regmap *cr_top;
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struct clk *phy_clk;
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unsigned int refclk;
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};
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static const unsigned long fsel_rate_map[] = {
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9600000,
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10000000,
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12000000,
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19200000,
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20000000,
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24000000,
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0,
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50000000,
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};
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static int pistachio_usb_phy_power_on(struct phy *phy)
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{
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struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
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unsigned long timeout, rate;
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unsigned int i;
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int ret;
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ret = clk_prepare_enable(p_phy->phy_clk);
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if (ret < 0) {
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dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
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return ret;
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}
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regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL,
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USB_PHY_STRAP_CONTROL_REFCLK_MASK <<
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USB_PHY_STRAP_CONTROL_REFCLK_SHIFT,
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p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT);
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rate = clk_get_rate(p_phy->phy_clk);
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if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) {
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dev_err(p_phy->dev, "Unsupported rate for XO crystal: %ld\n",
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rate);
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ret = -EINVAL;
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goto disable_clk;
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}
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for (i = 0; i < ARRAY_SIZE(fsel_rate_map); i++) {
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if (rate == fsel_rate_map[i])
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break;
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}
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if (i == ARRAY_SIZE(fsel_rate_map)) {
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dev_err(p_phy->dev, "Unsupported clock rate: %lu\n", rate);
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ret = -EINVAL;
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goto disable_clk;
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}
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regmap_update_bits(p_phy->cr_top, USB_PHY_CONTROL1,
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USB_PHY_CONTROL1_FSEL_MASK <<
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USB_PHY_CONTROL1_FSEL_SHIFT,
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i << USB_PHY_CONTROL1_FSEL_SHIFT);
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timeout = jiffies + msecs_to_jiffies(200);
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while (time_before(jiffies, timeout)) {
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unsigned int val;
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regmap_read(p_phy->cr_top, USB_PHY_STATUS, &val);
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if (val & USB_PHY_STATUS_VBUS_FAULT) {
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dev_err(p_phy->dev, "VBUS fault detected\n");
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ret = -EIO;
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goto disable_clk;
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}
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if ((val & USB_PHY_STATUS_RX_PHY_CLK) &&
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(val & USB_PHY_STATUS_RX_UTMI_CLK))
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return 0;
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usleep_range(1000, 1500);
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}
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dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
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ret = -ETIMEDOUT;
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disable_clk:
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clk_disable_unprepare(p_phy->phy_clk);
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return ret;
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}
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static int pistachio_usb_phy_power_off(struct phy *phy)
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{
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struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
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clk_disable_unprepare(p_phy->phy_clk);
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return 0;
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}
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static const struct phy_ops pistachio_usb_phy_ops = {
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.power_on = pistachio_usb_phy_power_on,
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.power_off = pistachio_usb_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int pistachio_usb_phy_probe(struct platform_device *pdev)
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{
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struct pistachio_usb_phy *p_phy;
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struct phy_provider *provider;
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struct phy *phy;
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int ret;
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p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
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if (!p_phy)
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return -ENOMEM;
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p_phy->dev = &pdev->dev;
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platform_set_drvdata(pdev, p_phy);
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p_phy->cr_top = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node,
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"img,cr-top");
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if (IS_ERR(p_phy->cr_top)) {
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dev_err(p_phy->dev, "Failed to get CR_TOP registers: %ld\n",
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PTR_ERR(p_phy->cr_top));
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return PTR_ERR(p_phy->cr_top);
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}
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p_phy->phy_clk = devm_clk_get(p_phy->dev, "usb_phy");
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if (IS_ERR(p_phy->phy_clk)) {
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dev_err(p_phy->dev, "Failed to get usb_phy clock: %ld\n",
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PTR_ERR(p_phy->phy_clk));
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return PTR_ERR(p_phy->phy_clk);
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}
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ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk",
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&p_phy->refclk);
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if (ret < 0) {
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dev_err(p_phy->dev, "No reference clock selector specified\n");
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return ret;
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}
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phy = devm_phy_create(p_phy->dev, NULL, &pistachio_usb_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(p_phy->dev, "Failed to create PHY: %ld\n",
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PTR_ERR(phy));
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, p_phy);
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provider = devm_of_phy_provider_register(p_phy->dev,
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of_phy_simple_xlate);
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if (IS_ERR(provider)) {
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dev_err(p_phy->dev, "Failed to register PHY provider: %ld\n",
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PTR_ERR(provider));
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return PTR_ERR(provider);
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}
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return 0;
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}
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static const struct of_device_id pistachio_usb_phy_of_match[] = {
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{ .compatible = "img,pistachio-usb-phy", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, pistachio_usb_phy_of_match);
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static struct platform_driver pistachio_usb_phy_driver = {
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.probe = pistachio_usb_phy_probe,
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.driver = {
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.name = "pistachio-usb-phy",
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.of_match_table = pistachio_usb_phy_of_match,
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},
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};
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module_platform_driver(pistachio_usb_phy_driver);
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MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
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MODULE_DESCRIPTION("IMG Pistachio USB2.0 PHY driver");
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MODULE_LICENSE("GPL v2");
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