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Blackfin: MPU: handle caches for reserved memory

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We weren't handling the user-specified cache behavior for the reserved
memory regions (via mem=/max_mem=).  The no-MPU code already takes care
of this, so add support to the MPU code as well.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Sonic Zhang 2009-12-09 07:01:50 +00:00 committed by Mike Frysinger
parent d94a1aa44e
commit 5792ab2a0a
1 changed files with 5 additions and 1 deletions
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6
arch/blackfin/kernel/cplb-mpu/cplbmgr.c
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@ -131,7 +131,9 @@ static noinline int dcplb_miss(unsigned int cpu)
} else } else
return CPLB_PROT_VIOL; return CPLB_PROT_VIOL;
} else if (addr >= _ramend) { } else if (addr >= _ramend) {
d_data |= CPLB_USER_RD | CPLB_USER_WR; d_data |= CPLB_USER_RD | CPLB_USER_WR;
if (reserved_mem_dcache_on)
d_data |= CPLB_L1_CHBL;
} else { } else {
mask = current_rwx_mask[cpu]; mask = current_rwx_mask[cpu];
if (mask) { if (mask) {
@ -231,6 +233,8 @@ static noinline int icplb_miss(unsigned int cpu)
return CPLB_PROT_VIOL; return CPLB_PROT_VIOL;
} else if (addr >= _ramend) { } else if (addr >= _ramend) {
i_data |= CPLB_USER_RD; i_data |= CPLB_USER_RD;
if (reserved_mem_icache_on)
i_data |= CPLB_L1_CHBL;
} else { } else {
/* /*
* Two cases to distinguish - a supervisor access must * Two cases to distinguish - a supervisor access must