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Blackfin arch: Fix Bug - System with EMAC driver enabled - Core not idling

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- Disable all bits in SIC_IWR unless we are going into a real (DPMC)
   power saving mode. Any Interrupt can wake the core form it's idle state.

 - Remove deep sleep mode as it is not going to be used anywhere:
   We support sleep, sleep deeper and hibernate.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich 2008-08-06 17:55:32 +08:00 committed by Bryan Wu
parent 15b0753689
commit 56f5f59052
8 changed files with 8 additions and 93 deletions
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7
arch/blackfin/mach-bf527/head.S
View file

@ -183,13 +183,6 @@ ENTRY(_start_dma_code)
[P2] = R1; [P2] = R1;
SSYNC; SSYNC;
p0.h = hi(SIC_IWR0);
p0.l = lo(SIC_IWR0);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;
RTS; RTS;
ENDPROC(_start_dma_code) ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */ #endif /* CONFIG_BFIN_KERNEL_CLOCK */

7
arch/blackfin/mach-bf533/head.S
View file

@ -177,13 +177,6 @@ ENTRY(_start_dma_code)
[P2] = R1; [P2] = R1;
SSYNC; SSYNC;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;
RTS; RTS;
ENDPROC(_start_dma_code) ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */ #endif /* CONFIG_BFIN_KERNEL_CLOCK */

7
arch/blackfin/mach-bf537/head.S
View file

@ -197,13 +197,6 @@ ENTRY(_start_dma_code)
[P2] = R1; [P2] = R1;
SSYNC; SSYNC;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;
RTS; RTS;
ENDPROC(_start_dma_code) ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */ #endif /* CONFIG_BFIN_KERNEL_CLOCK */

7
arch/blackfin/mach-bf548/head.S
View file

@ -201,13 +201,6 @@ ENTRY(_start_dma_code)
SSYNC; SSYNC;
#endif #endif
p0.h = hi(SIC_IWR0);
p0.l = lo(SIC_IWR0);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;
RTS; RTS;
ENDPROC(_start_dma_code) ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */ #endif /* CONFIG_BFIN_KERNEL_CLOCK */

56
arch/blackfin/mach-common/dpmc_modes.S
View file

@ -78,62 +78,6 @@ ENTRY(_hibernate_mode)
jump .Lforever; jump .Lforever;
ENDPROC(_hibernate_mode) ENDPROC(_hibernate_mode)
ENTRY(_deep_sleep)
[--SP] = ( R7:0, P5:0 );
[--SP] = RETS;
CLI R4;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
call _set_dram_srfs;
/* Clear all the interrupts,bits sticky */
R0 = 0xFFFF (Z);
call _set_rtc_istat
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R0 = W[P0](z);
BITSET (R0, 5);
W[P0] = R0.L;
call _test_pll_locked;
SSYNC;
IDLE;
call _unset_dram_srfs;
call _test_pll_locked;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R0 = w[p0](z);
BITCLR (R0, 3);
BITCLR (R0, 5);
BITCLR (R0, 8);
w[p0] = R0;
IDLE;
call _test_pll_locked;
STI R4;
RETS = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
ENDPROC(_deep_sleep)
ENTRY(_sleep_deeper) ENTRY(_sleep_deeper)
[--SP] = ( R7:0, P5:0 ); [--SP] = ( R7:0, P5:0 );
[--SP] = RETS; [--SP] = RETS;

8
arch/blackfin/mach-common/ints-priority.c
View file

@ -1068,13 +1068,13 @@ int __init init_arch_irq(void)
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL); bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL); bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
# ifdef CONFIG_BF54x # ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL); bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
# endif # endif
#else #else
bfin_write_SIC_IWR(IWR_ENABLE_ALL); bfin_write_SIC_IWR(IWR_DISABLE_ALL);
#endif #endif
return 0; return 0;

8
arch/blackfin/mach-common/pm.c
View file

@ -83,13 +83,13 @@ void bfin_pm_suspend_standby_enter(void)
bfin_pm_standby_restore(); bfin_pm_standby_restore();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL); bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL); bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
# ifdef CONFIG_BF54x # ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL); bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
# endif # endif
#else #else
bfin_write_SIC_IWR(IWR_ENABLE_ALL); bfin_write_SIC_IWR(IWR_DISABLE_ALL);
#endif #endif
local_irq_restore(flags); local_irq_restore(flags);

1
include/asm-blackfin/dpmc.h
View file

@ -11,7 +11,6 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void do_hibernate(int wakeup); void do_hibernate(int wakeup);