EDAC, AMD: decode bus unit MCEs
... according to Table 69, Fam10h BKDG (31116, rev. 3.28). Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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@ -228,6 +228,48 @@ static void amd_decode_ic_mce(u64 mc1_status)
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pr_warning("Corrupted IC MCE info?\n");
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pr_warning("Corrupted IC MCE info?\n");
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}
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}
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static void amd_decode_bu_mce(u64 mc2_status)
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{
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u32 ec = mc2_status & 0xffff;
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u32 xec = (mc2_status >> 16) & 0xf;
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pr_emerg(" Bus Unit Error");
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if (xec == 0x1)
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pr_cont(" in the write data buffers.\n");
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else if (xec == 0x3)
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pr_cont(" in the victim data buffers.\n");
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else if (xec == 0x2 && MEM_ERROR(ec))
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pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
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else if (xec == 0x0) {
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if (TLB_ERROR(ec))
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pr_cont(": %s error in a Page Descriptor Cache or "
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"Guest TLB.\n", TT_MSG(ec));
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else if (BUS_ERROR(ec))
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pr_cont(": %s/ECC error in data read from NB: %s.\n",
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RRRR_MSG(ec), PP_MSG(ec));
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else if (MEM_ERROR(ec)) {
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u8 rrrr = (ec >> 4) & 0xf;
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if (rrrr >= 0x7)
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pr_cont(": %s error during data copyback.\n",
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RRRR_MSG(ec));
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else if (rrrr <= 0x1)
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pr_cont(": %s parity/ECC error during data "
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"access from L2.\n", RRRR_MSG(ec));
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else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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return;
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wrong_bu_mce:
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pr_warning("Corrupted BU MCE info?\n");
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}
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void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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{
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{
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u32 ec = ERROR_CODE(regs->nbsl);
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u32 ec = ERROR_CODE(regs->nbsl);
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@ -320,6 +362,10 @@ void decode_mce(struct mce *m)
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amd_decode_ic_mce(m->status);
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amd_decode_ic_mce(m->status);
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break;
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break;
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case 2:
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amd_decode_bu_mce(m->status);
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break;
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case 4:
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case 4:
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regs.nbsl = (u32) m->status;
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regs.nbsl = (u32) m->status;
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regs.nbsh = (u32)(m->status >> 32);
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regs.nbsh = (u32)(m->status >> 32);
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