[ARM] 4133/1: Add ISB after changes to CP15 registers
According to ARM ARM, changes to the CP15 registers are only guaranteed to be visible after an Instruction Synchronization Barrier (ISB). This patch adds the ISB at the end of set_cr and set_copro_access functions and also moves them further down in the file, below the isb macro definition. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1 changed files with 40 additions and 38 deletions
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@ -140,44 +140,6 @@ static inline int cpu_is_xsc3(void)
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#define cpu_is_xscale() 1
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#define cpu_is_xscale() 1
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#endif
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#endif
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extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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}
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#ifndef CONFIG_SMP
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extern void adjust_cr(unsigned long mask, unsigned long set);
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#endif
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#define CPACC_FULL(n) (3 << (n * 2))
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#define CPACC_SVC(n) (1 << (n * 2))
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#define CPACC_DISABLE(n) (0 << (n * 2))
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static inline unsigned int get_copro_access(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
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: "=r" (val) : : "cc");
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return val;
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}
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static inline void set_copro_access(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
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: : "r" (val) : "cc");
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}
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#define UDBG_UNDEFINED (1 << 0)
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#define UDBG_UNDEFINED (1 << 0)
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#define UDBG_SYSCALL (1 << 1)
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#define UDBG_SYSCALL (1 << 1)
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#define UDBG_BADABORT (1 << 2)
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#define UDBG_BADABORT (1 << 2)
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@ -212,6 +174,46 @@ extern unsigned int user_debug;
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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#ifndef CONFIG_SMP
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extern void adjust_cr(unsigned long mask, unsigned long set);
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#endif
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#define CPACC_FULL(n) (3 << (n * 2))
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#define CPACC_SVC(n) (1 << (n * 2))
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#define CPACC_DISABLE(n) (0 << (n * 2))
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static inline unsigned int get_copro_access(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
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: "=r" (val) : : "cc");
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return val;
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}
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static inline void set_copro_access(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
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: : "r" (val) : "cc");
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isb();
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}
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/*
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/*
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* switch_mm() may do a full cache flush over the context switch,
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* switch_mm() may do a full cache flush over the context switch,
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* so enable interrupts over the context switch to avoid high
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* so enable interrupts over the context switch to avoid high
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