serial: quatech: add the other serial identifiers and preliminary control code
Jonathan Woithe posted an out of tree enabler/control module for these cards. Lift the relevant identifiers and put them in the 8250_pci driver along with code used to control custom registers on these cards. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Jonathan Woithe <jwoithe@just42.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
9931faca02
commit
55c7c0fdc5
2 changed files with 324 additions and 0 deletions
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@ -1040,6 +1040,253 @@ static int pci_asix_setup(struct serial_private *priv,
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return pci_default_setup(priv, board, port, idx);
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}
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/* Quatech devices have their own extra interface features */
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struct quatech_feature {
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u16 devid;
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bool amcc;
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};
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#define QPCR_TEST_FOR1 0x3F
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#define QPCR_TEST_GET1 0x00
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#define QPCR_TEST_FOR2 0x40
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#define QPCR_TEST_GET2 0x40
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#define QPCR_TEST_FOR3 0x80
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#define QPCR_TEST_GET3 0x40
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#define QPCR_TEST_FOR4 0xC0
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#define QPCR_TEST_GET4 0x80
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#define QOPR_CLOCK_X1 0x0000
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#define QOPR_CLOCK_X2 0x0001
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#define QOPR_CLOCK_X4 0x0002
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#define QOPR_CLOCK_X8 0x0003
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#define QOPR_CLOCK_RATE_MASK 0x0003
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static struct quatech_feature quatech_cards[] = {
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{ PCI_DEVICE_ID_QUATECH_QSC100, 1 },
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{ PCI_DEVICE_ID_QUATECH_DSC100, 1 },
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{ PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
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{ PCI_DEVICE_ID_QUATECH_DSC200, 1 },
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{ PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
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{ PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
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{ PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
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{ PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
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{ PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
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{ PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
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{ PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
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{ PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
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{ PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
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{ PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
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{ PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
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{ PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
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{ PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
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{ PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
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{ PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
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{ 0, }
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};
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static int pci_quatech_amcc(u16 devid)
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{
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struct quatech_feature *qf = &quatech_cards[0];
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while (qf->devid) {
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if (qf->devid == devid)
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return qf->amcc;
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qf++;
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}
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pr_err("quatech: unknown port type '0x%04X'.\n", devid);
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return 0;
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};
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static int pci_quatech_rqopr(struct uart_8250_port *port)
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{
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unsigned long base = port->port.iobase;
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u8 LCR, val;
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LCR = inb(base + UART_LCR);
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outb(0xBF, base + UART_LCR);
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val = inb(base + UART_SCR);
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outb(LCR, base + UART_LCR);
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return val;
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}
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static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
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{
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unsigned long base = port->port.iobase;
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u8 LCR, val;
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LCR = inb(base + UART_LCR);
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outb(0xBF, base + UART_LCR);
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val = inb(base + UART_SCR);
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outb(qopr, base + UART_SCR);
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outb(LCR, base + UART_LCR);
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}
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static int pci_quatech_rqmcr(struct uart_8250_port *port)
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{
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unsigned long base = port->port.iobase;
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u8 LCR, val, qmcr;
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LCR = inb(base + UART_LCR);
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outb(0xBF, base + UART_LCR);
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val = inb(base + UART_SCR);
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outb(val | 0x10, base + UART_SCR);
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qmcr = inb(base + UART_MCR);
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outb(val, base + UART_SCR);
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outb(LCR, base + UART_LCR);
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return qmcr;
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}
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static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
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{
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unsigned long base = port->port.iobase;
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u8 LCR, val;
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LCR = inb(base + UART_LCR);
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outb(0xBF, base + UART_LCR);
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val = inb(base + UART_SCR);
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outb(val | 0x10, base + UART_SCR);
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outb(qmcr, base + UART_MCR);
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outb(val, base + UART_SCR);
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outb(LCR, base + UART_LCR);
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}
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static int pci_quatech_has_qmcr(struct uart_8250_port *port)
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{
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unsigned long base = port->port.iobase;
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u8 LCR, val;
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LCR = inb(base + UART_LCR);
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outb(0xBF, base + UART_LCR);
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val = inb(base + UART_SCR);
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if (val & 0x20) {
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outb(0x80, UART_LCR);
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if (!(inb(UART_SCR) & 0x20)) {
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outb(LCR, base + UART_LCR);
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return 1;
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}
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}
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return 0;
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}
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static int pci_quatech_test(struct uart_8250_port *port)
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{
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u8 reg;
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u8 qopr = pci_quatech_rqopr(port);
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pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
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reg = pci_quatech_rqopr(port) & 0xC0;
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if (reg != QPCR_TEST_GET1)
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return -EINVAL;
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pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
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reg = pci_quatech_rqopr(port) & 0xC0;
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if (reg != QPCR_TEST_GET2)
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return -EINVAL;
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pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
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reg = pci_quatech_rqopr(port) & 0xC0;
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if (reg != QPCR_TEST_GET3)
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return -EINVAL;
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pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
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reg = pci_quatech_rqopr(port) & 0xC0;
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if (reg != QPCR_TEST_GET4)
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return -EINVAL;
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pci_quatech_wqopr(port, qopr);
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return 0;
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}
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static int pci_quatech_clock(struct uart_8250_port *port)
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{
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u8 qopr, reg, set;
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unsigned long clock;
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if (pci_quatech_test(port) < 0)
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return 1843200;
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qopr = pci_quatech_rqopr(port);
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pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
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reg = pci_quatech_rqopr(port);
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if (reg & QOPR_CLOCK_X8) {
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clock = 1843200;
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goto out;
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}
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pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
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reg = pci_quatech_rqopr(port);
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if (!(reg & QOPR_CLOCK_X8)) {
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clock = 1843200;
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goto out;
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}
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reg &= QOPR_CLOCK_X8;
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if (reg == QOPR_CLOCK_X2) {
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clock = 3685400;
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set = QOPR_CLOCK_X2;
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} else if (reg == QOPR_CLOCK_X4) {
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clock = 7372800;
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set = QOPR_CLOCK_X4;
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} else if (reg == QOPR_CLOCK_X8) {
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clock = 14745600;
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set = QOPR_CLOCK_X8;
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} else {
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clock = 1843200;
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set = QOPR_CLOCK_X1;
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}
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qopr &= ~QOPR_CLOCK_RATE_MASK;
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qopr |= set;
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out:
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pci_quatech_wqopr(port, qopr);
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return clock;
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}
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static int pci_quatech_rs422(struct uart_8250_port *port)
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{
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u8 qmcr;
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int rs422 = 0;
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if (!pci_quatech_has_qmcr(port))
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return 0;
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qmcr = pci_quatech_rqmcr(port);
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pci_quatech_wqmcr(port, 0xFF);
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if (pci_quatech_rqmcr(port))
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rs422 = 1;
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pci_quatech_wqmcr(port, qmcr);
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return rs422;
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}
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static int pci_quatech_init(struct pci_dev *dev)
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{
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if (pci_quatech_amcc(dev->device)) {
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unsigned long base = pci_resource_start(dev, 0);
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if (base) {
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u32 tmp;
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outl(inl(base + 0x38), base + 0x38);
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tmp = inl(base + 0x3c);
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outl(tmp | 0x01000000, base + 0x3c);
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outl(tmp, base + 0x3c);
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}
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}
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return 0;
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}
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static int pci_quatech_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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{
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/* Needed by pci_quatech calls below */
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port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
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/* Set up the clocking */
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port->port.uartclk = pci_quatech_clock(port);
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/* For now just warn about RS422 */
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if (pci_quatech_rs422(port))
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pr_warn("quatech: software control of RS422 features not currently supported.\n");
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return pci_default_setup(priv, board, port, idx);
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}
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static void __devexit pci_quatech_exit(struct pci_dev *dev)
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{
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}
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static int pci_default_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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@ -1528,6 +1775,16 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.setup = pci_ni8430_setup,
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.exit = pci_ni8430_exit,
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},
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/* Quatech */
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{
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.vendor = PCI_VENDOR_ID_QUATECH,
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.device = PCI_ANY_ID,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_quatech_init,
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.setup = pci_quatech_setup,
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.exit = __devexit_p(pci_quatech_exit),
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},
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/*
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* Panacom
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*/
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@ -3475,18 +3732,70 @@ static struct pci_device_id serial_pci_tbl[] = {
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
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0x10b5, 0x106a, 0, 0,
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pbn_plx_romulus },
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/*
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* Quatech cards. These actually have configurable clocks but for
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* now we just use the default.
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*
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* 100 series are RS232, 200 series RS422,
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*/
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_4_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_4_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_8_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_8_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_4_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_4_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b1_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_4_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_1_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_4_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_2_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b2_1_115200 },
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{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b0_8_115200 },
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{ PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
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PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
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0, 0,
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@ -1868,8 +1868,23 @@
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#define PCI_VENDOR_ID_QUATECH 0x135C
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#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010
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#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020
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#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030
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#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040
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#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050
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#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060
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#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120
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#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130
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#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140
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#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150
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#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170
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#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180
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#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181
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#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190
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#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0
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#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0
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#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1
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#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0
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#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0
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#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
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#define PCI_VENDOR_ID_SEALEVEL 0x135e
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