sh: Add support for SH7786 CPU subtype.
This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Kuninori Morimoto
Paul Mundt
parent
93fde77454
commit
55ba99eb21
14 changed files with 1734 additions and 6 deletions
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@ -356,6 +356,13 @@ config CPU_SUBTYPE_SH7785
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_NUMA
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config CPU_SUBTYPE_SH7786
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bool "Support SH7786 processor"
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select CPU_SH4A
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select CPU_SHX2
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_NUMA
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config CPU_SUBTYPE_SHX3
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bool "Support SH-X3 processor"
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select CPU_SH4A
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@ -31,7 +31,7 @@ enum cpu_type {
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CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
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/* SH-4A types */
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CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
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CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
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CPU_SH7723, CPU_SHX3,
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/* SH4AL-DSP types */
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@ -29,6 +29,10 @@
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#define FRQCR0 0xffc80000
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#define FRQCR1 0xffc80004
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#define FRQMR1 0xffc80014
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#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
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#define FRQCR0 0xffc40000
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#define FRQCR1 0xffc40004
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#define FRQMR1 0xffc40014
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#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
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#define FRQCR 0xffc00014
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#else
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192
arch/sh/include/cpu-sh4/cpu/sh7786.h
Normal file
192
arch/sh/include/cpu-sh4/cpu/sh7786.h
Normal file
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@ -0,0 +1,192 @@
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/*
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* SH7786 Pinmux
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*
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* Copyright (C) 2008, 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on sh7785.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __CPU_SH7786_H__
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#define __CPU_SH7786_H__
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enum {
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/* PA */
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GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
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GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
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/* PB */
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GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
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GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
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/* PC */
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GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
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GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
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/* PD */
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GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
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GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
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/* PE */
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GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
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GPIO_PE1, GPIO_PE0,
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/* PF */
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GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
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GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
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/* PG */
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GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
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GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
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/* PH */
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GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
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GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
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/* PJ */
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GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
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GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
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GPIO_FN_CDE,
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GPIO_FN_ETH_MAGIC,
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GPIO_FN_DISP,
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GPIO_FN_ETH_LINK,
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GPIO_FN_DR5,
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GPIO_FN_ETH_TX_ER,
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GPIO_FN_DR4,
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GPIO_FN_ETH_TX_EN,
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GPIO_FN_DR3,
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GPIO_FN_ETH_TXD3,
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GPIO_FN_DR2,
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GPIO_FN_ETH_TXD2,
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GPIO_FN_DR1,
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GPIO_FN_ETH_TXD1,
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GPIO_FN_DR0,
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GPIO_FN_ETH_TXD0,
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GPIO_FN_VSYNC,
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GPIO_FN_HSPI_CLK,
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GPIO_FN_ODDF,
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GPIO_FN_HSPI_CS,
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GPIO_FN_DG5,
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GPIO_FN_ETH_MDIO,
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GPIO_FN_DG4,
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GPIO_FN_ETH_RX_CLK,
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GPIO_FN_DG3,
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GPIO_FN_ETH_MDC,
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GPIO_FN_DG2,
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GPIO_FN_ETH_COL,
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GPIO_FN_DG1,
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GPIO_FN_ETH_TX_CLK,
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GPIO_FN_DG0,
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GPIO_FN_ETH_CRS,
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GPIO_FN_DCLKIN,
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GPIO_FN_HSPI_RX,
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GPIO_FN_HSYNC,
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GPIO_FN_HSPI_TX,
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GPIO_FN_DB5,
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GPIO_FN_ETH_RXD3,
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GPIO_FN_DB4,
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GPIO_FN_ETH_RXD2,
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GPIO_FN_DB3,
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GPIO_FN_ETH_RXD1,
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GPIO_FN_DB2,
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GPIO_FN_ETH_RXD0,
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GPIO_FN_DB1,
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GPIO_FN_ETH_RX_DV,
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GPIO_FN_DB0,
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GPIO_FN_ETH_RX_ER,
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GPIO_FN_DCLKOUT,
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GPIO_FN_SCIF1_SLK,
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GPIO_FN_SCIF1_RXD,
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GPIO_FN_SCIF1_TXD,
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GPIO_FN_DACK1,
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GPIO_FN_BACK,
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GPIO_FN_FALE,
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GPIO_FN_DACK0,
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GPIO_FN_FCLE,
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GPIO_FN_DREQ1,
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GPIO_FN_BREQ,
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GPIO_FN_USB_OVC1,
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GPIO_FN_DREQ0,
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GPIO_FN_USB_OVC0,
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GPIO_FN_USB_PENC1,
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GPIO_FN_USB_PENC0,
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GPIO_FN_HAC1_SDOUT,
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GPIO_FN_SSI1_SDATA,
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GPIO_FN_SDIF1CMD,
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GPIO_FN_HAC1_SDIN,
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GPIO_FN_SSI1_SCK,
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GPIO_FN_SDIF1CD,
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GPIO_FN_HAC1_SYNC,
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GPIO_FN_SSI1_WS,
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GPIO_FN_SDIF1WP,
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GPIO_FN_HAC1_BITCLK,
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GPIO_FN_SSI1_CLK,
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GPIO_FN_SDIF1CLK,
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GPIO_FN_HAC0_SDOUT,
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GPIO_FN_SSI0_SDATA,
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GPIO_FN_SDIF1D3,
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GPIO_FN_HAC0_SDIN,
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GPIO_FN_SSI0_SCK,
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GPIO_FN_SDIF1D2,
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GPIO_FN_HAC0_SYNC,
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GPIO_FN_SSI0_WS,
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GPIO_FN_SDIF1D1,
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GPIO_FN_HAC0_BITCLK,
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GPIO_FN_SSI0_CLK,
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GPIO_FN_SDIF1D0,
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GPIO_FN_SCIF3_SCK,
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GPIO_FN_SSI2_SDATA,
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GPIO_FN_SCIF3_RXD,
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GPIO_FN_TCLK,
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GPIO_FN_SSI2_SCK,
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GPIO_FN_SCIF3_TXD,
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GPIO_FN_HAC_RES,
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GPIO_FN_SSI2_WS,
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GPIO_FN_DACK3,
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GPIO_FN_SDIF0CMD,
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GPIO_FN_DACK2,
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GPIO_FN_SDIF0CD,
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GPIO_FN_DREQ3,
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GPIO_FN_SDIF0WP,
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GPIO_FN_SCIF0_CTS,
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GPIO_FN_DREQ2,
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GPIO_FN_SDIF0CLK,
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GPIO_FN_SCIF0_RTS,
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GPIO_FN_IRL7,
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GPIO_FN_SDIF0D3,
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GPIO_FN_SCIF0_SCK,
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GPIO_FN_IRL6,
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GPIO_FN_SDIF0D2,
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GPIO_FN_SCIF0_RXD,
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GPIO_FN_IRL5,
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GPIO_FN_SDIF0D1,
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GPIO_FN_SCIF0_TXD,
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GPIO_FN_IRL4,
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GPIO_FN_SDIF0D0,
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GPIO_FN_SCIF5_SCK,
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GPIO_FN_FRB,
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GPIO_FN_SCIF5_RXD,
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GPIO_FN_IOIS16,
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GPIO_FN_SCIF5_TXD,
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GPIO_FN_CE2B,
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GPIO_FN_DRAK3,
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GPIO_FN_CE2A,
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GPIO_FN_SCIF4_SCK,
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GPIO_FN_DRAK2,
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GPIO_FN_SSI3_WS,
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GPIO_FN_SCIF4_RXD,
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GPIO_FN_DRAK1,
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GPIO_FN_SSI3_SDATA,
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GPIO_FN_FSTATUS,
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GPIO_FN_SCIF4_TXD,
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GPIO_FN_DRAK0,
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GPIO_FN_SSI3_SCK,
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GPIO_FN_FSE,
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};
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#endif /* __CPU_SH7786_H__ */
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@ -129,6 +129,13 @@ int __init detect_cpu_and_cache_system(void)
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boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
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CPU_HAS_LLSC;
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break;
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case 0x4004:
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boot_cpu_data.type = CPU_SH7786;
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
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CPU_HAS_LLSC;
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break;
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case 0x3008:
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.dcache.ways = 4;
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@ -7,6 +7,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
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@ -21,6 +22,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
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@ -31,6 +33,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
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obj-y += $(clock-y)
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obj-$(CONFIG_SMP) += $(smp-y)
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148
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
Normal file
148
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
Normal file
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@ -0,0 +1,148 @@
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/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7786.c
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*
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* SH7786 support for the clock framework
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*
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* Copyright (C) 2008, 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on SH7785
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* Copyright (C) 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static int ifc_divisors[] = { 1, 2, 4, 1 };
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static int sfc_divisors[] = { 1, 1, 4, 1 };
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static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
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24, 32, 1, 1, 1, 1, 1, 1 };
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static int mfc_divisors[] = { 1, 1, 4, 1 };
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static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
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24, 32, 1, 48, 1, 1, 1, 1 };
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
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}
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static struct clk_ops sh7786_master_clk_ops = {
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.init = master_clk_init,
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};
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static void module_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQMR1) & 0x000f);
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clk->rate = clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7786_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static void bus_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
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clk->rate = clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops sh7786_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static void cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
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clk->rate = clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops sh7786_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7786_clk_ops[] = {
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&sh7786_master_clk_ops,
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&sh7786_module_clk_ops,
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&sh7786_bus_clk_ops,
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&sh7786_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7786_clk_ops))
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*ops = sh7786_clk_ops[idx];
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}
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static void shyway_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
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clk->rate = clk->parent->rate / sfc_divisors[idx];
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}
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static struct clk_ops sh7786_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk sh7786_shyway_clk = {
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.name = "shyway_clk",
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.flags = CLK_ALWAYS_ENABLED,
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.ops = &sh7786_shyway_clk_ops,
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};
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static void ddr_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
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clk->rate = clk->parent->rate / mfc_divisors[idx];
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}
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static struct clk_ops sh7786_ddr_clk_ops = {
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.recalc = ddr_clk_recalc,
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};
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static struct clk sh7786_ddr_clk = {
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.name = "ddr_clk",
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.flags = CLK_ALWAYS_ENABLED,
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.ops = &sh7786_ddr_clk_ops,
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};
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/*
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* Additional SH7786-specific on-chip clocks that aren't already part of the
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* clock framework
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*/
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static struct clk *sh7786_onchip_clocks[] = {
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&sh7786_shyway_clk,
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&sh7786_ddr_clk,
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};
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static int __init sh7786_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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int i;
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for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
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struct clk *clkp = sh7786_onchip_clocks[i];
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clkp->parent = clk;
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clk_register(clkp);
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clk_enable(clkp);
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}
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/*
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* Now that we have the rest of the clocks registered, we need to
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* force the parent clock to propagate so that these clocks will
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* automatically figure out their rate. We cheat by handing the
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* parent clock its current rate and forcing child propagation.
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*/
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clk_set_rate(clk, clk_get_rate(clk));
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clk_put(clk);
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return 0;
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}
|
||||
arch_initcall(sh7786_clk_init);
|
||||
950
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
Normal file
950
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
Normal file
|
|
@ -0,0 +1,950 @@
|
|||
/*
|
||||
* SH7786 Pinmux
|
||||
*
|
||||
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Based on SH7785 pinmux
|
||||
*
|
||||
* Copyright (C) 2008 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <cpu/sh7786.h>
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
||||
PINMUX_DATA_BEGIN,
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
|
||||
PE7_DATA, PE6_DATA,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA,
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA,
|
||||
PINMUX_DATA_END,
|
||||
|
||||
PINMUX_INPUT_BEGIN,
|
||||
PA7_IN, PA6_IN, PA5_IN, PA4_IN,
|
||||
PA3_IN, PA2_IN, PA1_IN, PA0_IN,
|
||||
PB7_IN, PB6_IN, PB5_IN, PB4_IN,
|
||||
PB3_IN, PB2_IN, PB1_IN, PB0_IN,
|
||||
PC7_IN, PC6_IN, PC5_IN, PC4_IN,
|
||||
PC3_IN, PC2_IN, PC1_IN, PC0_IN,
|
||||
PD7_IN, PD6_IN, PD5_IN, PD4_IN,
|
||||
PD3_IN, PD2_IN, PD1_IN, PD0_IN,
|
||||
PE7_IN, PE6_IN,
|
||||
PF7_IN, PF6_IN, PF5_IN, PF4_IN,
|
||||
PF3_IN, PF2_IN, PF1_IN, PF0_IN,
|
||||
PG7_IN, PG6_IN, PG5_IN,
|
||||
PH7_IN, PH6_IN, PH5_IN, PH4_IN,
|
||||
PH3_IN, PH2_IN, PH1_IN, PH0_IN,
|
||||
PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
|
||||
PJ3_IN, PJ2_IN, PJ1_IN,
|
||||
PINMUX_INPUT_END,
|
||||
|
||||
PINMUX_INPUT_PULLUP_BEGIN,
|
||||
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
|
||||
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
|
||||
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
|
||||
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
|
||||
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
|
||||
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
|
||||
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
|
||||
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
|
||||
PE7_IN_PU, PE6_IN_PU,
|
||||
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
|
||||
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
|
||||
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
|
||||
PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
|
||||
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
|
||||
PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
|
||||
PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
|
||||
PINMUX_INPUT_PULLUP_END,
|
||||
|
||||
PINMUX_OUTPUT_BEGIN,
|
||||
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
|
||||
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
|
||||
PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
|
||||
PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
|
||||
PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
|
||||
PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
|
||||
PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
|
||||
PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
|
||||
PE7_OUT, PE6_OUT,
|
||||
PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
|
||||
PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
|
||||
PG7_OUT, PG6_OUT, PG5_OUT,
|
||||
PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
|
||||
PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
|
||||
PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
|
||||
PJ3_OUT, PJ2_OUT, PJ1_OUT,
|
||||
PINMUX_OUTPUT_END,
|
||||
|
||||
PINMUX_FUNCTION_BEGIN,
|
||||
PA7_FN, PA6_FN, PA5_FN, PA4_FN,
|
||||
PA3_FN, PA2_FN, PA1_FN, PA0_FN,
|
||||
PB7_FN, PB6_FN, PB5_FN, PB4_FN,
|
||||
PB3_FN, PB2_FN, PB1_FN, PB0_FN,
|
||||
PC7_FN, PC6_FN, PC5_FN, PC4_FN,
|
||||
PC3_FN, PC2_FN, PC1_FN, PC0_FN,
|
||||
PD7_FN, PD6_FN, PD5_FN, PD4_FN,
|
||||
PD3_FN, PD2_FN, PD1_FN, PD0_FN,
|
||||
PE7_FN, PE6_FN,
|
||||
PF7_FN, PF6_FN, PF5_FN, PF4_FN,
|
||||
PF3_FN, PF2_FN, PF1_FN, PF0_FN,
|
||||
PG7_FN, PG6_FN, PG5_FN,
|
||||
PH7_FN, PH6_FN, PH5_FN, PH4_FN,
|
||||
PH3_FN, PH2_FN, PH1_FN, PH0_FN,
|
||||
PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
|
||||
PJ3_FN, PJ2_FN, PJ1_FN,
|
||||
P1MSEL14_0, P1MSEL14_1,
|
||||
P1MSEL13_0, P1MSEL13_1,
|
||||
P1MSEL12_0, P1MSEL12_1,
|
||||
P1MSEL11_0, P1MSEL11_1,
|
||||
P1MSEL10_0, P1MSEL10_1,
|
||||
P1MSEL9_0, P1MSEL9_1,
|
||||
P1MSEL8_0, P1MSEL8_1,
|
||||
P1MSEL7_0, P1MSEL7_1,
|
||||
P1MSEL6_0, P1MSEL6_1,
|
||||
P1MSEL5_0, P1MSEL5_1,
|
||||
P1MSEL4_0, P1MSEL4_1,
|
||||
P1MSEL3_0, P1MSEL3_1,
|
||||
P1MSEL2_0, P1MSEL2_1,
|
||||
P1MSEL1_0, P1MSEL1_1,
|
||||
P1MSEL0_0, P1MSEL0_1,
|
||||
|
||||
P2MSEL15_0, P2MSEL15_1,
|
||||
P2MSEL14_0, P2MSEL14_1,
|
||||
P2MSEL13_0, P2MSEL13_1,
|
||||
P2MSEL12_0, P2MSEL12_1,
|
||||
P2MSEL11_0, P2MSEL11_1,
|
||||
P2MSEL10_0, P2MSEL10_1,
|
||||
P2MSEL9_0, P2MSEL9_1,
|
||||
P2MSEL8_0, P2MSEL8_1,
|
||||
P2MSEL7_0, P2MSEL7_1,
|
||||
P2MSEL6_0, P2MSEL6_1,
|
||||
P2MSEL5_0, P2MSEL5_1,
|
||||
P2MSEL4_0, P2MSEL4_1,
|
||||
P2MSEL3_0, P2MSEL3_1,
|
||||
P2MSEL2_0, P2MSEL2_1,
|
||||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1,
|
||||
PINMUX_FUNCTION_END,
|
||||
|
||||
PINMUX_MARK_BEGIN,
|
||||
CDE_MARK,
|
||||
ETH_MAGIC_MARK,
|
||||
DISP_MARK,
|
||||
ETH_LINK_MARK,
|
||||
DR5_MARK,
|
||||
ETH_TX_ER_MARK,
|
||||
DR4_MARK,
|
||||
ETH_TX_EN_MARK,
|
||||
DR3_MARK,
|
||||
ETH_TXD3_MARK,
|
||||
DR2_MARK,
|
||||
ETH_TXD2_MARK,
|
||||
DR1_MARK,
|
||||
ETH_TXD1_MARK,
|
||||
DR0_MARK,
|
||||
ETH_TXD0_MARK,
|
||||
|
||||
VSYNC_MARK,
|
||||
HSPI_CLK_MARK,
|
||||
ODDF_MARK,
|
||||
HSPI_CS_MARK,
|
||||
DG5_MARK,
|
||||
ETH_MDIO_MARK,
|
||||
DG4_MARK,
|
||||
ETH_RX_CLK_MARK,
|
||||
DG3_MARK,
|
||||
ETH_MDC_MARK,
|
||||
DG2_MARK,
|
||||
ETH_COL_MARK,
|
||||
DG1_MARK,
|
||||
ETH_TX_CLK_MARK,
|
||||
DG0_MARK,
|
||||
ETH_CRS_MARK,
|
||||
|
||||
DCLKIN_MARK,
|
||||
HSPI_RX_MARK,
|
||||
HSYNC_MARK,
|
||||
HSPI_TX_MARK,
|
||||
DB5_MARK,
|
||||
ETH_RXD3_MARK,
|
||||
DB4_MARK,
|
||||
ETH_RXD2_MARK,
|
||||
DB3_MARK,
|
||||
ETH_RXD1_MARK,
|
||||
DB2_MARK,
|
||||
ETH_RXD0_MARK,
|
||||
DB1_MARK,
|
||||
ETH_RX_DV_MARK,
|
||||
DB0_MARK,
|
||||
ETH_RX_ER_MARK,
|
||||
|
||||
DCLKOUT_MARK,
|
||||
SCIF1_SLK_MARK,
|
||||
SCIF1_RXD_MARK,
|
||||
SCIF1_TXD_MARK,
|
||||
DACK1_MARK,
|
||||
BACK_MARK,
|
||||
FALE_MARK,
|
||||
DACK0_MARK,
|
||||
FCLE_MARK,
|
||||
DREQ1_MARK,
|
||||
BREQ_MARK,
|
||||
USB_OVC1_MARK,
|
||||
DREQ0_MARK,
|
||||
USB_OVC0_MARK,
|
||||
|
||||
USB_PENC1_MARK,
|
||||
USB_PENC0_MARK,
|
||||
|
||||
HAC1_SDOUT_MARK,
|
||||
SSI1_SDATA_MARK,
|
||||
SDIF1CMD_MARK,
|
||||
HAC1_SDIN_MARK,
|
||||
SSI1_SCK_MARK,
|
||||
SDIF1CD_MARK,
|
||||
HAC1_SYNC_MARK,
|
||||
SSI1_WS_MARK,
|
||||
SDIF1WP_MARK,
|
||||
HAC1_BITCLK_MARK,
|
||||
SSI1_CLK_MARK,
|
||||
SDIF1CLK_MARK,
|
||||
HAC0_SDOUT_MARK,
|
||||
SSI0_SDATA_MARK,
|
||||
SDIF1D3_MARK,
|
||||
HAC0_SDIN_MARK,
|
||||
SSI0_SCK_MARK,
|
||||
SDIF1D2_MARK,
|
||||
HAC0_SYNC_MARK,
|
||||
SSI0_WS_MARK,
|
||||
SDIF1D1_MARK,
|
||||
HAC0_BITCLK_MARK,
|
||||
SSI0_CLK_MARK,
|
||||
SDIF1D0_MARK,
|
||||
|
||||
SCIF3_SCK_MARK,
|
||||
SSI2_SDATA_MARK,
|
||||
SCIF3_RXD_MARK,
|
||||
TCLK_MARK,
|
||||
SSI2_SCK_MARK,
|
||||
SCIF3_TXD_MARK,
|
||||
HAC_RES_MARK,
|
||||
SSI2_WS_MARK,
|
||||
|
||||
DACK3_MARK,
|
||||
SDIF0CMD_MARK,
|
||||
DACK2_MARK,
|
||||
SDIF0CD_MARK,
|
||||
DREQ3_MARK,
|
||||
SDIF0WP_MARK,
|
||||
SCIF0_CTS_MARK,
|
||||
DREQ2_MARK,
|
||||
SDIF0CLK_MARK,
|
||||
SCIF0_RTS_MARK,
|
||||
IRL7_MARK,
|
||||
SDIF0D3_MARK,
|
||||
SCIF0_SCK_MARK,
|
||||
IRL6_MARK,
|
||||
SDIF0D2_MARK,
|
||||
SCIF0_RXD_MARK,
|
||||
IRL5_MARK,
|
||||
SDIF0D1_MARK,
|
||||
SCIF0_TXD_MARK,
|
||||
IRL4_MARK,
|
||||
SDIF0D0_MARK,
|
||||
|
||||
SCIF5_SCK_MARK,
|
||||
FRB_MARK,
|
||||
SCIF5_RXD_MARK,
|
||||
IOIS16_MARK,
|
||||
SCIF5_TXD_MARK,
|
||||
CE2B_MARK,
|
||||
DRAK3_MARK,
|
||||
CE2A_MARK,
|
||||
SCIF4_SCK_MARK,
|
||||
DRAK2_MARK,
|
||||
SSI3_WS_MARK,
|
||||
SCIF4_RXD_MARK,
|
||||
DRAK1_MARK,
|
||||
SSI3_SDATA_MARK,
|
||||
FSTATUS_MARK,
|
||||
SCIF4_TXD_MARK,
|
||||
DRAK0_MARK,
|
||||
SSI3_SCK_MARK,
|
||||
FSE_MARK,
|
||||
PINMUX_MARK_END,
|
||||
};
|
||||
|
||||
static pinmux_enum_t pinmux_data[] = {
|
||||
|
||||
/* PA GPIO */
|
||||
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
|
||||
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
|
||||
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
|
||||
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
|
||||
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
|
||||
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
|
||||
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
|
||||
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
|
||||
|
||||
/* PB GPIO */
|
||||
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
|
||||
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
|
||||
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
|
||||
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
|
||||
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
|
||||
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
|
||||
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
|
||||
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
|
||||
|
||||
/* PC GPIO */
|
||||
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
|
||||
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
|
||||
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
|
||||
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
|
||||
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
|
||||
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
|
||||
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
|
||||
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
|
||||
|
||||
/* PD GPIO */
|
||||
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
|
||||
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
|
||||
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
|
||||
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
|
||||
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
|
||||
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
|
||||
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
|
||||
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
|
||||
|
||||
/* PE GPIO */
|
||||
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
|
||||
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
|
||||
|
||||
/* PF GPIO */
|
||||
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
|
||||
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
|
||||
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
|
||||
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
|
||||
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
|
||||
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
|
||||
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
|
||||
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
|
||||
|
||||
/* PG GPIO */
|
||||
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
|
||||
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
|
||||
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
|
||||
|
||||
/* PH GPIO */
|
||||
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
|
||||
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
|
||||
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
|
||||
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
|
||||
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
|
||||
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
|
||||
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
|
||||
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
|
||||
|
||||
/* PJ GPIO */
|
||||
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
|
||||
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
|
||||
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
|
||||
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
|
||||
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
|
||||
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
|
||||
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
|
||||
|
||||
/* PA FN */
|
||||
PINMUX_MARK_BEGIN,
|
||||
PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
|
||||
PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
|
||||
PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
|
||||
PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
|
||||
PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
|
||||
PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
|
||||
PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
|
||||
PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
|
||||
PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
|
||||
PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
|
||||
PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
|
||||
PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
|
||||
PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
|
||||
PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
|
||||
PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
|
||||
PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
|
||||
|
||||
/* PB FN */
|
||||
PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
|
||||
PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
|
||||
PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
|
||||
PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
|
||||
PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
|
||||
PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
|
||||
PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
|
||||
PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
|
||||
PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
|
||||
PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
|
||||
PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
|
||||
PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
|
||||
PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
|
||||
PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
|
||||
PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
|
||||
PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
|
||||
|
||||
/* PC FN */
|
||||
PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
|
||||
PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
|
||||
PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
|
||||
PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
|
||||
PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
|
||||
PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
|
||||
PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
|
||||
PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
|
||||
|
||||
PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
|
||||
PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
|
||||
PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
|
||||
PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
|
||||
PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
|
||||
PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
|
||||
PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
|
||||
PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
|
||||
|
||||
/* PD FN */
|
||||
PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
|
||||
PINMUX_DATA(SCIF1_SLK_MARK, PD6_FN),
|
||||
PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
|
||||
PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
|
||||
PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
|
||||
PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
|
||||
PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
|
||||
PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
|
||||
PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
|
||||
PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
|
||||
PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
|
||||
PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
|
||||
PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
|
||||
PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
|
||||
|
||||
/* PE FN */
|
||||
PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
|
||||
PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
|
||||
|
||||
/* PF FN */
|
||||
PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
|
||||
PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
|
||||
PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
|
||||
PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
|
||||
PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
|
||||
PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
|
||||
PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
|
||||
PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
|
||||
PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
|
||||
PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
|
||||
PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
|
||||
PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
|
||||
PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
|
||||
PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
|
||||
PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
|
||||
PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
|
||||
PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
|
||||
PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
|
||||
PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
|
||||
PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
|
||||
PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
|
||||
PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
|
||||
PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
|
||||
PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
|
||||
|
||||
/* PG FN */
|
||||
PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
|
||||
PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
|
||||
PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
|
||||
PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
|
||||
PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
|
||||
PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
|
||||
PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
|
||||
PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
|
||||
|
||||
/* PH FN */
|
||||
PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
|
||||
PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
|
||||
PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
|
||||
PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
|
||||
PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
|
||||
PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
|
||||
PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
|
||||
PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
|
||||
PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
|
||||
PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
|
||||
PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
|
||||
PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
|
||||
PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
|
||||
PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
|
||||
PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
|
||||
PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
|
||||
PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
|
||||
PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
|
||||
PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
|
||||
PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
|
||||
PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
|
||||
|
||||
/* PJ FN */
|
||||
PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
|
||||
PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
|
||||
PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
|
||||
PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
|
||||
PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
|
||||
PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
|
||||
PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
|
||||
PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
|
||||
PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
|
||||
PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
|
||||
PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
|
||||
PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
|
||||
PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
|
||||
PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
|
||||
PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
|
||||
PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
|
||||
PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
|
||||
PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
|
||||
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
|
||||
};
|
||||
|
||||
static struct pinmux_gpio pinmux_gpios[] = {
|
||||
/* PA */
|
||||
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
|
||||
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
|
||||
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
|
||||
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
|
||||
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
|
||||
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
|
||||
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
|
||||
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
|
||||
|
||||
/* PB */
|
||||
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
|
||||
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
|
||||
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
|
||||
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
|
||||
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
|
||||
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
|
||||
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
|
||||
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
|
||||
|
||||
/* PC */
|
||||
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
|
||||
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
|
||||
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
|
||||
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
|
||||
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
|
||||
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
|
||||
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
|
||||
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
|
||||
|
||||
/* PD */
|
||||
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
|
||||
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
|
||||
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
|
||||
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
|
||||
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
|
||||
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
|
||||
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
|
||||
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
|
||||
|
||||
/* PE */
|
||||
PINMUX_GPIO(GPIO_PE5, PE7_DATA),
|
||||
PINMUX_GPIO(GPIO_PE4, PE6_DATA),
|
||||
|
||||
/* PF */
|
||||
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
|
||||
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
|
||||
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
|
||||
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
|
||||
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
|
||||
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
|
||||
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
|
||||
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
|
||||
|
||||
/* PG */
|
||||
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
|
||||
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
|
||||
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
|
||||
|
||||
/* PH */
|
||||
PINMUX_GPIO(GPIO_PH7, PH7_DATA),
|
||||
PINMUX_GPIO(GPIO_PH6, PH6_DATA),
|
||||
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
|
||||
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
|
||||
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
|
||||
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
|
||||
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
|
||||
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
|
||||
|
||||
/* PJ */
|
||||
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
|
||||
|
||||
/* FN */
|
||||
PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_SLK, SCIF1_SLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
|
||||
};
|
||||
|
||||
static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
|
||||
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
|
||||
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
|
||||
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
|
||||
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
|
||||
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
|
||||
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
|
||||
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
|
||||
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
|
||||
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
|
||||
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
|
||||
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
|
||||
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
|
||||
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
|
||||
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
|
||||
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
|
||||
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
|
||||
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
|
||||
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
|
||||
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
|
||||
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
|
||||
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
|
||||
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
|
||||
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
|
||||
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
|
||||
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
|
||||
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
|
||||
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
|
||||
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
|
||||
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
|
||||
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
|
||||
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
|
||||
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
|
||||
PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
|
||||
PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
|
||||
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
|
||||
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
|
||||
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
|
||||
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
|
||||
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
|
||||
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
|
||||
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
|
||||
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
|
||||
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
|
||||
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
|
||||
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
|
||||
PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
|
||||
PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
|
||||
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
|
||||
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
|
||||
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
|
||||
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
|
||||
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
|
||||
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
|
||||
PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
|
||||
PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
|
||||
PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
|
||||
PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
|
||||
PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
|
||||
PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
|
||||
PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
|
||||
0, 0,
|
||||
P1MSEL14_0, P1MSEL14_1,
|
||||
P1MSEL13_0, P1MSEL13_1,
|
||||
P1MSEL12_0, P1MSEL12_1,
|
||||
P1MSEL11_0, P1MSEL11_1,
|
||||
P1MSEL10_0, P1MSEL10_1,
|
||||
P1MSEL9_0, P1MSEL9_1,
|
||||
P1MSEL8_0, P1MSEL8_1,
|
||||
P1MSEL7_0, P1MSEL7_1,
|
||||
P1MSEL6_0, P1MSEL6_1,
|
||||
P1MSEL5_0, P1MSEL5_1,
|
||||
P1MSEL4_0, P1MSEL4_1,
|
||||
P1MSEL3_0, P1MSEL3_1,
|
||||
P1MSEL2_0, P1MSEL2_1,
|
||||
P1MSEL1_0, P1MSEL1_1,
|
||||
P1MSEL0_0, P1MSEL0_1 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
|
||||
P2MSEL15_0, P2MSEL15_1,
|
||||
P2MSEL14_0, P2MSEL14_1,
|
||||
P2MSEL13_0, P2MSEL13_1,
|
||||
P2MSEL12_0, P2MSEL12_1,
|
||||
P2MSEL11_0, P2MSEL11_1,
|
||||
P2MSEL10_0, P2MSEL10_1,
|
||||
P2MSEL9_0, P2MSEL9_1,
|
||||
P2MSEL8_0, P2MSEL8_1,
|
||||
P2MSEL7_0, P2MSEL7_1,
|
||||
P2MSEL6_0, P2MSEL6_1,
|
||||
P2MSEL5_0, P2MSEL5_1,
|
||||
P2MSEL4_0, P2MSEL4_1,
|
||||
P2MSEL3_0, P2MSEL3_1,
|
||||
P2MSEL2_0, P2MSEL2_1,
|
||||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1 }
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
|
||||
PE7_DATA, PE6_DATA,
|
||||
0, 0, 0, 0, 0, 0 }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, 0,
|
||||
0, 0, 0, 0 }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct pinmux_info sh7786_pinmux_info = {
|
||||
.name = "sh7786_pfc",
|
||||
.reserved_id = PINMUX_RESERVED,
|
||||
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
|
||||
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
|
||||
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
|
||||
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
.first_gpio = GPIO_PA7,
|
||||
.last_gpio = GPIO_FN_FSE,
|
||||
|
||||
.gpios = pinmux_gpios,
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.data_regs = pinmux_data_regs,
|
||||
|
||||
.gpio_data = pinmux_data,
|
||||
.gpio_data_size = ARRAY_SIZE(pinmux_data),
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return register_pinmux(&sh7786_pinmux_info);
|
||||
}
|
||||
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
407
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
Normal file
407
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
Normal file
|
|
@ -0,0 +1,407 @@
|
|||
/*
|
||||
* SH7786 Setup
|
||||
*
|
||||
* Copyright (C) 2009 Renesas Solutions Corp.
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Based on SH7785 Setup
|
||||
*
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/mmzone.h>
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffea0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
},
|
||||
/*
|
||||
* The rest of these all have multiplexed IRQs
|
||||
*/
|
||||
{
|
||||
.mapbase = 0xffeb0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 44, 44, 44, 44 },
|
||||
}, {
|
||||
.mapbase = 0xffec0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 50, 50, 50, 50 },
|
||||
}, {
|
||||
.mapbase = 0xffed0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 51, 51, 51, 51 },
|
||||
}, {
|
||||
.mapbase = 0xffee0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 52, 52, 52, 52 },
|
||||
}, {
|
||||
.mapbase = 0xffef0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 53, 53, 53, 53 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *sh7786_devices[] __initdata = {
|
||||
&sci_device,
|
||||
};
|
||||
|
||||
static int __init sh7786_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7786_devices,
|
||||
ARRAY_SIZE(sh7786_devices));
|
||||
}
|
||||
device_initcall(sh7786_devices_setup);
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
|
||||
IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
|
||||
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
|
||||
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
|
||||
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
|
||||
|
||||
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
|
||||
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
|
||||
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
|
||||
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
|
||||
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
WDT,
|
||||
TMU0_0, TMU0_1, TMU0_2, TMU0_3,
|
||||
TMU1_0, TMU1_1, TMU1_2,
|
||||
DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
|
||||
HUDI1, HUDI0,
|
||||
DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
|
||||
HPB_0, HPB_1, HPB_2,
|
||||
SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
|
||||
SCIF1,
|
||||
TMU2, TMU3,
|
||||
SCIF2, SCIF3, SCIF4, SCIF5,
|
||||
Eth_0, Eth_1,
|
||||
PCIeC0_0, PCIeC0_1, PCIeC0_2,
|
||||
PCIeC1_0, PCIeC1_1, PCIeC1_2,
|
||||
USB,
|
||||
I2C0, I2C1,
|
||||
DU,
|
||||
SSI0, SSI1, SSI2, SSI3,
|
||||
PCIeC2_0, PCIeC2_1, PCIeC2_2,
|
||||
HAC0, HAC1,
|
||||
FLCTL,
|
||||
HSPI,
|
||||
GPIO0, GPIO1,
|
||||
Thermal,
|
||||
INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
|
||||
|
||||
/* interrupt groups */
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(WDT, 0x3e0),
|
||||
INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
|
||||
INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
|
||||
INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
|
||||
INTC_VECT(TMU1_2, 0x4c0),
|
||||
INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
|
||||
INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
|
||||
INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
|
||||
INTC_VECT(DMAC0_6, 0x5c0),
|
||||
INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
|
||||
INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
|
||||
INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
|
||||
INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
|
||||
INTC_VECT(HPB_2, 0x6e0),
|
||||
INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
|
||||
INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
|
||||
INTC_VECT(SCIF1, 0x780),
|
||||
INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
|
||||
INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
|
||||
INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
|
||||
INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
|
||||
INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
|
||||
INTC_VECT(PCIeC0_2, 0xb20),
|
||||
INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
|
||||
INTC_VECT(PCIeC1_2, 0xb80),
|
||||
INTC_VECT(USB, 0xba0),
|
||||
INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
|
||||
INTC_VECT(DU, 0xd00),
|
||||
INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
|
||||
INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
|
||||
INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
|
||||
INTC_VECT(PCIeC2_2, 0xde0),
|
||||
INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
|
||||
INTC_VECT(FLCTL, 0xe40),
|
||||
INTC_VECT(HSPI, 0xe80),
|
||||
INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
|
||||
INTC_VECT(Thermal, 0xee0),
|
||||
};
|
||||
|
||||
/* FIXME: Main CPU support only now */
|
||||
#if 1 /* Main CPU */
|
||||
#define CnINTMSK0 0xfe410030
|
||||
#define CnINTMSK1 0xfe410040
|
||||
#define CnINTMSKCLR0 0xfe410050
|
||||
#define CnINTMSKCLR1 0xfe410060
|
||||
#define CnINT2MSKR0 0xfe410a20
|
||||
#define CnINT2MSKR1 0xfe410a24
|
||||
#define CnINT2MSKR2 0xfe410a28
|
||||
#define CnINT2MSKR3 0xfe410a2c
|
||||
#define CnINT2MSKCR0 0xfe410a30
|
||||
#define CnINT2MSKCR1 0xfe410a34
|
||||
#define CnINT2MSKCR2 0xfe410a38
|
||||
#define CnINT2MSKCR3 0xfe410a3c
|
||||
#else /* Sub CPU */
|
||||
#define CnINTMSK0 0xfe410034
|
||||
#define CnINTMSK1 0xfe410044
|
||||
#define CnINTMSKCLR0 0xfe410054
|
||||
#define CnINTMSKCLR1 0xfe410064
|
||||
#define CnINT2MSKR0 0xfe410b20
|
||||
#define CnINT2MSKR1 0xfe410b24
|
||||
#define CnINT2MSKR2 0xfe410b28
|
||||
#define CnINT2MSKR3 0xfe410b2c
|
||||
#define CnINT2MSKCR0 0xfe410b30
|
||||
#define CnINT2MSKCR1 0xfe410b34
|
||||
#define CnINT2MSKCR2 0xfe410b38
|
||||
#define CnINT2MSKCR3 0xfe410b3c
|
||||
#endif
|
||||
|
||||
#define INTMSK2 0xfe410068
|
||||
#define INTMSKCLR2 0xfe41006c
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ CnINTMSK0, CnINTMSKCLR0, 32,
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ INTMSK2, INTMSKCLR2, 32,
|
||||
{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
|
||||
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
|
||||
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
|
||||
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
|
||||
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
|
||||
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
|
||||
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
|
||||
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
|
||||
{ CnINT2MSKR0, CnINT2MSKCR0 , 32,
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
|
||||
{ CnINT2MSKR1, CnINT2MSKCR1, 32,
|
||||
{ TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
|
||||
DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
|
||||
HUDI1, HUDI0,
|
||||
DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
|
||||
HPB_0, HPB_1, HPB_2,
|
||||
SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
|
||||
SCIF1,
|
||||
TMU2, TMU3, 0, } },
|
||||
{ CnINT2MSKR2, CnINT2MSKCR2, 32,
|
||||
{ 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
|
||||
Eth_0, Eth_1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PCIeC0_0, PCIeC0_1, PCIeC0_2,
|
||||
PCIeC1_0, PCIeC1_1, PCIeC1_2,
|
||||
USB, 0, 0 } },
|
||||
{ CnINT2MSKR3, CnINT2MSKCR3, 32,
|
||||
{ 0, 0, 0, 0, 0, 0,
|
||||
I2C0, I2C1,
|
||||
DU, SSI0, SSI1, SSI2, SSI3,
|
||||
PCIeC2_0, PCIeC2_1, PCIeC2_2,
|
||||
HAC0, HAC1,
|
||||
FLCTL, 0,
|
||||
HSPI, GPIO0, GPIO1, Thermal,
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
|
||||
{ 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
|
||||
TMU0_2, TMU0_3 } },
|
||||
{ 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
|
||||
TMU1_2, 0 } },
|
||||
{ 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
|
||||
DMAC0_2, DMAC0_3 } },
|
||||
{ 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
|
||||
DMAC0_6, HUDI1 } },
|
||||
{ 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
|
||||
DMAC1_1, DMAC1_2 } },
|
||||
{ 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
|
||||
HPB_1, HPB_2 } },
|
||||
{ 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
|
||||
SCIF0_2, SCIF0_3 } },
|
||||
{ 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
|
||||
{ 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
|
||||
{ 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
|
||||
Eth_0, Eth_1 } },
|
||||
{ 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
|
||||
{ 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
|
||||
PCIeC1_0, PCIeC1_1 } },
|
||||
{ 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
|
||||
{ 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
|
||||
{ 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
|
||||
{ 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
|
||||
PCIeC2_1, PCIeC2_2 } },
|
||||
{ 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
|
||||
{ 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
|
||||
GPIO1, Thermal } },
|
||||
{ 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
/* Support for external interrupt pins in IRQ mode */
|
||||
|
||||
static struct intc_vect vectors_irq0123[] __initdata = {
|
||||
INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
|
||||
INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irq4567[] __initdata = {
|
||||
INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
|
||||
INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_sense_reg sense_registers[] __initdata = {
|
||||
{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg ack_registers[] __initdata = {
|
||||
{ 0xfe410024, 0, 32, /* INTREQ */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
|
||||
vectors_irq0123, NULL, mask_registers,
|
||||
prio_registers, sense_registers, ack_registers);
|
||||
|
||||
static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
|
||||
vectors_irq4567, NULL, mask_registers,
|
||||
prio_registers, sense_registers, ack_registers);
|
||||
|
||||
/* External interrupt pins in IRL mode */
|
||||
|
||||
static struct intc_vect vectors_irl0123[] __initdata = {
|
||||
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
|
||||
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
|
||||
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
|
||||
INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
|
||||
INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
|
||||
INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
|
||||
INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
|
||||
INTC_VECT(IRL0_HHHL, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irl4567[] __initdata = {
|
||||
INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
|
||||
INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
|
||||
INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
|
||||
INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
|
||||
INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
|
||||
INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
|
||||
INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
|
||||
INTC_VECT(IRL4_HHHL, 0xac0),
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
|
||||
NULL, mask_registers, NULL, NULL);
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
|
||||
NULL, mask_registers, NULL, NULL);
|
||||
|
||||
#define INTC_ICR0 0xfe410000
|
||||
#define INTC_INTMSK0 CnINTMSK0
|
||||
#define INTC_INTMSK1 CnINTMSK1
|
||||
#define INTC_INTMSK2 INTMSK2
|
||||
#define INTC_INTMSKCLR1 CnINTMSKCLR1
|
||||
#define INTC_INTMSKCLR2 INTMSKCLR2
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
/* disable IRQ3-0 + IRQ7-4 */
|
||||
ctrl_outl(0xff000000, INTC_INTMSK0);
|
||||
|
||||
/* disable IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(0xc0000000, INTC_INTMSK1);
|
||||
ctrl_outl(0xfffefffe, INTC_INTMSK2);
|
||||
|
||||
/* select IRL mode for IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
|
||||
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
void __init plat_irq_setup_pins(int mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case IRQ_MODE_IRQ7654:
|
||||
/* select IRQ mode for IRL7-4 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
|
||||
register_intc_controller(&intc_desc_irq4567);
|
||||
break;
|
||||
case IRQ_MODE_IRQ3210:
|
||||
/* select IRQ mode for IRL3-0 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
|
||||
register_intc_controller(&intc_desc_irq0123);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654:
|
||||
/* enable IRL7-4 but don't provide any masking */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210:
|
||||
/* enable IRL0-3 but don't provide any masking */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654_MASK:
|
||||
/* enable IRL7-4 and mask using cpu intc controller */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_desc_irl4567);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210_MASK:
|
||||
/* enable IRL0-3 and mask using cpu intc controller */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_desc_irl0123);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -432,6 +432,7 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
|
||||
[CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
|
||||
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
|
||||
[CPU_SH7786] = "SH7786",
|
||||
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
|
||||
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
|
||||
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
|
||||
|
|
|
|||
|
|
@ -244,6 +244,7 @@ static int tmu_timer_init(void)
|
|||
!defined(CONFIG_CPU_SUBTYPE_SH7721) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7786) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -107,6 +107,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
|
|||
case CPU_SH7780:
|
||||
case CPU_SH7781:
|
||||
case CPU_SH7785:
|
||||
case CPU_SH7786:
|
||||
case CPU_SH7723:
|
||||
case CPU_SHX3:
|
||||
lmodel = &op_model_sh4a_ops;
|
||||
|
|
|
|||
|
|
@ -263,6 +263,7 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
|
|||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
|
||||
{
|
||||
|
|
@ -284,7 +285,8 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
|
|||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
static inline int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
|
||||
|
|
|
|||
|
|
@ -126,7 +126,8 @@
|
|||
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
|
||||
|
|
@ -182,6 +183,7 @@
|
|||
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
|
||||
#else
|
||||
|
|
@ -413,7 +415,8 @@ SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
|
|||
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
||||
|
|
@ -644,7 +647,8 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffea0000)
|
||||
|
|
@ -746,7 +750,8 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
*/
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
|
|
|
|||
Loading…
Reference in a new issue