mfd: sec-core: Add support for S2MPU02 device
Add support for Samsung S2MPU02 PMIC device to the MFD sec-core driver. The S2MPU02 device includes PMIC/RTC/Clock devices. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Chanwoo Choi
Lee Jones
parent
10f9edaeaa
commit
54e8827d5f
5 changed files with 352 additions and 30 deletions
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@ -89,6 +89,15 @@ static const struct mfd_cell s2mpa01_devs[] = {
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},
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};
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static const struct mfd_cell s2mpu02_devs[] = {
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{ .name = "s2mpu02-pmic", },
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{ .name = "s2mpu02-rtc", },
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{
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.name = "s2mpu02-clk",
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.of_compatible = "samsung,s2mpu02-clk",
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}
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};
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#ifdef CONFIG_OF
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static const struct of_device_id sec_dt_match[] = {
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{ .compatible = "samsung,s5m8767-pmic",
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@ -102,6 +111,9 @@ static const struct of_device_id sec_dt_match[] = {
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}, {
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.compatible = "samsung,s2mpa01-pmic",
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.data = (void *)S2MPA01,
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}, {
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.compatible = "samsung,s2mpu02-pmic",
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.data = (void *)S2MPU02,
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}, {
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/* Sentinel */
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},
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@ -250,9 +262,10 @@ static int sec_pmic_probe(struct i2c_client *i2c,
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{
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struct sec_platform_data *pdata = dev_get_platdata(&i2c->dev);
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const struct regmap_config *regmap;
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const struct mfd_cell *sec_devs;
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struct sec_pmic_dev *sec_pmic;
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unsigned long device_type;
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int ret;
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int ret, num_sec_devs;
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sec_pmic = devm_kzalloc(&i2c->dev, sizeof(struct sec_pmic_dev),
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GFP_KERNEL);
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@ -319,34 +332,39 @@ static int sec_pmic_probe(struct i2c_client *i2c,
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switch (sec_pmic->device_type) {
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case S5M8751X:
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ret = mfd_add_devices(sec_pmic->dev, -1, s5m8751_devs,
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ARRAY_SIZE(s5m8751_devs), NULL, 0, NULL);
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sec_devs = s5m8751_devs;
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num_sec_devs = ARRAY_SIZE(s5m8751_devs);
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break;
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case S5M8763X:
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ret = mfd_add_devices(sec_pmic->dev, -1, s5m8763_devs,
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ARRAY_SIZE(s5m8763_devs), NULL, 0, NULL);
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sec_devs = s5m8763_devs;
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num_sec_devs = ARRAY_SIZE(s5m8763_devs);
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break;
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case S5M8767X:
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ret = mfd_add_devices(sec_pmic->dev, -1, s5m8767_devs,
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ARRAY_SIZE(s5m8767_devs), NULL, 0, NULL);
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sec_devs = s5m8767_devs;
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num_sec_devs = ARRAY_SIZE(s5m8767_devs);
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break;
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case S2MPA01:
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ret = mfd_add_devices(sec_pmic->dev, -1, s2mpa01_devs,
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ARRAY_SIZE(s2mpa01_devs), NULL, 0, NULL);
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sec_devs = s2mpa01_devs;
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num_sec_devs = ARRAY_SIZE(s2mpa01_devs);
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break;
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case S2MPS11X:
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ret = mfd_add_devices(sec_pmic->dev, -1, s2mps11_devs,
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ARRAY_SIZE(s2mps11_devs), NULL, 0, NULL);
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sec_devs = s2mps11_devs;
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num_sec_devs = ARRAY_SIZE(s2mps11_devs);
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break;
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case S2MPS14X:
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ret = mfd_add_devices(sec_pmic->dev, -1, s2mps14_devs,
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ARRAY_SIZE(s2mps14_devs), NULL, 0, NULL);
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sec_devs = s2mps14_devs;
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num_sec_devs = ARRAY_SIZE(s2mps14_devs);
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break;
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case S2MPU02:
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sec_devs = s2mpu02_devs;
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num_sec_devs = ARRAY_SIZE(s2mpu02_devs);
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break;
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default:
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/* If this happens the probe function is problem */
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BUG();
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}
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ret = mfd_add_devices(sec_pmic->dev, -1, sec_devs, num_sec_devs, NULL,
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0, NULL);
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if (ret)
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goto err_mfd;
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@ -20,6 +20,7 @@
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#include <linux/mfd/samsung/irq.h>
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#include <linux/mfd/samsung/s2mps11.h>
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#include <linux/mfd/samsung/s2mps14.h>
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#include <linux/mfd/samsung/s2mpu02.h>
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#include <linux/mfd/samsung/s5m8763.h>
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#include <linux/mfd/samsung/s5m8767.h>
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@ -161,6 +162,77 @@ static const struct regmap_irq s2mps14_irqs[] = {
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},
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};
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static const struct regmap_irq s2mpu02_irqs[] = {
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[S2MPU02_IRQ_PWRONF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRONF_MASK,
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},
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[S2MPU02_IRQ_PWRONR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRONR_MASK,
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},
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[S2MPU02_IRQ_JIGONBF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_JIGONBF_MASK,
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},
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[S2MPU02_IRQ_JIGONBR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_JIGONBR_MASK,
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},
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[S2MPU02_IRQ_ACOKBF] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_ACOKBF_MASK,
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},
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[S2MPU02_IRQ_ACOKBR] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_ACOKBR_MASK,
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},
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[S2MPU02_IRQ_PWRON1S] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_PWRON1S_MASK,
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},
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[S2MPU02_IRQ_MRB] = {
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.reg_offset = 0,
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.mask = S2MPS11_IRQ_MRB_MASK,
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},
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[S2MPU02_IRQ_RTC60S] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTC60S_MASK,
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},
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[S2MPU02_IRQ_RTCA1] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA1_MASK,
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},
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[S2MPU02_IRQ_RTCA0] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA0_MASK,
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},
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[S2MPU02_IRQ_SMPL] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_SMPL_MASK,
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},
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[S2MPU02_IRQ_RTC1S] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTC1S_MASK,
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},
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[S2MPU02_IRQ_WTSR] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_WTSR_MASK,
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},
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[S2MPU02_IRQ_INT120C] = {
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.reg_offset = 2,
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.mask = S2MPS11_IRQ_INT120C_MASK,
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},
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[S2MPU02_IRQ_INT140C] = {
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.reg_offset = 2,
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.mask = S2MPS11_IRQ_INT140C_MASK,
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},
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[S2MPU02_IRQ_TSD] = {
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.reg_offset = 2,
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.mask = S2MPS14_IRQ_TSD_MASK,
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},
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};
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static const struct regmap_irq s5m8767_irqs[] = {
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[S5M8767_IRQ_PWRR] = {
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.reg_offset = 0,
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@ -327,6 +399,16 @@ static const struct regmap_irq_chip s2mps14_irq_chip = {
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.ack_base = S2MPS14_REG_INT1,
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};
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static const struct regmap_irq_chip s2mpu02_irq_chip = {
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.name = "s2mpu02",
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.irqs = s2mpu02_irqs,
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.num_irqs = ARRAY_SIZE(s2mpu02_irqs),
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.num_regs = 3,
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.status_base = S2MPU02_REG_INT1,
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.mask_base = S2MPU02_REG_INT1M,
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.ack_base = S2MPU02_REG_INT1,
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};
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static const struct regmap_irq_chip s5m8767_irq_chip = {
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.name = "s5m8767",
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.irqs = s5m8767_irqs,
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@ -351,6 +433,7 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
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{
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int ret = 0;
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int type = sec_pmic->device_type;
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const struct regmap_irq_chip *sec_irq_chip;
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if (!sec_pmic->irq) {
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dev_warn(sec_pmic->dev,
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@ -361,28 +444,19 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
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switch (type) {
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case S5M8763X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s5m8763_irq_chip,
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&sec_pmic->irq_data);
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sec_irq_chip = &s5m8763_irq_chip;
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break;
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case S5M8767X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s5m8767_irq_chip,
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&sec_pmic->irq_data);
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sec_irq_chip = &s5m8767_irq_chip;
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break;
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case S2MPS11X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s2mps11_irq_chip,
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&sec_pmic->irq_data);
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sec_irq_chip = &s2mps11_irq_chip;
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break;
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case S2MPS14X:
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, &s2mps14_irq_chip,
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&sec_pmic->irq_data);
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sec_irq_chip = &s2mps14_irq_chip;
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break;
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case S2MPU02:
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sec_irq_chip = &s2mpu02_irq_chip;
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break;
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default:
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dev_err(sec_pmic->dev, "Unknown device type %lu\n",
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@ -390,6 +464,10 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
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return -EINVAL;
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}
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ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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sec_pmic->irq_base, sec_irq_chip,
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&sec_pmic->irq_data);
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if (ret != 0) {
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dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
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return ret;
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@ -21,6 +21,7 @@ enum sec_device_type {
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S2MPA01,
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S2MPS11X,
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S2MPS14X,
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S2MPU02,
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};
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/**
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@ -129,6 +129,30 @@ enum s2mps14_irq {
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S2MPS14_IRQ_NR,
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};
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enum s2mpu02_irq {
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S2MPU02_IRQ_PWRONF,
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S2MPU02_IRQ_PWRONR,
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S2MPU02_IRQ_JIGONBF,
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S2MPU02_IRQ_JIGONBR,
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S2MPU02_IRQ_ACOKBF,
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S2MPU02_IRQ_ACOKBR,
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S2MPU02_IRQ_PWRON1S,
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S2MPU02_IRQ_MRB,
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S2MPU02_IRQ_RTC60S,
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S2MPU02_IRQ_RTCA1,
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S2MPU02_IRQ_RTCA0,
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S2MPU02_IRQ_SMPL,
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S2MPU02_IRQ_RTC1S,
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S2MPU02_IRQ_WTSR,
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S2MPU02_IRQ_INT120C,
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S2MPU02_IRQ_INT140C,
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S2MPU02_IRQ_TSD,
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S2MPU02_IRQ_NR,
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};
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/* Masks for interrupts are the same as in s2mps11 */
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#define S2MPS14_IRQ_TSD_MASK (1 << 2)
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201
include/linux/mfd/samsung/s2mpu02.h
Normal file
201
include/linux/mfd/samsung/s2mpu02.h
Normal file
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@ -0,0 +1,201 @@
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/*
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* s2mpu02.h
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __LINUX_MFD_S2MPU02_H
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#define __LINUX_MFD_S2MPU02_H
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/* S2MPU02 registers */
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enum S2MPU02_reg {
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S2MPU02_REG_ID,
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S2MPU02_REG_INT1,
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S2MPU02_REG_INT2,
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S2MPU02_REG_INT3,
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S2MPU02_REG_INT1M,
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S2MPU02_REG_INT2M,
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S2MPU02_REG_INT3M,
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S2MPU02_REG_ST1,
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S2MPU02_REG_ST2,
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S2MPU02_REG_PWRONSRC,
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S2MPU02_REG_OFFSRC,
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S2MPU02_REG_BU_CHG,
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S2MPU02_REG_RTCCTRL,
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S2MPU02_REG_PMCTRL1,
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S2MPU02_REG_RSVD1,
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S2MPU02_REG_RSVD2,
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S2MPU02_REG_RSVD3,
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S2MPU02_REG_RSVD4,
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S2MPU02_REG_RSVD5,
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S2MPU02_REG_RSVD6,
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S2MPU02_REG_RSVD7,
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S2MPU02_REG_WRSTEN,
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S2MPU02_REG_RSVD8,
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S2MPU02_REG_RSVD9,
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S2MPU02_REG_RSVD10,
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S2MPU02_REG_B1CTRL1,
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S2MPU02_REG_B1CTRL2,
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S2MPU02_REG_B2CTRL1,
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S2MPU02_REG_B2CTRL2,
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S2MPU02_REG_B3CTRL1,
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S2MPU02_REG_B3CTRL2,
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S2MPU02_REG_B4CTRL1,
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S2MPU02_REG_B4CTRL2,
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S2MPU02_REG_B5CTRL1,
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S2MPU02_REG_B5CTRL2,
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S2MPU02_REG_B5CTRL3,
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S2MPU02_REG_B5CTRL4,
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S2MPU02_REG_B5CTRL5,
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S2MPU02_REG_B6CTRL1,
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S2MPU02_REG_B6CTRL2,
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S2MPU02_REG_B7CTRL1,
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S2MPU02_REG_B7CTRL2,
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S2MPU02_REG_RAMP1,
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S2MPU02_REG_RAMP2,
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S2MPU02_REG_L1CTRL,
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S2MPU02_REG_L2CTRL1,
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S2MPU02_REG_L2CTRL2,
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S2MPU02_REG_L2CTRL3,
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S2MPU02_REG_L2CTRL4,
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S2MPU02_REG_L3CTRL,
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S2MPU02_REG_L4CTRL,
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S2MPU02_REG_L5CTRL,
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S2MPU02_REG_L6CTRL,
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S2MPU02_REG_L7CTRL,
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S2MPU02_REG_L8CTRL,
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S2MPU02_REG_L9CTRL,
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S2MPU02_REG_L10CTRL,
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S2MPU02_REG_L11CTRL,
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S2MPU02_REG_L12CTRL,
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S2MPU02_REG_L13CTRL,
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S2MPU02_REG_L14CTRL,
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S2MPU02_REG_L15CTRL,
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S2MPU02_REG_L16CTRL,
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S2MPU02_REG_L17CTRL,
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S2MPU02_REG_L18CTRL,
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S2MPU02_REG_L19CTRL,
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S2MPU02_REG_L20CTRL,
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S2MPU02_REG_L21CTRL,
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S2MPU02_REG_L22CTRL,
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S2MPU02_REG_L23CTRL,
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S2MPU02_REG_L24CTRL,
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S2MPU02_REG_L25CTRL,
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S2MPU02_REG_L26CTRL,
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S2MPU02_REG_L27CTRL,
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S2MPU02_REG_L28CTRL,
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S2MPU02_REG_LDODSCH1,
|
||||
S2MPU02_REG_LDODSCH2,
|
||||
S2MPU02_REG_LDODSCH3,
|
||||
S2MPU02_REG_LDODSCH4,
|
||||
S2MPU02_REG_SELMIF,
|
||||
S2MPU02_REG_RSVD11,
|
||||
S2MPU02_REG_RSVD12,
|
||||
S2MPU02_REG_RSVD13,
|
||||
S2MPU02_REG_DVSSEL,
|
||||
S2MPU02_REG_DVSPTR,
|
||||
S2MPU02_REG_DVSDATA,
|
||||
};
|
||||
|
||||
/* S2MPU02 regulator ids */
|
||||
enum S2MPU02_regulators {
|
||||
S2MPU02_LDO1,
|
||||
S2MPU02_LDO2,
|
||||
S2MPU02_LDO3,
|
||||
S2MPU02_LDO4,
|
||||
S2MPU02_LDO5,
|
||||
S2MPU02_LDO6,
|
||||
S2MPU02_LDO7,
|
||||
S2MPU02_LDO8,
|
||||
S2MPU02_LDO9,
|
||||
S2MPU02_LDO10,
|
||||
S2MPU02_LDO11,
|
||||
S2MPU02_LDO12,
|
||||
S2MPU02_LDO13,
|
||||
S2MPU02_LDO14,
|
||||
S2MPU02_LDO15,
|
||||
S2MPU02_LDO16,
|
||||
S2MPU02_LDO17,
|
||||
S2MPU02_LDO18,
|
||||
S2MPU02_LDO19,
|
||||
S2MPU02_LDO20,
|
||||
S2MPU02_LDO21,
|
||||
S2MPU02_LDO22,
|
||||
S2MPU02_LDO23,
|
||||
S2MPU02_LDO24,
|
||||
S2MPU02_LDO25,
|
||||
S2MPU02_LDO26,
|
||||
S2MPU02_LDO27,
|
||||
S2MPU02_LDO28,
|
||||
S2MPU02_BUCK1,
|
||||
S2MPU02_BUCK2,
|
||||
S2MPU02_BUCK3,
|
||||
S2MPU02_BUCK4,
|
||||
S2MPU02_BUCK5,
|
||||
S2MPU02_BUCK6,
|
||||
S2MPU02_BUCK7,
|
||||
|
||||
S2MPU02_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
/* Regulator constraints for BUCKx */
|
||||
#define S2MPU02_BUCK1234_MIN_600MV 600000
|
||||
#define S2MPU02_BUCK5_MIN_1081_25MV 1081250
|
||||
#define S2MPU02_BUCK6_MIN_1700MV 1700000
|
||||
#define S2MPU02_BUCK7_MIN_900MV 900000
|
||||
|
||||
#define S2MPU02_BUCK1234_STEP_6_25MV 6250
|
||||
#define S2MPU02_BUCK5_STEP_6_25MV 6250
|
||||
#define S2MPU02_BUCK6_STEP_2_50MV 2500
|
||||
#define S2MPU02_BUCK7_STEP_6_25MV 6250
|
||||
|
||||
#define S2MPU02_BUCK1234_START_SEL 0x00
|
||||
#define S2MPU02_BUCK5_START_SEL 0x4D
|
||||
#define S2MPU02_BUCK6_START_SEL 0x28
|
||||
#define S2MPU02_BUCK7_START_SEL 0x30
|
||||
|
||||
#define S2MPU02_BUCK_RAMP_DELAY 12500
|
||||
|
||||
/* Regulator constraints for different types of LDOx */
|
||||
#define S2MPU02_LDO_MIN_900MV 900000
|
||||
#define S2MPU02_LDO_MIN_1050MV 1050000
|
||||
#define S2MPU02_LDO_MIN_1600MV 1600000
|
||||
#define S2MPU02_LDO_STEP_12_5MV 12500
|
||||
#define S2MPU02_LDO_STEP_25MV 25000
|
||||
#define S2MPU02_LDO_STEP_50MV 50000
|
||||
|
||||
#define S2MPU02_LDO_GROUP1_START_SEL 0x8
|
||||
#define S2MPU02_LDO_GROUP2_START_SEL 0xA
|
||||
#define S2MPU02_LDO_GROUP3_START_SEL 0x10
|
||||
|
||||
#define S2MPU02_LDO_VSEL_MASK 0x3F
|
||||
#define S2MPU02_BUCK_VSEL_MASK 0xFF
|
||||
#define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_ENABLE_SHIFT 6
|
||||
|
||||
/* On/Off controlled by PWREN */
|
||||
#define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1)
|
||||
#define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1)
|
||||
|
||||
/* RAMP delay for BUCK1234*/
|
||||
#define S2MPU02_BUCK1_RAMP_SHIFT 6
|
||||
#define S2MPU02_BUCK2_RAMP_SHIFT 4
|
||||
#define S2MPU02_BUCK3_RAMP_SHIFT 2
|
||||
#define S2MPU02_BUCK4_RAMP_SHIFT 0
|
||||
#define S2MPU02_BUCK1234_RAMP_MASK 0x3
|
||||
|
||||
#endif /* __LINUX_MFD_S2MPU02_H */
|
||||
Loading…
Reference in a new issue