Merge branch 'topic/sun6i' into for-linus
This commit is contained in:
Vinod Koul
commit
53b84bad9e
1 changed files with 188 additions and 66 deletions
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@ -146,6 +146,8 @@ struct sun6i_vchan {
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struct dma_slave_config cfg;
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struct sun6i_pchan *phy;
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u8 port;
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u8 irq_type;
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bool cyclic;
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};
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struct sun6i_dma_dev {
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@ -254,6 +256,30 @@ static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
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return addr_width >> 1;
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}
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static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
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{
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struct sun6i_desc *txd = pchan->desc;
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struct sun6i_dma_lli *lli;
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size_t bytes;
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dma_addr_t pos;
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pos = readl(pchan->base + DMA_CHAN_LLI_ADDR);
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bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
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if (pos == LLI_LAST_ITEM)
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return bytes;
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for (lli = txd->v_lli; lli; lli = lli->v_lli_next) {
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if (lli->p_lli_next == pos) {
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for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next)
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bytes += lli->len;
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break;
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}
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}
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return bytes;
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}
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static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
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struct sun6i_dma_lli *next,
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dma_addr_t next_phy,
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@ -276,45 +302,6 @@ static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
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return next;
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}
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static inline int sun6i_dma_cfg_lli(struct sun6i_dma_lli *lli,
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dma_addr_t src,
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dma_addr_t dst, u32 len,
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struct dma_slave_config *config)
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{
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u8 src_width, dst_width, src_burst, dst_burst;
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if (!config)
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return -EINVAL;
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src_burst = convert_burst(config->src_maxburst);
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if (src_burst)
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return src_burst;
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dst_burst = convert_burst(config->dst_maxburst);
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if (dst_burst)
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return dst_burst;
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src_width = convert_buswidth(config->src_addr_width);
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if (src_width)
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return src_width;
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dst_width = convert_buswidth(config->dst_addr_width);
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if (dst_width)
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return dst_width;
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lli->cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |
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DMA_CHAN_CFG_SRC_WIDTH(src_width) |
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DMA_CHAN_CFG_DST_BURST(dst_burst) |
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DMA_CHAN_CFG_DST_WIDTH(dst_width);
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lli->src = src;
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lli->dst = dst;
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lli->len = len;
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lli->para = NORMAL_WAIT;
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return 0;
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}
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static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
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struct sun6i_dma_lli *lli)
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{
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@ -381,9 +368,13 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
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irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
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irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
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irq_val = readl(sdev->base + DMA_IRQ_EN(irq_offset));
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irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH);
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writel(irq_val, sdev->base + DMA_IRQ_EN(irq_offset));
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vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE;
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irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg));
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irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) <<
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(irq_offset * DMA_IRQ_CHAN_WIDTH));
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irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH);
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writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
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writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
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writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
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@ -479,11 +470,12 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
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writel(status, sdev->base + DMA_IRQ_STAT(i));
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for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
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if (status & DMA_IRQ_QUEUE) {
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pchan = sdev->pchans + j;
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vchan = pchan->vchan;
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if (vchan) {
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pchan = sdev->pchans + j;
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vchan = pchan->vchan;
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if (vchan && (status & vchan->irq_type)) {
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if (vchan->cyclic) {
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vchan_cyclic_callback(&pchan->desc->vd);
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} else {
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spin_lock(&vchan->vc.lock);
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vchan_cookie_complete(&pchan->desc->vd);
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pchan->done = pchan->desc;
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@ -502,6 +494,55 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
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return ret;
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}
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static int set_config(struct sun6i_dma_dev *sdev,
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struct dma_slave_config *sconfig,
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enum dma_transfer_direction direction,
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u32 *p_cfg)
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{
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s8 src_width, dst_width, src_burst, dst_burst;
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switch (direction) {
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case DMA_MEM_TO_DEV:
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src_burst = convert_burst(sconfig->src_maxburst ?
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sconfig->src_maxburst : 8);
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src_width = convert_buswidth(sconfig->src_addr_width !=
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DMA_SLAVE_BUSWIDTH_UNDEFINED ?
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sconfig->src_addr_width :
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DMA_SLAVE_BUSWIDTH_4_BYTES);
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dst_burst = convert_burst(sconfig->dst_maxburst);
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dst_width = convert_buswidth(sconfig->dst_addr_width);
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break;
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case DMA_DEV_TO_MEM:
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src_burst = convert_burst(sconfig->src_maxburst);
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src_width = convert_buswidth(sconfig->src_addr_width);
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dst_burst = convert_burst(sconfig->dst_maxburst ?
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sconfig->dst_maxburst : 8);
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dst_width = convert_buswidth(sconfig->dst_addr_width !=
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DMA_SLAVE_BUSWIDTH_UNDEFINED ?
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sconfig->dst_addr_width :
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DMA_SLAVE_BUSWIDTH_4_BYTES);
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break;
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default:
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return -EINVAL;
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}
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if (src_burst < 0)
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return src_burst;
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if (src_width < 0)
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return src_width;
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if (dst_burst < 0)
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return dst_burst;
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if (dst_width < 0)
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return dst_width;
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*p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |
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DMA_CHAN_CFG_SRC_WIDTH(src_width) |
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DMA_CHAN_CFG_DST_BURST(dst_burst) |
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DMA_CHAN_CFG_DST_WIDTH(dst_width);
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return 0;
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}
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static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
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struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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size_t len, unsigned long flags)
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@ -569,13 +610,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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struct sun6i_desc *txd;
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struct scatterlist *sg;
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dma_addr_t p_lli;
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u32 lli_cfg;
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int i, ret;
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if (!sgl)
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return NULL;
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if (!is_slave_direction(dir)) {
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dev_err(chan2dev(chan), "Invalid DMA direction\n");
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ret = set_config(sdev, sconfig, dir, &lli_cfg);
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if (ret) {
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dev_err(chan2dev(chan), "Invalid DMA configuration\n");
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return NULL;
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}
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@ -588,14 +631,14 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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if (!v_lli)
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goto err_lli_free;
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if (dir == DMA_MEM_TO_DEV) {
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ret = sun6i_dma_cfg_lli(v_lli, sg_dma_address(sg),
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sconfig->dst_addr, sg_dma_len(sg),
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sconfig);
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if (ret)
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goto err_cur_lli_free;
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v_lli->len = sg_dma_len(sg);
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v_lli->para = NORMAL_WAIT;
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v_lli->cfg |= DMA_CHAN_CFG_DST_IO_MODE |
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if (dir == DMA_MEM_TO_DEV) {
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v_lli->src = sg_dma_address(sg);
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v_lli->dst = sconfig->dst_addr;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_IO_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_DST_DRQ(vchan->port);
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@ -607,13 +650,10 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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sg_dma_len(sg), flags);
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} else {
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ret = sun6i_dma_cfg_lli(v_lli, sconfig->src_addr,
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sg_dma_address(sg), sg_dma_len(sg),
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sconfig);
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if (ret)
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goto err_cur_lli_free;
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v_lli->cfg |= DMA_CHAN_CFG_DST_LINEAR_MODE |
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v_lli->src = sconfig->src_addr;
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v_lli->dst = sg_dma_address(sg);
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_IO_MODE |
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DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_SRC_DRQ(vchan->port);
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@ -634,8 +674,78 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
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err_cur_lli_free:
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dma_pool_free(sdev->pool, v_lli, p_lli);
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err_lli_free:
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for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
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dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
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kfree(txd);
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return NULL;
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}
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static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
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struct dma_chan *chan,
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dma_addr_t buf_addr,
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size_t buf_len,
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size_t period_len,
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enum dma_transfer_direction dir,
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unsigned long flags)
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{
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struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
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struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
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struct dma_slave_config *sconfig = &vchan->cfg;
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struct sun6i_dma_lli *v_lli, *prev = NULL;
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struct sun6i_desc *txd;
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dma_addr_t p_lli;
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u32 lli_cfg;
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unsigned int i, periods = buf_len / period_len;
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int ret;
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ret = set_config(sdev, sconfig, dir, &lli_cfg);
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if (ret) {
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dev_err(chan2dev(chan), "Invalid DMA configuration\n");
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return NULL;
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}
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txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
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if (!txd)
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return NULL;
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for (i = 0; i < periods; i++) {
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v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
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if (!v_lli) {
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dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
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goto err_lli_free;
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}
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v_lli->len = period_len;
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v_lli->para = NORMAL_WAIT;
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if (dir == DMA_MEM_TO_DEV) {
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v_lli->src = buf_addr + period_len * i;
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v_lli->dst = sconfig->dst_addr;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_IO_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_DST_DRQ(vchan->port);
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} else {
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v_lli->src = sconfig->src_addr;
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v_lli->dst = buf_addr + period_len * i;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_IO_MODE |
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DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_SRC_DRQ(vchan->port);
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}
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prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
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}
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prev->p_lli_next = txd->p_lli; /* cyclic list */
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vchan->cyclic = true;
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return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
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err_lli_free:
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for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
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dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
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@ -712,6 +822,16 @@ static int sun6i_dma_terminate_all(struct dma_chan *chan)
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spin_lock_irqsave(&vchan->vc.lock, flags);
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if (vchan->cyclic) {
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vchan->cyclic = false;
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if (pchan && pchan->desc) {
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struct virt_dma_desc *vd = &pchan->desc->vd;
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struct virt_dma_chan *vc = &vchan->vc;
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list_add_tail(&vd->node, &vc->desc_completed);
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}
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}
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vchan_get_all_descriptors(&vchan->vc, &head);
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if (pchan) {
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@ -759,7 +879,7 @@ static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
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} else if (!pchan || !pchan->desc) {
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bytes = 0;
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} else {
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bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
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bytes = sun6i_get_chan_size(pchan);
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}
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spin_unlock_irqrestore(&vchan->vc.lock, flags);
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@ -963,6 +1083,7 @@ static int sun6i_dma_probe(struct platform_device *pdev)
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dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
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dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
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dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
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dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask);
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INIT_LIST_HEAD(&sdc->slave.channels);
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sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources;
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@ -970,6 +1091,7 @@ static int sun6i_dma_probe(struct platform_device *pdev)
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sdc->slave.device_issue_pending = sun6i_dma_issue_pending;
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sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg;
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sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy;
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sdc->slave.device_prep_dma_cyclic = sun6i_dma_prep_dma_cyclic;
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sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES;
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sdc->slave.device_config = sun6i_dma_config;
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sdc->slave.device_pause = sun6i_dma_pause;
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